1 /**
2   ******************************************************************************
3   * @file    stm32f071xb.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32F0xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2016 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 /** @addtogroup CMSIS
27   * @{
28   */
29 
30 /** @addtogroup stm32f071xb
31   * @{
32   */
33 
34 #ifndef __STM32F071xB_H
35 #define __STM32F071xB_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 /**
45  * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
46  */
47 #define __CM0_REV                 0 /*!< Core Revision r0p0                            */
48 #define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
49 #define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
51 
52 /**
53   * @}
54   */
55 
56 /** @addtogroup Peripheral_interrupt_number_definition
57   * @{
58   */
59 
60 /**
61  * @brief STM32F0xx Interrupt Number Definition, according to the selected device
62  *        in @ref Library_configuration_section
63  */
64 
65 /*!< Interrupt Number Definition */
66 typedef enum
67 {
68 /******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */
70   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */
71   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
72   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */
73   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */
74 
75 /******  STM32F0 specific Interrupt Numbers ******************************************************************/
76   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
77   PVD_VDDIO2_IRQn             = 1,      /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31             */
78   RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
79   FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
80   RCC_CRS_IRQn                = 4,      /*!< RCC & CRS global Interrupt                                      */
81   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupt                                     */
82   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupt                                     */
83   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupt                                     */
84   TSC_IRQn                    = 8,      /*!< Touch Sensing Controller Interrupts                             */
85   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
86   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupt                          */
87   DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4 to Channel 7 Interrupt                           */
88   ADC1_COMP_IRQn              = 12,     /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
89   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupt           */
90   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
91   TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                           */
92   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
93   TIM6_DAC_IRQn               = 17,     /*!< TIM6 global and DAC channel underrun error Interrupt            */
94   TIM7_IRQn                   = 18,     /*!< TIM7 global Interrupt                                           */
95   TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
96   TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                          */
97   TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
98   TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
99   I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
100   I2C2_IRQn                   = 24,     /*!< I2C2 Event Interrupt                                            */
101   SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
102   SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
103   USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
104   USART2_IRQn                 = 28,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
105   USART3_4_IRQn               = 29,     /*!< USART3 and USART4 global Interrupt                              */
106   CEC_CAN_IRQn                = 30      /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt           */
107 } IRQn_Type;
108 
109 /**
110   * @}
111   */
112 
113 #include "core_cm0.h"            /* Cortex-M0 processor and core peripherals */
114 #include "system_stm32f0xx.h"    /* STM32F0xx System Header */
115 #include <stdint.h>
116 
117 /** @addtogroup Peripheral_registers_structures
118   * @{
119   */
120 
121 /**
122   * @brief Analog to Digital Converter
123   */
124 
125 typedef struct
126 {
127   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
128   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
129   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
130   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
131   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
132   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
133        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
134        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
135   __IO uint32_t TR;           /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
136        uint32_t RESERVED3;    /*!< Reserved,                                                      0x24 */
137   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
138        uint32_t RESERVED4[5]; /*!< Reserved,                                                      0x2C */
139   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
140 } ADC_TypeDef;
141 
142 typedef struct
143 {
144   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
145 } ADC_Common_TypeDef;
146 
147 /**
148   * @brief HDMI-CEC
149   */
150 
151 typedef struct
152 {
153   __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
154   __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
155   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
156   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
157   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
158   __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
159 }CEC_TypeDef;
160 
161 /**
162   * @brief Comparator
163   */
164 
165 typedef struct
166 {
167   __IO uint16_t CSR;         /*!< COMP control and status register,                                                 Address offset: 0x00 */
168 } COMP_TypeDef;
169 
170 typedef struct
171 {
172   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
173 } COMP_Common_TypeDef;
174 
175 /* Legacy defines */
176 typedef struct
177 {
178   __IO uint32_t CSR;         /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */
179 }COMP1_2_TypeDef;
180 
181 /**
182   * @brief CRC calculation unit
183   */
184 
185 typedef struct
186 {
187   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
188   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
189   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
190   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
191   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
192   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
193   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
194   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
195 } CRC_TypeDef;
196 
197 /**
198   * @brief Clock Recovery System
199   */
200 typedef struct
201 {
202 __IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
203 __IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
204 __IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
205 __IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
206 }CRS_TypeDef;
207 
208 /**
209   * @brief Digital to Analog Converter
210   */
211 
212 typedef struct
213 {
214   __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
215   __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
216   __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
217   __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
218   __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
219   __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
220   __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
221   __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
222   __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
223   __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
224   __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
225   __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
226   __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
227   __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
228 } DAC_TypeDef;
229 
230 /**
231   * @brief Debug MCU
232   */
233 
234 typedef struct
235 {
236   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
237   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
238   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
239   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
240 }DBGMCU_TypeDef;
241 
242 /**
243   * @brief DMA Controller
244   */
245 
246 typedef struct
247 {
248   __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
249   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
250   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
251   __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
252 } DMA_Channel_TypeDef;
253 
254 typedef struct
255 {
256   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
257   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
258 } DMA_TypeDef;
259 
260 /**
261   * @brief External Interrupt/Event Controller
262   */
263 
264 typedef struct
265 {
266   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
267   __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
268   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
269   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
270   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
271   __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
272 } EXTI_TypeDef;
273 
274 /**
275   * @brief FLASH Registers
276   */
277 typedef struct
278 {
279   __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
280   __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
281   __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
282   __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
283   __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
284   __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
285   __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
286   __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
287   __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
288 } FLASH_TypeDef;
289 
290 /**
291   * @brief Option Bytes Registers
292   */
293 typedef struct
294 {
295   __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */
296   __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */
297   __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
298   __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
299   __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */
300   __IO uint16_t WRP1;         /*!< FLASH option byte write protection 1,          Address offset: 0x0A */
301   __IO uint16_t WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C */
302   __IO uint16_t WRP3;         /*!< FLASH option byte write protection 3,          Address offset: 0x0E */
303 } OB_TypeDef;
304 
305 /**
306   * @brief General Purpose I/O
307   */
308 
309 typedef struct
310 {
311   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
312   __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
313   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
314   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
315   __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
316   __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
317   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
318   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
319   __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,  Address offset: 0x20-0x24 */
320   __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
321 } GPIO_TypeDef;
322 
323 /**
324   * @brief SysTem Configuration
325   */
326 
327 typedef struct
328 {
329   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
330        uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
331   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
332   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
333 } SYSCFG_TypeDef;
334 
335 /**
336   * @brief Inter-integrated Circuit Interface
337   */
338 
339 typedef struct
340 {
341   __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
342   __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
343   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
344   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
345   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
346   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
347   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
348   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
349   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
350   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
351   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
352 } I2C_TypeDef;
353 
354 /**
355   * @brief Independent WATCHDOG
356   */
357 
358 typedef struct
359 {
360   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
361   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
362   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
363   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
364   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
365 } IWDG_TypeDef;
366 
367 /**
368   * @brief Power Control
369   */
370 
371 typedef struct
372 {
373   __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
374   __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
375 } PWR_TypeDef;
376 
377 /**
378   * @brief Reset and Clock Control
379   */
380 
381 typedef struct
382 {
383   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
384   __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
385   __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
386   __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
387   __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
388   __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
389   __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
390   __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
391   __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
392   __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
393   __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
394   __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
395   __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
396   __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
397 } RCC_TypeDef;
398 
399 /**
400   * @brief Real-Time Clock
401   */
402 typedef struct
403 {
404   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
405   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
406   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
407   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
408   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
409   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
410        uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x18 */
411   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
412        uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x20 */
413   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
414   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
415   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
416   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
417   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
418   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
419   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
420   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
421   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
422        uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x48 */
423        uint32_t RESERVED4;  /*!< Reserved,                                                  Address offset: 0x4C */
424   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
425   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
426   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
427   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
428   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
429 } RTC_TypeDef;
430 
431 /**
432   * @brief Serial Peripheral Interface
433   */
434 
435 typedef struct
436 {
437   __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
438   __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
439   __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
440   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
441   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
442   __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
443   __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
444   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
445   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
446 } SPI_TypeDef;
447 
448 /**
449   * @brief TIM
450   */
451 typedef struct
452 {
453   __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
454   __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
455   __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
456   __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
457   __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
458   __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
459   __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
460   __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
461   __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
462   __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
463   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
464   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
465   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
466   __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
467   __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
468   __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
469   __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
470   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
471   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
472   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
473   __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
474 } TIM_TypeDef;
475 
476 /**
477   * @brief Touch Sensing Controller (TSC)
478   */
479 typedef struct
480 {
481   __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
482   __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
483   __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */
484   __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
485   __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
486        uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
487   __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
488        uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
489   __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
490        uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
491   __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
492        uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
493   __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
494   __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
495 }TSC_TypeDef;
496 
497 /**
498   * @brief Universal Synchronous Asynchronous Receiver Transmitter
499   */
500 
501 typedef struct
502 {
503   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
504   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
505   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
506   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
507   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
508   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
509   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
510   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
511   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
512   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
513   uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
514   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
515   uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
516 } USART_TypeDef;
517 
518 /**
519   * @brief Window WATCHDOG
520   */
521 typedef struct
522 {
523   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
524   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
525   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
526 } WWDG_TypeDef;
527 
528 /**
529   * @}
530   */
531 
532 /** @addtogroup Peripheral_memory_map
533   * @{
534   */
535 
536 #define FLASH_BASE            0x08000000UL              /*!< FLASH base address in the alias region */
537 #define FLASH_BANK1_END       0x0801FFFFUL /*!< FLASH END address of bank1 */
538 #define SRAM_BASE             0x20000000UL              /*!< SRAM base address in the alias region */
539 #define PERIPH_BASE           0x40000000UL              /*!< Peripheral base address in the alias region */
540 
541 /*!< Peripheral memory map */
542 #define APBPERIPH_BASE        PERIPH_BASE
543 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
544 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
545 
546 /*!< APB peripherals */
547 #define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
548 #define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
549 #define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
550 #define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
551 #define TIM14_BASE            (APBPERIPH_BASE + 0x00002000UL)
552 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
553 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
554 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
555 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
556 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
557 #define USART3_BASE           (APBPERIPH_BASE + 0x00004800UL)
558 #define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
559 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
560 #define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
561 #define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
562 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
563 #define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
564 
565 #define CEC_BASE              (APBPERIPH_BASE + 0x00007800UL)
566 
567 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
568 #define COMP_BASE             (APBPERIPH_BASE + 0x0001001CUL)
569 #define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
570 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
571 #define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
572 #define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00UL)
573 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
574 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
575 #define TIM15_BASE            (APBPERIPH_BASE + 0x00014000UL)
576 #define TIM16_BASE            (APBPERIPH_BASE + 0x00014400UL)
577 #define TIM17_BASE            (APBPERIPH_BASE + 0x00014800UL)
578 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
579 
580 /*!< AHB peripherals */
581 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
582 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
583 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
584 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
585 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
586 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
587 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
588 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
589 
590 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
591 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
592 #define OB_BASE               0x1FFFF800UL       /*!< FLASH Option Bytes base address */
593 #define FLASHSIZE_BASE        0x1FFFF7CCUL       /*!< FLASH Size register base address */
594 #define UID_BASE              0x1FFFF7ACUL       /*!< Unique device ID register base address */
595 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
596 #define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
597 
598 /*!< AHB2 peripherals */
599 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000UL)
600 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400UL)
601 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800UL)
602 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00UL)
603 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000UL)
604 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400UL)
605 
606 /**
607   * @}
608   */
609 
610 /** @addtogroup Peripheral_declaration
611   * @{
612   */
613 
614 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
615 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
616 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
617 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
618 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
619 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
620 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
621 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
622 #define USART2              ((USART_TypeDef *) USART2_BASE)
623 #define USART3              ((USART_TypeDef *) USART3_BASE)
624 #define USART4              ((USART_TypeDef *) USART4_BASE)
625 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
626 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
627 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
628 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
629 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
630 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
631 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
632 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
633 #define COMP1               ((COMP_TypeDef *) COMP_BASE)
634 #define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
635 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)
636 #define COMP                ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */
637 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
638 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
639 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
640 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
641 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
642 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
643 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
644 #define USART1              ((USART_TypeDef *) USART1_BASE)
645 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
646 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
647 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
648 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
649 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
650 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
651 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
652 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
653 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
654 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
655 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
656 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
657 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
658 #define OB                  ((OB_TypeDef *) OB_BASE)
659 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
660 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
661 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
662 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
663 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
664 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
665 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
666 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
667 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
668 /**
669   * @}
670   */
671 
672 /** @addtogroup Exported_constants
673   * @{
674   */
675 
676 /** @addtogroup Hardware_Constant_Definition
677   * @{
678   */
679 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */
680 
681 /**
682   * @}
683   */
684 
685 /** @addtogroup Peripheral_Registers_Bits_Definition
686   * @{
687   */
688 
689 /******************************************************************************/
690 /*                         Peripheral Registers Bits Definition               */
691 /******************************************************************************/
692 
693 /******************************************************************************/
694 /*                                                                            */
695 /*                      Analog to Digital Converter (ADC)                     */
696 /*                                                                            */
697 /******************************************************************************/
698 
699 /*
700  * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
701  */
702 #define ADC_CHANNEL_VBAT_SUPPORT                       /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
703 
704 /********************  Bits definition for ADC_ISR register  ******************/
705 #define ADC_ISR_ADRDY_Pos         (0U)
706 #define ADC_ISR_ADRDY_Msk         (0x1UL << ADC_ISR_ADRDY_Pos)                  /*!< 0x00000001 */
707 #define ADC_ISR_ADRDY             ADC_ISR_ADRDY_Msk                            /*!< ADC ready flag */
708 #define ADC_ISR_EOSMP_Pos         (1U)
709 #define ADC_ISR_EOSMP_Msk         (0x1UL << ADC_ISR_EOSMP_Pos)                  /*!< 0x00000002 */
710 #define ADC_ISR_EOSMP             ADC_ISR_EOSMP_Msk                            /*!< ADC group regular end of sampling flag */
711 #define ADC_ISR_EOC_Pos           (2U)
712 #define ADC_ISR_EOC_Msk           (0x1UL << ADC_ISR_EOC_Pos)                    /*!< 0x00000004 */
713 #define ADC_ISR_EOC               ADC_ISR_EOC_Msk                              /*!< ADC group regular end of unitary conversion flag */
714 #define ADC_ISR_EOS_Pos           (3U)
715 #define ADC_ISR_EOS_Msk           (0x1UL << ADC_ISR_EOS_Pos)                    /*!< 0x00000008 */
716 #define ADC_ISR_EOS               ADC_ISR_EOS_Msk                              /*!< ADC group regular end of sequence conversions flag */
717 #define ADC_ISR_OVR_Pos           (4U)
718 #define ADC_ISR_OVR_Msk           (0x1UL << ADC_ISR_OVR_Pos)                    /*!< 0x00000010 */
719 #define ADC_ISR_OVR               ADC_ISR_OVR_Msk                              /*!< ADC group regular overrun flag */
720 #define ADC_ISR_AWD1_Pos          (7U)
721 #define ADC_ISR_AWD1_Msk          (0x1UL << ADC_ISR_AWD1_Pos)                   /*!< 0x00000080 */
722 #define ADC_ISR_AWD1              ADC_ISR_AWD1_Msk                             /*!< ADC analog watchdog 1 flag */
723 
724 /* Legacy defines */
725 #define ADC_ISR_AWD             (ADC_ISR_AWD1)
726 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
727 
728 /********************  Bits definition for ADC_IER register  ******************/
729 #define ADC_IER_ADRDYIE_Pos       (0U)
730 #define ADC_IER_ADRDYIE_Msk       (0x1UL << ADC_IER_ADRDYIE_Pos)                /*!< 0x00000001 */
731 #define ADC_IER_ADRDYIE           ADC_IER_ADRDYIE_Msk                          /*!< ADC ready interrupt */
732 #define ADC_IER_EOSMPIE_Pos       (1U)
733 #define ADC_IER_EOSMPIE_Msk       (0x1UL << ADC_IER_EOSMPIE_Pos)                /*!< 0x00000002 */
734 #define ADC_IER_EOSMPIE           ADC_IER_EOSMPIE_Msk                          /*!< ADC group regular end of sampling interrupt */
735 #define ADC_IER_EOCIE_Pos         (2U)
736 #define ADC_IER_EOCIE_Msk         (0x1UL << ADC_IER_EOCIE_Pos)                  /*!< 0x00000004 */
737 #define ADC_IER_EOCIE             ADC_IER_EOCIE_Msk                            /*!< ADC group regular end of unitary conversion interrupt */
738 #define ADC_IER_EOSIE_Pos         (3U)
739 #define ADC_IER_EOSIE_Msk         (0x1UL << ADC_IER_EOSIE_Pos)                  /*!< 0x00000008 */
740 #define ADC_IER_EOSIE             ADC_IER_EOSIE_Msk                            /*!< ADC group regular end of sequence conversions interrupt */
741 #define ADC_IER_OVRIE_Pos         (4U)
742 #define ADC_IER_OVRIE_Msk         (0x1UL << ADC_IER_OVRIE_Pos)                  /*!< 0x00000010 */
743 #define ADC_IER_OVRIE             ADC_IER_OVRIE_Msk                            /*!< ADC group regular overrun interrupt */
744 #define ADC_IER_AWD1IE_Pos        (7U)
745 #define ADC_IER_AWD1IE_Msk        (0x1UL << ADC_IER_AWD1IE_Pos)                 /*!< 0x00000080 */
746 #define ADC_IER_AWD1IE            ADC_IER_AWD1IE_Msk                           /*!< ADC analog watchdog 1 interrupt */
747 
748 /* Legacy defines */
749 #define ADC_IER_AWDIE           (ADC_IER_AWD1IE)
750 #define ADC_IER_EOSEQIE         (ADC_IER_EOSIE)
751 
752 /********************  Bits definition for ADC_CR register  *******************/
753 #define ADC_CR_ADEN_Pos           (0U)
754 #define ADC_CR_ADEN_Msk           (0x1UL << ADC_CR_ADEN_Pos)                    /*!< 0x00000001 */
755 #define ADC_CR_ADEN               ADC_CR_ADEN_Msk                              /*!< ADC enable */
756 #define ADC_CR_ADDIS_Pos          (1U)
757 #define ADC_CR_ADDIS_Msk          (0x1UL << ADC_CR_ADDIS_Pos)                   /*!< 0x00000002 */
758 #define ADC_CR_ADDIS              ADC_CR_ADDIS_Msk                             /*!< ADC disable */
759 #define ADC_CR_ADSTART_Pos        (2U)
760 #define ADC_CR_ADSTART_Msk        (0x1UL << ADC_CR_ADSTART_Pos)                 /*!< 0x00000004 */
761 #define ADC_CR_ADSTART            ADC_CR_ADSTART_Msk                           /*!< ADC group regular conversion start */
762 #define ADC_CR_ADSTP_Pos          (4U)
763 #define ADC_CR_ADSTP_Msk          (0x1UL << ADC_CR_ADSTP_Pos)                   /*!< 0x00000010 */
764 #define ADC_CR_ADSTP              ADC_CR_ADSTP_Msk                             /*!< ADC group regular conversion stop */
765 #define ADC_CR_ADCAL_Pos          (31U)
766 #define ADC_CR_ADCAL_Msk          (0x1UL << ADC_CR_ADCAL_Pos)                   /*!< 0x80000000 */
767 #define ADC_CR_ADCAL              ADC_CR_ADCAL_Msk                             /*!< ADC calibration */
768 
769 /*******************  Bits definition for ADC_CFGR1 register  *****************/
770 #define ADC_CFGR1_DMAEN_Pos       (0U)
771 #define ADC_CFGR1_DMAEN_Msk       (0x1UL << ADC_CFGR1_DMAEN_Pos)                /*!< 0x00000001 */
772 #define ADC_CFGR1_DMAEN           ADC_CFGR1_DMAEN_Msk                          /*!< ADC DMA transfer enable */
773 #define ADC_CFGR1_DMACFG_Pos      (1U)
774 #define ADC_CFGR1_DMACFG_Msk      (0x1UL << ADC_CFGR1_DMACFG_Pos)               /*!< 0x00000002 */
775 #define ADC_CFGR1_DMACFG          ADC_CFGR1_DMACFG_Msk                         /*!< ADC DMA transfer configuration */
776 #define ADC_CFGR1_SCANDIR_Pos     (2U)
777 #define ADC_CFGR1_SCANDIR_Msk     (0x1UL << ADC_CFGR1_SCANDIR_Pos)              /*!< 0x00000004 */
778 #define ADC_CFGR1_SCANDIR         ADC_CFGR1_SCANDIR_Msk                        /*!< ADC group regular sequencer scan direction */
779 
780 #define ADC_CFGR1_RES_Pos         (3U)
781 #define ADC_CFGR1_RES_Msk         (0x3UL << ADC_CFGR1_RES_Pos)                  /*!< 0x00000018 */
782 #define ADC_CFGR1_RES             ADC_CFGR1_RES_Msk                            /*!< ADC data resolution */
783 #define ADC_CFGR1_RES_0           (0x1UL << ADC_CFGR1_RES_Pos)                  /*!< 0x00000008 */
784 #define ADC_CFGR1_RES_1           (0x2UL << ADC_CFGR1_RES_Pos)                  /*!< 0x00000010 */
785 
786 #define ADC_CFGR1_ALIGN_Pos       (5U)
787 #define ADC_CFGR1_ALIGN_Msk       (0x1UL << ADC_CFGR1_ALIGN_Pos)                /*!< 0x00000020 */
788 #define ADC_CFGR1_ALIGN           ADC_CFGR1_ALIGN_Msk                          /*!< ADC data alignment */
789 
790 #define ADC_CFGR1_EXTSEL_Pos      (6U)
791 #define ADC_CFGR1_EXTSEL_Msk      (0x7UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x000001C0 */
792 #define ADC_CFGR1_EXTSEL          ADC_CFGR1_EXTSEL_Msk                         /*!< ADC group regular external trigger source */
793 #define ADC_CFGR1_EXTSEL_0        (0x1UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000040 */
794 #define ADC_CFGR1_EXTSEL_1        (0x2UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000080 */
795 #define ADC_CFGR1_EXTSEL_2        (0x4UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000100 */
796 
797 #define ADC_CFGR1_EXTEN_Pos       (10U)
798 #define ADC_CFGR1_EXTEN_Msk       (0x3UL << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000C00 */
799 #define ADC_CFGR1_EXTEN           ADC_CFGR1_EXTEN_Msk                          /*!< ADC group regular external trigger polarity */
800 #define ADC_CFGR1_EXTEN_0         (0x1UL << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000400 */
801 #define ADC_CFGR1_EXTEN_1         (0x2UL << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000800 */
802 
803 #define ADC_CFGR1_OVRMOD_Pos      (12U)
804 #define ADC_CFGR1_OVRMOD_Msk      (0x1UL << ADC_CFGR1_OVRMOD_Pos)               /*!< 0x00001000 */
805 #define ADC_CFGR1_OVRMOD          ADC_CFGR1_OVRMOD_Msk                         /*!< ADC group regular overrun configuration */
806 #define ADC_CFGR1_CONT_Pos        (13U)
807 #define ADC_CFGR1_CONT_Msk        (0x1UL << ADC_CFGR1_CONT_Pos)                 /*!< 0x00002000 */
808 #define ADC_CFGR1_CONT            ADC_CFGR1_CONT_Msk                           /*!< ADC group regular continuous conversion mode */
809 #define ADC_CFGR1_WAIT_Pos        (14U)
810 #define ADC_CFGR1_WAIT_Msk        (0x1UL << ADC_CFGR1_WAIT_Pos)                 /*!< 0x00004000 */
811 #define ADC_CFGR1_WAIT            ADC_CFGR1_WAIT_Msk                           /*!< ADC low power auto wait */
812 #define ADC_CFGR1_AUTOFF_Pos      (15U)
813 #define ADC_CFGR1_AUTOFF_Msk      (0x1UL << ADC_CFGR1_AUTOFF_Pos)               /*!< 0x00008000 */
814 #define ADC_CFGR1_AUTOFF          ADC_CFGR1_AUTOFF_Msk                         /*!< ADC low power auto power off */
815 #define ADC_CFGR1_DISCEN_Pos      (16U)
816 #define ADC_CFGR1_DISCEN_Msk      (0x1UL << ADC_CFGR1_DISCEN_Pos)               /*!< 0x00010000 */
817 #define ADC_CFGR1_DISCEN          ADC_CFGR1_DISCEN_Msk                         /*!< ADC group regular sequencer discontinuous mode */
818 
819 #define ADC_CFGR1_AWD1SGL_Pos     (22U)
820 #define ADC_CFGR1_AWD1SGL_Msk     (0x1UL << ADC_CFGR1_AWD1SGL_Pos)              /*!< 0x00400000 */
821 #define ADC_CFGR1_AWD1SGL         ADC_CFGR1_AWD1SGL_Msk                        /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
822 #define ADC_CFGR1_AWD1EN_Pos      (23U)
823 #define ADC_CFGR1_AWD1EN_Msk      (0x1UL << ADC_CFGR1_AWD1EN_Pos)               /*!< 0x00800000 */
824 #define ADC_CFGR1_AWD1EN          ADC_CFGR1_AWD1EN_Msk                         /*!< ADC analog watchdog 1 enable on scope ADC group regular */
825 
826 #define ADC_CFGR1_AWD1CH_Pos      (26U)
827 #define ADC_CFGR1_AWD1CH_Msk      (0x1FUL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x7C000000 */
828 #define ADC_CFGR1_AWD1CH          ADC_CFGR1_AWD1CH_Msk                         /*!< ADC analog watchdog 1 monitored channel selection */
829 #define ADC_CFGR1_AWD1CH_0        (0x01UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x04000000 */
830 #define ADC_CFGR1_AWD1CH_1        (0x02UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x08000000 */
831 #define ADC_CFGR1_AWD1CH_2        (0x04UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x10000000 */
832 #define ADC_CFGR1_AWD1CH_3        (0x08UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x20000000 */
833 #define ADC_CFGR1_AWD1CH_4        (0x10UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x40000000 */
834 
835 /* Legacy defines */
836 #define ADC_CFGR1_AUTDLY        (ADC_CFGR1_WAIT)
837 #define ADC_CFGR1_AWDSGL        (ADC_CFGR1_AWD1SGL)
838 #define ADC_CFGR1_AWDEN         (ADC_CFGR1_AWD1EN)
839 #define ADC_CFGR1_AWDCH         (ADC_CFGR1_AWD1CH)
840 #define ADC_CFGR1_AWDCH_0       (ADC_CFGR1_AWD1CH_0)
841 #define ADC_CFGR1_AWDCH_1       (ADC_CFGR1_AWD1CH_1)
842 #define ADC_CFGR1_AWDCH_2       (ADC_CFGR1_AWD1CH_2)
843 #define ADC_CFGR1_AWDCH_3       (ADC_CFGR1_AWD1CH_3)
844 #define ADC_CFGR1_AWDCH_4       (ADC_CFGR1_AWD1CH_4)
845 
846 /*******************  Bits definition for ADC_CFGR2 register  *****************/
847 #define ADC_CFGR2_CKMODE_Pos      (30U)
848 #define ADC_CFGR2_CKMODE_Msk      (0x3UL << ADC_CFGR2_CKMODE_Pos)               /*!< 0xC0000000 */
849 #define ADC_CFGR2_CKMODE          ADC_CFGR2_CKMODE_Msk                         /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
850 #define ADC_CFGR2_CKMODE_1        (0x2UL << ADC_CFGR2_CKMODE_Pos)               /*!< 0x80000000 */
851 #define ADC_CFGR2_CKMODE_0        (0x1UL << ADC_CFGR2_CKMODE_Pos)               /*!< 0x40000000 */
852 
853 /* Legacy defines */
854 #define  ADC_CFGR2_JITOFFDIV4   (ADC_CFGR2_CKMODE_1)   /*!< ADC clocked by PCLK div4 */
855 #define  ADC_CFGR2_JITOFFDIV2   (ADC_CFGR2_CKMODE_0)   /*!< ADC clocked by PCLK div2 */
856 
857 /******************  Bit definition for ADC_SMPR register  ********************/
858 #define ADC_SMPR_SMP_Pos          (0U)
859 #define ADC_SMPR_SMP_Msk          (0x7UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000007 */
860 #define ADC_SMPR_SMP              ADC_SMPR_SMP_Msk                             /*!< ADC group of channels sampling time 2 */
861 #define ADC_SMPR_SMP_0            (0x1UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000001 */
862 #define ADC_SMPR_SMP_1            (0x2UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000002 */
863 #define ADC_SMPR_SMP_2            (0x4UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000004 */
864 
865 /* Legacy defines */
866 #define  ADC_SMPR1_SMPR         (ADC_SMPR_SMP)         /*!< SMP[2:0] bits (Sampling time selection) */
867 #define  ADC_SMPR1_SMPR_0       (ADC_SMPR_SMP_0)       /*!< bit 0 */
868 #define  ADC_SMPR1_SMPR_1       (ADC_SMPR_SMP_1)       /*!< bit 1 */
869 #define  ADC_SMPR1_SMPR_2       (ADC_SMPR_SMP_2)       /*!< bit 2 */
870 
871 /*******************  Bit definition for ADC_TR register  ********************/
872 #define ADC_TR1_LT1_Pos           (0U)
873 #define ADC_TR1_LT1_Msk           (0xFFFUL << ADC_TR1_LT1_Pos)                  /*!< 0x00000FFF */
874 #define ADC_TR1_LT1               ADC_TR1_LT1_Msk                              /*!< ADC analog watchdog 1 threshold low */
875 #define ADC_TR1_LT1_0             (0x001UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000001 */
876 #define ADC_TR1_LT1_1             (0x002UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000002 */
877 #define ADC_TR1_LT1_2             (0x004UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000004 */
878 #define ADC_TR1_LT1_3             (0x008UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000008 */
879 #define ADC_TR1_LT1_4             (0x010UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000010 */
880 #define ADC_TR1_LT1_5             (0x020UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000020 */
881 #define ADC_TR1_LT1_6             (0x040UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000040 */
882 #define ADC_TR1_LT1_7             (0x080UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000080 */
883 #define ADC_TR1_LT1_8             (0x100UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000100 */
884 #define ADC_TR1_LT1_9             (0x200UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000200 */
885 #define ADC_TR1_LT1_10            (0x400UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000400 */
886 #define ADC_TR1_LT1_11            (0x800UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000800 */
887 
888 #define ADC_TR1_HT1_Pos           (16U)
889 #define ADC_TR1_HT1_Msk           (0xFFFUL << ADC_TR1_HT1_Pos)                  /*!< 0x0FFF0000 */
890 #define ADC_TR1_HT1               ADC_TR1_HT1_Msk                              /*!< ADC Analog watchdog 1 threshold high */
891 #define ADC_TR1_HT1_0             (0x001UL << ADC_TR1_HT1_Pos)                  /*!< 0x00010000 */
892 #define ADC_TR1_HT1_1             (0x002UL << ADC_TR1_HT1_Pos)                  /*!< 0x00020000 */
893 #define ADC_TR1_HT1_2             (0x004UL << ADC_TR1_HT1_Pos)                  /*!< 0x00040000 */
894 #define ADC_TR1_HT1_3             (0x008UL << ADC_TR1_HT1_Pos)                  /*!< 0x00080000 */
895 #define ADC_TR1_HT1_4             (0x010UL << ADC_TR1_HT1_Pos)                  /*!< 0x00100000 */
896 #define ADC_TR1_HT1_5             (0x020UL << ADC_TR1_HT1_Pos)                  /*!< 0x00200000 */
897 #define ADC_TR1_HT1_6             (0x040UL << ADC_TR1_HT1_Pos)                  /*!< 0x00400000 */
898 #define ADC_TR1_HT1_7             (0x080UL << ADC_TR1_HT1_Pos)                  /*!< 0x00800000 */
899 #define ADC_TR1_HT1_8             (0x100UL << ADC_TR1_HT1_Pos)                  /*!< 0x01000000 */
900 #define ADC_TR1_HT1_9             (0x200UL << ADC_TR1_HT1_Pos)                  /*!< 0x02000000 */
901 #define ADC_TR1_HT1_10            (0x400UL << ADC_TR1_HT1_Pos)                  /*!< 0x04000000 */
902 #define ADC_TR1_HT1_11            (0x800UL << ADC_TR1_HT1_Pos)                  /*!< 0x08000000 */
903 
904 /* Legacy defines */
905 #define  ADC_TR_HT              (ADC_TR1_HT1)
906 #define  ADC_TR_LT              (ADC_TR1_LT1)
907 #define  ADC_HTR_HT             (ADC_TR1_HT1)
908 #define  ADC_LTR_LT             (ADC_TR1_LT1)
909 
910 /******************  Bit definition for ADC_CHSELR register  ******************/
911 #define ADC_CHSELR_CHSEL_Pos      (0U)
912 #define ADC_CHSELR_CHSEL_Msk      (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)           /*!< 0x0007FFFF */
913 #define ADC_CHSELR_CHSEL          ADC_CHSELR_CHSEL_Msk                         /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
914 #define ADC_CHSELR_CHSEL18_Pos    (18U)
915 #define ADC_CHSELR_CHSEL18_Msk    (0x1UL << ADC_CHSELR_CHSEL18_Pos)             /*!< 0x00040000 */
916 #define ADC_CHSELR_CHSEL18        ADC_CHSELR_CHSEL18_Msk                       /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
917 #define ADC_CHSELR_CHSEL17_Pos    (17U)
918 #define ADC_CHSELR_CHSEL17_Msk    (0x1UL << ADC_CHSELR_CHSEL17_Pos)             /*!< 0x00020000 */
919 #define ADC_CHSELR_CHSEL17        ADC_CHSELR_CHSEL17_Msk                       /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
920 #define ADC_CHSELR_CHSEL16_Pos    (16U)
921 #define ADC_CHSELR_CHSEL16_Msk    (0x1UL << ADC_CHSELR_CHSEL16_Pos)             /*!< 0x00010000 */
922 #define ADC_CHSELR_CHSEL16        ADC_CHSELR_CHSEL16_Msk                       /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
923 #define ADC_CHSELR_CHSEL15_Pos    (15U)
924 #define ADC_CHSELR_CHSEL15_Msk    (0x1UL << ADC_CHSELR_CHSEL15_Pos)             /*!< 0x00008000 */
925 #define ADC_CHSELR_CHSEL15        ADC_CHSELR_CHSEL15_Msk                       /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
926 #define ADC_CHSELR_CHSEL14_Pos    (14U)
927 #define ADC_CHSELR_CHSEL14_Msk    (0x1UL << ADC_CHSELR_CHSEL14_Pos)             /*!< 0x00004000 */
928 #define ADC_CHSELR_CHSEL14        ADC_CHSELR_CHSEL14_Msk                       /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
929 #define ADC_CHSELR_CHSEL13_Pos    (13U)
930 #define ADC_CHSELR_CHSEL13_Msk    (0x1UL << ADC_CHSELR_CHSEL13_Pos)             /*!< 0x00002000 */
931 #define ADC_CHSELR_CHSEL13        ADC_CHSELR_CHSEL13_Msk                       /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
932 #define ADC_CHSELR_CHSEL12_Pos    (12U)
933 #define ADC_CHSELR_CHSEL12_Msk    (0x1UL << ADC_CHSELR_CHSEL12_Pos)             /*!< 0x00001000 */
934 #define ADC_CHSELR_CHSEL12        ADC_CHSELR_CHSEL12_Msk                       /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
935 #define ADC_CHSELR_CHSEL11_Pos    (11U)
936 #define ADC_CHSELR_CHSEL11_Msk    (0x1UL << ADC_CHSELR_CHSEL11_Pos)             /*!< 0x00000800 */
937 #define ADC_CHSELR_CHSEL11        ADC_CHSELR_CHSEL11_Msk                       /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
938 #define ADC_CHSELR_CHSEL10_Pos    (10U)
939 #define ADC_CHSELR_CHSEL10_Msk    (0x1UL << ADC_CHSELR_CHSEL10_Pos)             /*!< 0x00000400 */
940 #define ADC_CHSELR_CHSEL10        ADC_CHSELR_CHSEL10_Msk                       /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
941 #define ADC_CHSELR_CHSEL9_Pos     (9U)
942 #define ADC_CHSELR_CHSEL9_Msk     (0x1UL << ADC_CHSELR_CHSEL9_Pos)              /*!< 0x00000200 */
943 #define ADC_CHSELR_CHSEL9         ADC_CHSELR_CHSEL9_Msk                        /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
944 #define ADC_CHSELR_CHSEL8_Pos     (8U)
945 #define ADC_CHSELR_CHSEL8_Msk     (0x1UL << ADC_CHSELR_CHSEL8_Pos)              /*!< 0x00000100 */
946 #define ADC_CHSELR_CHSEL8         ADC_CHSELR_CHSEL8_Msk                        /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
947 #define ADC_CHSELR_CHSEL7_Pos     (7U)
948 #define ADC_CHSELR_CHSEL7_Msk     (0x1UL << ADC_CHSELR_CHSEL7_Pos)              /*!< 0x00000080 */
949 #define ADC_CHSELR_CHSEL7         ADC_CHSELR_CHSEL7_Msk                        /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
950 #define ADC_CHSELR_CHSEL6_Pos     (6U)
951 #define ADC_CHSELR_CHSEL6_Msk     (0x1UL << ADC_CHSELR_CHSEL6_Pos)              /*!< 0x00000040 */
952 #define ADC_CHSELR_CHSEL6         ADC_CHSELR_CHSEL6_Msk                        /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
953 #define ADC_CHSELR_CHSEL5_Pos     (5U)
954 #define ADC_CHSELR_CHSEL5_Msk     (0x1UL << ADC_CHSELR_CHSEL5_Pos)              /*!< 0x00000020 */
955 #define ADC_CHSELR_CHSEL5         ADC_CHSELR_CHSEL5_Msk                        /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
956 #define ADC_CHSELR_CHSEL4_Pos     (4U)
957 #define ADC_CHSELR_CHSEL4_Msk     (0x1UL << ADC_CHSELR_CHSEL4_Pos)              /*!< 0x00000010 */
958 #define ADC_CHSELR_CHSEL4         ADC_CHSELR_CHSEL4_Msk                        /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
959 #define ADC_CHSELR_CHSEL3_Pos     (3U)
960 #define ADC_CHSELR_CHSEL3_Msk     (0x1UL << ADC_CHSELR_CHSEL3_Pos)              /*!< 0x00000008 */
961 #define ADC_CHSELR_CHSEL3         ADC_CHSELR_CHSEL3_Msk                        /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
962 #define ADC_CHSELR_CHSEL2_Pos     (2U)
963 #define ADC_CHSELR_CHSEL2_Msk     (0x1UL << ADC_CHSELR_CHSEL2_Pos)              /*!< 0x00000004 */
964 #define ADC_CHSELR_CHSEL2         ADC_CHSELR_CHSEL2_Msk                        /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
965 #define ADC_CHSELR_CHSEL1_Pos     (1U)
966 #define ADC_CHSELR_CHSEL1_Msk     (0x1UL << ADC_CHSELR_CHSEL1_Pos)              /*!< 0x00000002 */
967 #define ADC_CHSELR_CHSEL1         ADC_CHSELR_CHSEL1_Msk                        /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
968 #define ADC_CHSELR_CHSEL0_Pos     (0U)
969 #define ADC_CHSELR_CHSEL0_Msk     (0x1UL << ADC_CHSELR_CHSEL0_Pos)              /*!< 0x00000001 */
970 #define ADC_CHSELR_CHSEL0         ADC_CHSELR_CHSEL0_Msk                        /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
971 
972 /********************  Bit definition for ADC_DR register  ********************/
973 #define ADC_DR_DATA_Pos           (0U)
974 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
975 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!< ADC group regular conversion data */
976 #define ADC_DR_DATA_0             (0x0001UL << ADC_DR_DATA_Pos)                 /*!< 0x00000001 */
977 #define ADC_DR_DATA_1             (0x0002UL << ADC_DR_DATA_Pos)                 /*!< 0x00000002 */
978 #define ADC_DR_DATA_2             (0x0004UL << ADC_DR_DATA_Pos)                 /*!< 0x00000004 */
979 #define ADC_DR_DATA_3             (0x0008UL << ADC_DR_DATA_Pos)                 /*!< 0x00000008 */
980 #define ADC_DR_DATA_4             (0x0010UL << ADC_DR_DATA_Pos)                 /*!< 0x00000010 */
981 #define ADC_DR_DATA_5             (0x0020UL << ADC_DR_DATA_Pos)                 /*!< 0x00000020 */
982 #define ADC_DR_DATA_6             (0x0040UL << ADC_DR_DATA_Pos)                 /*!< 0x00000040 */
983 #define ADC_DR_DATA_7             (0x0080UL << ADC_DR_DATA_Pos)                 /*!< 0x00000080 */
984 #define ADC_DR_DATA_8             (0x0100UL << ADC_DR_DATA_Pos)                 /*!< 0x00000100 */
985 #define ADC_DR_DATA_9             (0x0200UL << ADC_DR_DATA_Pos)                 /*!< 0x00000200 */
986 #define ADC_DR_DATA_10            (0x0400UL << ADC_DR_DATA_Pos)                 /*!< 0x00000400 */
987 #define ADC_DR_DATA_11            (0x0800UL << ADC_DR_DATA_Pos)                 /*!< 0x00000800 */
988 #define ADC_DR_DATA_12            (0x1000UL << ADC_DR_DATA_Pos)                 /*!< 0x00001000 */
989 #define ADC_DR_DATA_13            (0x2000UL << ADC_DR_DATA_Pos)                 /*!< 0x00002000 */
990 #define ADC_DR_DATA_14            (0x4000UL << ADC_DR_DATA_Pos)                 /*!< 0x00004000 */
991 #define ADC_DR_DATA_15            (0x8000UL << ADC_DR_DATA_Pos)                 /*!< 0x00008000 */
992 
993 /*************************  ADC Common registers  *****************************/
994 /*******************  Bit definition for ADC_CCR register  ********************/
995 #define ADC_CCR_VREFEN_Pos        (22U)
996 #define ADC_CCR_VREFEN_Msk        (0x1UL << ADC_CCR_VREFEN_Pos)                 /*!< 0x00400000 */
997 #define ADC_CCR_VREFEN            ADC_CCR_VREFEN_Msk                           /*!< ADC internal path to VrefInt enable */
998 #define ADC_CCR_TSEN_Pos          (23U)
999 #define ADC_CCR_TSEN_Msk          (0x1UL << ADC_CCR_TSEN_Pos)                   /*!< 0x00800000 */
1000 #define ADC_CCR_TSEN              ADC_CCR_TSEN_Msk                             /*!< ADC internal path to temperature sensor enable */
1001 
1002 #define ADC_CCR_VBATEN_Pos        (24U)
1003 #define ADC_CCR_VBATEN_Msk        (0x1UL << ADC_CCR_VBATEN_Pos)                 /*!< 0x01000000 */
1004 #define ADC_CCR_VBATEN            ADC_CCR_VBATEN_Msk                           /*!< ADC internal path to battery voltage enable */
1005 
1006 /******************************************************************************/
1007 /*                                                                            */
1008 /*                                 HDMI-CEC (CEC)                             */
1009 /*                                                                            */
1010 /******************************************************************************/
1011 
1012 /*******************  Bit definition for CEC_CR register  *********************/
1013 #define CEC_CR_CECEN_Pos         (0U)
1014 #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
1015 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                         */
1016 #define CEC_CR_TXSOM_Pos         (1U)
1017 #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
1018 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message            */
1019 #define CEC_CR_TXEOM_Pos         (2U)
1020 #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
1021 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message              */
1022 
1023 /*******************  Bit definition for CEC_CFGR register  *******************/
1024 #define CEC_CFGR_SFT_Pos         (0U)
1025 #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
1026 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time               */
1027 #define CEC_CFGR_RXTOL_Pos       (3U)
1028 #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
1029 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                      */
1030 #define CEC_CFGR_BRESTP_Pos      (4U)
1031 #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
1032 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                        */
1033 #define CEC_CFGR_BREGEN_Pos      (5U)
1034 #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
1035 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation    */
1036 #define CEC_CFGR_LBPEGEN_Pos     (6U)
1037 #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
1038 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error gener.   */
1039 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
1040 #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
1041 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No Error generation  */
1042 #define CEC_CFGR_SFTOPT_Pos      (8U)
1043 #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
1044 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional      */
1045 #define CEC_CFGR_OAR_Pos         (16U)
1046 #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
1047 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                    */
1048 #define CEC_CFGR_LSTN_Pos        (31U)
1049 #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
1050 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                    */
1051 
1052 /*******************  Bit definition for CEC_TXDR register  *******************/
1053 #define CEC_TXDR_TXD_Pos         (0U)
1054 #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
1055 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                        */
1056 
1057 /*******************  Bit definition for CEC_RXDR register  *******************/
1058 #define CEC_RXDR_RXD_Pos         (0U)
1059 #define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                   /*!< 0x000000FF */
1060 #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                        */
1061 /* Legacy aliases */
1062 #define CEC_TXDR_RXD_Pos         CEC_RXDR_RXD_Pos
1063 #define CEC_TXDR_RXD_Msk         CEC_RXDR_RXD_Msk
1064 #define CEC_TXDR_RXD             CEC_RXDR_RXD
1065 /*******************  Bit definition for CEC_ISR register  ********************/
1066 #define CEC_ISR_RXBR_Pos         (0U)
1067 #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
1068 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                   */
1069 #define CEC_ISR_RXEND_Pos        (1U)
1070 #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
1071 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                   */
1072 #define CEC_ISR_RXOVR_Pos        (2U)
1073 #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
1074 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                         */
1075 #define CEC_ISR_BRE_Pos          (3U)
1076 #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
1077 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                */
1078 #define CEC_ISR_SBPE_Pos         (4U)
1079 #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
1080 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error          */
1081 #define CEC_ISR_LBPE_Pos         (5U)
1082 #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
1083 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error           */
1084 #define CEC_ISR_RXACKE_Pos       (6U)
1085 #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
1086 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge             */
1087 #define CEC_ISR_ARBLST_Pos       (7U)
1088 #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
1089 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                   */
1090 #define CEC_ISR_TXBR_Pos         (8U)
1091 #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
1092 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                    */
1093 #define CEC_ISR_TXEND_Pos        (9U)
1094 #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
1095 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                */
1096 #define CEC_ISR_TXUDR_Pos        (10U)
1097 #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
1098 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                 */
1099 #define CEC_ISR_TXERR_Pos        (11U)
1100 #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
1101 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                           */
1102 #define CEC_ISR_TXACKE_Pos       (12U)
1103 #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
1104 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge             */
1105 
1106 /*******************  Bit definition for CEC_IER register  ********************/
1107 #define CEC_IER_RXBRIE_Pos       (0U)
1108 #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
1109 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable         */
1110 #define CEC_IER_RXENDIE_Pos      (1U)
1111 #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
1112 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable         */
1113 #define CEC_IER_RXOVRIE_Pos      (2U)
1114 #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
1115 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable               */
1116 #define CEC_IER_BREIE_Pos        (3U)
1117 #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
1118 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable      */
1119 #define CEC_IER_SBPEIE_Pos       (4U)
1120 #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
1121 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable*/
1122 #define CEC_IER_LBPEIE_Pos       (5U)
1123 #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
1124 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable */
1125 #define CEC_IER_RXACKEIE_Pos     (6U)
1126 #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
1127 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable   */
1128 #define CEC_IER_ARBLSTIE_Pos     (7U)
1129 #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
1130 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable         */
1131 #define CEC_IER_TXBRIE_Pos       (8U)
1132 #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
1133 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable         */
1134 #define CEC_IER_TXENDIE_Pos      (9U)
1135 #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
1136 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable      */
1137 #define CEC_IER_TXUDRIE_Pos      (10U)
1138 #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
1139 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable       */
1140 #define CEC_IER_TXERRIE_Pos      (11U)
1141 #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
1142 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                 */
1143 #define CEC_IER_TXACKEIE_Pos     (12U)
1144 #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
1145 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable   */
1146 
1147 /******************************************************************************/
1148 /*                                                                            */
1149 /*                      Analog Comparators (COMP)                             */
1150 /*                                                                            */
1151 /******************************************************************************/
1152 /***********************  Bit definition for COMP_CSR register  ***************/
1153 /* COMP1 bits definition */
1154 #define COMP_CSR_COMP1EN_Pos          (0U)
1155 #define COMP_CSR_COMP1EN_Msk          (0x1UL << COMP_CSR_COMP1EN_Pos)           /*!< 0x00000001 */
1156 #define COMP_CSR_COMP1EN              COMP_CSR_COMP1EN_Msk                     /*!< COMP1 enable */
1157 #define COMP_CSR_COMP1SW1_Pos         (1U)
1158 #define COMP_CSR_COMP1SW1_Msk         (0x1UL << COMP_CSR_COMP1SW1_Pos)          /*!< 0x00000002 */
1159 #define COMP_CSR_COMP1SW1             COMP_CSR_COMP1SW1_Msk                    /*!< COMP1 SW1 switch control */
1160 #define COMP_CSR_COMP1MODE_Pos        (2U)
1161 #define COMP_CSR_COMP1MODE_Msk        (0x3UL << COMP_CSR_COMP1MODE_Pos)         /*!< 0x0000000C */
1162 #define COMP_CSR_COMP1MODE            COMP_CSR_COMP1MODE_Msk                   /*!< COMP1 power mode */
1163 #define COMP_CSR_COMP1MODE_0          (0x1UL << COMP_CSR_COMP1MODE_Pos)         /*!< 0x00000004 */
1164 #define COMP_CSR_COMP1MODE_1          (0x2UL << COMP_CSR_COMP1MODE_Pos)         /*!< 0x00000008 */
1165 #define COMP_CSR_COMP1INSEL_Pos       (4U)
1166 #define COMP_CSR_COMP1INSEL_Msk       (0x7UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000070 */
1167 #define COMP_CSR_COMP1INSEL           COMP_CSR_COMP1INSEL_Msk                  /*!< COMP1 inverting input select */
1168 #define COMP_CSR_COMP1INSEL_0         (0x1UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000010 */
1169 #define COMP_CSR_COMP1INSEL_1         (0x2UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000020 */
1170 #define COMP_CSR_COMP1INSEL_2         (0x4UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000040 */
1171 #define COMP_CSR_COMP1OUTSEL_Pos      (8U)
1172 #define COMP_CSR_COMP1OUTSEL_Msk      (0x7UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000700 */
1173 #define COMP_CSR_COMP1OUTSEL          COMP_CSR_COMP1OUTSEL_Msk                 /*!< COMP1 output select */
1174 #define COMP_CSR_COMP1OUTSEL_0        (0x1UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000100 */
1175 #define COMP_CSR_COMP1OUTSEL_1        (0x2UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000200 */
1176 #define COMP_CSR_COMP1OUTSEL_2        (0x4UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000400 */
1177 #define COMP_CSR_COMP1POL_Pos         (11U)
1178 #define COMP_CSR_COMP1POL_Msk         (0x1UL << COMP_CSR_COMP1POL_Pos)          /*!< 0x00000800 */
1179 #define COMP_CSR_COMP1POL             COMP_CSR_COMP1POL_Msk                    /*!< COMP1 output polarity */
1180 #define COMP_CSR_COMP1HYST_Pos        (12U)
1181 #define COMP_CSR_COMP1HYST_Msk        (0x3UL << COMP_CSR_COMP1HYST_Pos)         /*!< 0x00003000 */
1182 #define COMP_CSR_COMP1HYST            COMP_CSR_COMP1HYST_Msk                   /*!< COMP1 hysteresis */
1183 #define COMP_CSR_COMP1HYST_0          (0x1UL << COMP_CSR_COMP1HYST_Pos)         /*!< 0x00001000 */
1184 #define COMP_CSR_COMP1HYST_1          (0x2UL << COMP_CSR_COMP1HYST_Pos)         /*!< 0x00002000 */
1185 #define COMP_CSR_COMP1OUT_Pos         (14U)
1186 #define COMP_CSR_COMP1OUT_Msk         (0x1UL << COMP_CSR_COMP1OUT_Pos)          /*!< 0x00004000 */
1187 #define COMP_CSR_COMP1OUT             COMP_CSR_COMP1OUT_Msk                    /*!< COMP1 output level */
1188 #define COMP_CSR_COMP1LOCK_Pos        (15U)
1189 #define COMP_CSR_COMP1LOCK_Msk        (0x1UL << COMP_CSR_COMP1LOCK_Pos)         /*!< 0x00008000 */
1190 #define COMP_CSR_COMP1LOCK            COMP_CSR_COMP1LOCK_Msk                   /*!< COMP1 lock */
1191 /* COMP2 bits definition */
1192 #define COMP_CSR_COMP2EN_Pos          (16U)
1193 #define COMP_CSR_COMP2EN_Msk          (0x1UL << COMP_CSR_COMP2EN_Pos)           /*!< 0x00010000 */
1194 #define COMP_CSR_COMP2EN              COMP_CSR_COMP2EN_Msk                     /*!< COMP2 enable */
1195 #define COMP_CSR_COMP2MODE_Pos        (18U)
1196 #define COMP_CSR_COMP2MODE_Msk        (0x3UL << COMP_CSR_COMP2MODE_Pos)         /*!< 0x000C0000 */
1197 #define COMP_CSR_COMP2MODE            COMP_CSR_COMP2MODE_Msk                   /*!< COMP2 power mode */
1198 #define COMP_CSR_COMP2MODE_0          (0x1UL << COMP_CSR_COMP2MODE_Pos)         /*!< 0x00040000 */
1199 #define COMP_CSR_COMP2MODE_1          (0x2UL << COMP_CSR_COMP2MODE_Pos)         /*!< 0x00080000 */
1200 #define COMP_CSR_COMP2INSEL_Pos       (20U)
1201 #define COMP_CSR_COMP2INSEL_Msk       (0x7UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00700000 */
1202 #define COMP_CSR_COMP2INSEL           COMP_CSR_COMP2INSEL_Msk                  /*!< COMP2 inverting input select */
1203 #define COMP_CSR_COMP2INSEL_0         (0x1UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00100000 */
1204 #define COMP_CSR_COMP2INSEL_1         (0x2UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00200000 */
1205 #define COMP_CSR_COMP2INSEL_2         (0x4UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00400000 */
1206 #define COMP_CSR_WNDWEN_Pos           (23U)
1207 #define COMP_CSR_WNDWEN_Msk           (0x1UL << COMP_CSR_WNDWEN_Pos)            /*!< 0x00800000 */
1208 #define COMP_CSR_WNDWEN               COMP_CSR_WNDWEN_Msk                      /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
1209 #define COMP_CSR_COMP2OUTSEL_Pos      (24U)
1210 #define COMP_CSR_COMP2OUTSEL_Msk      (0x7UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x07000000 */
1211 #define COMP_CSR_COMP2OUTSEL          COMP_CSR_COMP2OUTSEL_Msk                 /*!< COMP2 output select */
1212 #define COMP_CSR_COMP2OUTSEL_0        (0x1UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x01000000 */
1213 #define COMP_CSR_COMP2OUTSEL_1        (0x2UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x02000000 */
1214 #define COMP_CSR_COMP2OUTSEL_2        (0x4UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x04000000 */
1215 #define COMP_CSR_COMP2POL_Pos         (27U)
1216 #define COMP_CSR_COMP2POL_Msk         (0x1UL << COMP_CSR_COMP2POL_Pos)          /*!< 0x08000000 */
1217 #define COMP_CSR_COMP2POL             COMP_CSR_COMP2POL_Msk                    /*!< COMP2 output polarity */
1218 #define COMP_CSR_COMP2HYST_Pos        (28U)
1219 #define COMP_CSR_COMP2HYST_Msk        (0x3UL << COMP_CSR_COMP2HYST_Pos)         /*!< 0x30000000 */
1220 #define COMP_CSR_COMP2HYST            COMP_CSR_COMP2HYST_Msk                   /*!< COMP2 hysteresis */
1221 #define COMP_CSR_COMP2HYST_0          (0x1UL << COMP_CSR_COMP2HYST_Pos)         /*!< 0x10000000 */
1222 #define COMP_CSR_COMP2HYST_1          (0x2UL << COMP_CSR_COMP2HYST_Pos)         /*!< 0x20000000 */
1223 #define COMP_CSR_COMP2OUT_Pos         (30U)
1224 #define COMP_CSR_COMP2OUT_Msk         (0x1UL << COMP_CSR_COMP2OUT_Pos)          /*!< 0x40000000 */
1225 #define COMP_CSR_COMP2OUT             COMP_CSR_COMP2OUT_Msk                    /*!< COMP2 output level */
1226 #define COMP_CSR_COMP2LOCK_Pos        (31U)
1227 #define COMP_CSR_COMP2LOCK_Msk        (0x1UL << COMP_CSR_COMP2LOCK_Pos)         /*!< 0x80000000 */
1228 #define COMP_CSR_COMP2LOCK            COMP_CSR_COMP2LOCK_Msk                   /*!< COMP2 lock */
1229 /* COMPx bits definition */
1230 #define COMP_CSR_COMPxEN_Pos          (0U)
1231 #define COMP_CSR_COMPxEN_Msk          (0x1UL << COMP_CSR_COMPxEN_Pos)           /*!< 0x00000001 */
1232 #define COMP_CSR_COMPxEN              COMP_CSR_COMPxEN_Msk                     /*!< COMPx enable */
1233 #define COMP_CSR_COMPxMODE_Pos        (2U)
1234 #define COMP_CSR_COMPxMODE_Msk        (0x3UL << COMP_CSR_COMPxMODE_Pos)         /*!< 0x0000000C */
1235 #define COMP_CSR_COMPxMODE            COMP_CSR_COMPxMODE_Msk                   /*!< COMPx power mode */
1236 #define COMP_CSR_COMPxMODE_0          (0x1UL << COMP_CSR_COMPxMODE_Pos)         /*!< 0x00000004 */
1237 #define COMP_CSR_COMPxMODE_1          (0x2UL << COMP_CSR_COMPxMODE_Pos)         /*!< 0x00000008 */
1238 #define COMP_CSR_COMPxINSEL_Pos       (4U)
1239 #define COMP_CSR_COMPxINSEL_Msk       (0x7UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000070 */
1240 #define COMP_CSR_COMPxINSEL           COMP_CSR_COMPxINSEL_Msk                  /*!< COMPx inverting input select */
1241 #define COMP_CSR_COMPxINSEL_0         (0x1UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000010 */
1242 #define COMP_CSR_COMPxINSEL_1         (0x2UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000020 */
1243 #define COMP_CSR_COMPxINSEL_2         (0x4UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000040 */
1244 #define COMP_CSR_COMPxOUTSEL_Pos      (8U)
1245 #define COMP_CSR_COMPxOUTSEL_Msk      (0x7UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000700 */
1246 #define COMP_CSR_COMPxOUTSEL          COMP_CSR_COMPxOUTSEL_Msk                 /*!< COMPx output select */
1247 #define COMP_CSR_COMPxOUTSEL_0        (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000100 */
1248 #define COMP_CSR_COMPxOUTSEL_1        (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000200 */
1249 #define COMP_CSR_COMPxOUTSEL_2        (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000400 */
1250 #define COMP_CSR_COMPxPOL_Pos         (11U)
1251 #define COMP_CSR_COMPxPOL_Msk         (0x1UL << COMP_CSR_COMPxPOL_Pos)          /*!< 0x00000800 */
1252 #define COMP_CSR_COMPxPOL             COMP_CSR_COMPxPOL_Msk                    /*!< COMPx output polarity */
1253 #define COMP_CSR_COMPxHYST_Pos        (12U)
1254 #define COMP_CSR_COMPxHYST_Msk        (0x3UL << COMP_CSR_COMPxHYST_Pos)         /*!< 0x00003000 */
1255 #define COMP_CSR_COMPxHYST            COMP_CSR_COMPxHYST_Msk                   /*!< COMPx hysteresis */
1256 #define COMP_CSR_COMPxHYST_0          (0x1UL << COMP_CSR_COMPxHYST_Pos)         /*!< 0x00001000 */
1257 #define COMP_CSR_COMPxHYST_1          (0x2UL << COMP_CSR_COMPxHYST_Pos)         /*!< 0x00002000 */
1258 #define COMP_CSR_COMPxOUT_Pos         (14U)
1259 #define COMP_CSR_COMPxOUT_Msk         (0x1UL << COMP_CSR_COMPxOUT_Pos)          /*!< 0x00004000 */
1260 #define COMP_CSR_COMPxOUT             COMP_CSR_COMPxOUT_Msk                    /*!< COMPx output level */
1261 #define COMP_CSR_COMPxLOCK_Pos        (15U)
1262 #define COMP_CSR_COMPxLOCK_Msk        (0x1UL << COMP_CSR_COMPxLOCK_Pos)         /*!< 0x00008000 */
1263 #define COMP_CSR_COMPxLOCK            COMP_CSR_COMPxLOCK_Msk                   /*!< COMPx lock */
1264 
1265 /******************************************************************************/
1266 /*                                                                            */
1267 /*                       CRC calculation unit (CRC)                           */
1268 /*                                                                            */
1269 /******************************************************************************/
1270 
1271 /*
1272 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
1273 */
1274 
1275 /* Support of Programmable Polynomial size and value feature */
1276 #define CRC_PROG_POLYNOMIAL_SUPPORT
1277 
1278 /*******************  Bit definition for CRC_DR register  *********************/
1279 #define CRC_DR_DR_Pos            (0U)
1280 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
1281 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
1282 
1283 /*******************  Bit definition for CRC_IDR register  ********************/
1284 #define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
1285 
1286 /********************  Bit definition for CRC_CR register  ********************/
1287 #define CRC_CR_RESET_Pos         (0U)
1288 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
1289 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
1290 #define CRC_CR_POLYSIZE_Pos      (3U)
1291 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
1292 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
1293 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
1294 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
1295 #define CRC_CR_REV_IN_Pos        (5U)
1296 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
1297 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
1298 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
1299 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
1300 #define CRC_CR_REV_OUT_Pos       (7U)
1301 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
1302 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
1303 
1304 /*******************  Bit definition for CRC_INIT register  *******************/
1305 #define CRC_INIT_INIT_Pos        (0U)
1306 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
1307 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
1308 
1309 /*******************  Bit definition for CRC_POL register  ********************/
1310 #define CRC_POL_POL_Pos          (0U)
1311 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
1312 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial  */
1313 
1314 /******************************************************************************/
1315 /*                                                                            */
1316 /*                          CRS Clock Recovery System                         */
1317 /******************************************************************************/
1318 
1319 /*******************  Bit definition for CRS_CR register  *********************/
1320 #define CRS_CR_SYNCOKIE_Pos       (0U)
1321 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
1322 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
1323 #define CRS_CR_SYNCWARNIE_Pos     (1U)
1324 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
1325 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
1326 #define CRS_CR_ERRIE_Pos          (2U)
1327 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
1328 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
1329 #define CRS_CR_ESYNCIE_Pos        (3U)
1330 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
1331 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
1332 #define CRS_CR_CEN_Pos            (5U)
1333 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
1334 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
1335 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
1336 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
1337 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
1338 #define CRS_CR_SWSYNC_Pos         (7U)
1339 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
1340 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
1341 #define CRS_CR_TRIM_Pos           (8U)
1342 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
1343 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
1344 
1345 /*******************  Bit definition for CRS_CFGR register  *********************/
1346 #define CRS_CFGR_RELOAD_Pos       (0U)
1347 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
1348 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
1349 #define CRS_CFGR_FELIM_Pos        (16U)
1350 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
1351 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
1352 
1353 #define CRS_CFGR_SYNCDIV_Pos      (24U)
1354 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
1355 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
1356 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
1357 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
1358 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
1359 
1360 #define CRS_CFGR_SYNCSRC_Pos      (28U)
1361 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
1362 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
1363 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
1364 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
1365 
1366 #define CRS_CFGR_SYNCPOL_Pos      (31U)
1367 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
1368 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
1369 
1370 /*******************  Bit definition for CRS_ISR register  *********************/
1371 #define CRS_ISR_SYNCOKF_Pos       (0U)
1372 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
1373 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
1374 #define CRS_ISR_SYNCWARNF_Pos     (1U)
1375 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
1376 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
1377 #define CRS_ISR_ERRF_Pos          (2U)
1378 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
1379 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
1380 #define CRS_ISR_ESYNCF_Pos        (3U)
1381 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
1382 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
1383 #define CRS_ISR_SYNCERR_Pos       (8U)
1384 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
1385 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
1386 #define CRS_ISR_SYNCMISS_Pos      (9U)
1387 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
1388 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
1389 #define CRS_ISR_TRIMOVF_Pos       (10U)
1390 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
1391 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
1392 #define CRS_ISR_FEDIR_Pos         (15U)
1393 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
1394 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
1395 #define CRS_ISR_FECAP_Pos         (16U)
1396 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
1397 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
1398 
1399 /*******************  Bit definition for CRS_ICR register  *********************/
1400 #define CRS_ICR_SYNCOKC_Pos       (0U)
1401 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
1402 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
1403 #define CRS_ICR_SYNCWARNC_Pos     (1U)
1404 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
1405 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
1406 #define CRS_ICR_ERRC_Pos          (2U)
1407 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
1408 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag        */
1409 #define CRS_ICR_ESYNCC_Pos        (3U)
1410 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
1411 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
1412 
1413 /******************************************************************************/
1414 /*                                                                            */
1415 /*                 Digital to Analog Converter (DAC)                          */
1416 /*                                                                            */
1417 /******************************************************************************/
1418 
1419 /*
1420  * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
1421  */
1422 #define DAC_CHANNEL2_SUPPORT                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
1423 
1424 /********************  Bit definition for DAC_CR register  ********************/
1425 #define DAC_CR_EN1_Pos              (0U)
1426 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
1427 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
1428 #define DAC_CR_BOFF1_Pos            (1U)
1429 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
1430 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
1431 #define DAC_CR_TEN1_Pos             (2U)
1432 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
1433 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
1434 
1435 #define DAC_CR_TSEL1_Pos            (3U)
1436 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
1437 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1438 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
1439 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
1440 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
1441 
1442 #define DAC_CR_WAVE1_Pos            (6U)
1443 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
1444 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1445 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
1446 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
1447 
1448 #define DAC_CR_MAMP1_Pos            (8U)
1449 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
1450 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)  */
1451 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
1452 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
1453 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
1454 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
1455 
1456 #define DAC_CR_DMAEN1_Pos           (12U)
1457 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
1458 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
1459 #define DAC_CR_DMAUDRIE1_Pos        (13U)
1460 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
1461 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun Interrupt enable */
1462 
1463 #define DAC_CR_EN2_Pos              (16U)
1464 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
1465 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
1466 #define DAC_CR_BOFF2_Pos            (17U)
1467 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
1468 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
1469 #define DAC_CR_TEN2_Pos             (18U)
1470 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
1471 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
1472 
1473 #define DAC_CR_TSEL2_Pos            (19U)
1474 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
1475 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
1476 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
1477 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
1478 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
1479 
1480 #define DAC_CR_WAVE2_Pos            (22U)
1481 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
1482 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1483 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
1484 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
1485 
1486 #define DAC_CR_MAMP2_Pos            (24U)
1487 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
1488 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1489 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
1490 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
1491 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
1492 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
1493 
1494 #define DAC_CR_DMAEN2_Pos           (28U)
1495 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
1496 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
1497 #define DAC_CR_DMAUDRIE2_Pos        (29U)
1498 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
1499 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel2 DMA Underrun Interrupt enable */
1500 
1501 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
1502 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
1503 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
1504 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
1505 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
1506 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
1507 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
1508 
1509 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
1510 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
1511 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
1512 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
1513 
1514 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
1515 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
1516 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
1517 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
1518 
1519 /******************  Bit definition for DAC_DHR8R1 register  ******************/
1520 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
1521 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
1522 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
1523 
1524 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
1525 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
1526 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
1527 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
1528 
1529 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
1530 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
1531 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
1532 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
1533 
1534 /******************  Bit definition for DAC_DHR8R2 register  ******************/
1535 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
1536 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
1537 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
1538 
1539 /*****************  Bit definition for DAC_DHR12RD register  ******************/
1540 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
1541 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
1542 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
1543 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
1544 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
1545 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data  */
1546 
1547 /*****************  Bit definition for DAC_DHR12LD register  ******************/
1548 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
1549 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
1550 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
1551 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
1552 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
1553 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data  */
1554 
1555 /******************  Bit definition for DAC_DHR8RD register  ******************/
1556 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
1557 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
1558 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
1559 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
1560 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
1561 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
1562 
1563 /*******************  Bit definition for DAC_DOR1 register  *******************/
1564 #define DAC_DOR1_DACC1DOR_Pos       (0U)
1565 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
1566 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
1567 
1568 /*******************  Bit definition for DAC_DOR2 register  *******************/
1569 #define DAC_DOR2_DACC2DOR_Pos       (0U)
1570 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
1571 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
1572 
1573 /********************  Bit definition for DAC_SR register  ********************/
1574 #define DAC_SR_DMAUDR1_Pos          (13U)
1575 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
1576 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
1577 #define DAC_SR_DMAUDR2_Pos          (29U)
1578 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
1579 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag  */
1580 
1581 /******************************************************************************/
1582 /*                                                                            */
1583 /*                           Debug MCU (DBGMCU)                               */
1584 /*                                                                            */
1585 /******************************************************************************/
1586 
1587 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
1588 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
1589 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1590 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  /*!< Device Identifier */
1591 
1592 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
1593 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1594 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  /*!< REV_ID[15:0] bits (Revision Identifier) */
1595 #define DBGMCU_IDCODE_REV_ID_0                       (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1596 #define DBGMCU_IDCODE_REV_ID_1                       (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1597 #define DBGMCU_IDCODE_REV_ID_2                       (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1598 #define DBGMCU_IDCODE_REV_ID_3                       (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1599 #define DBGMCU_IDCODE_REV_ID_4                       (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1600 #define DBGMCU_IDCODE_REV_ID_5                       (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1601 #define DBGMCU_IDCODE_REV_ID_6                       (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1602 #define DBGMCU_IDCODE_REV_ID_7                       (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1603 #define DBGMCU_IDCODE_REV_ID_8                       (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1604 #define DBGMCU_IDCODE_REV_ID_9                       (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1605 #define DBGMCU_IDCODE_REV_ID_10                      (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1606 #define DBGMCU_IDCODE_REV_ID_11                      (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1607 #define DBGMCU_IDCODE_REV_ID_12                      (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1608 #define DBGMCU_IDCODE_REV_ID_13                      (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1609 #define DBGMCU_IDCODE_REV_ID_14                      (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1610 #define DBGMCU_IDCODE_REV_ID_15                      (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1611 
1612 /******************  Bit definition for DBGMCU_CR register  *******************/
1613 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
1614 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1615 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    /*!< Debug Stop Mode */
1616 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
1617 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1618 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
1619 
1620 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
1621 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
1622 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1623 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1624 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
1625 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
1626 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
1627 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
1628 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
1629 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
1630 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
1631 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
1632 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted  */
1633 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
1634 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
1635 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
1636 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
1637 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1638 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1639 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
1640 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1641 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1642 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
1643 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1644 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1645 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
1646 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
1647 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1648 
1649 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
1650 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (11U)
1651 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
1652 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
1653 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos            (16U)
1654 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
1655 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP                DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted  */
1656 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos            (17U)
1657 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
1658 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP                DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
1659 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos            (18U)
1660 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
1661 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP                DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
1662 
1663 /******************************************************************************/
1664 /*                                                                            */
1665 /*                           DMA Controller (DMA)                             */
1666 /*                                                                            */
1667 /******************************************************************************/
1668 /*******************  Bit definition for DMA_ISR register  ********************/
1669 #define DMA_ISR_GIF1_Pos       (0U)
1670 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
1671 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
1672 #define DMA_ISR_TCIF1_Pos      (1U)
1673 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
1674 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
1675 #define DMA_ISR_HTIF1_Pos      (2U)
1676 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
1677 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
1678 #define DMA_ISR_TEIF1_Pos      (3U)
1679 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
1680 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
1681 #define DMA_ISR_GIF2_Pos       (4U)
1682 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
1683 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
1684 #define DMA_ISR_TCIF2_Pos      (5U)
1685 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
1686 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
1687 #define DMA_ISR_HTIF2_Pos      (6U)
1688 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
1689 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
1690 #define DMA_ISR_TEIF2_Pos      (7U)
1691 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
1692 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
1693 #define DMA_ISR_GIF3_Pos       (8U)
1694 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
1695 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
1696 #define DMA_ISR_TCIF3_Pos      (9U)
1697 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
1698 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
1699 #define DMA_ISR_HTIF3_Pos      (10U)
1700 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
1701 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
1702 #define DMA_ISR_TEIF3_Pos      (11U)
1703 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
1704 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
1705 #define DMA_ISR_GIF4_Pos       (12U)
1706 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
1707 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
1708 #define DMA_ISR_TCIF4_Pos      (13U)
1709 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
1710 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
1711 #define DMA_ISR_HTIF4_Pos      (14U)
1712 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
1713 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
1714 #define DMA_ISR_TEIF4_Pos      (15U)
1715 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
1716 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
1717 #define DMA_ISR_GIF5_Pos       (16U)
1718 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
1719 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
1720 #define DMA_ISR_TCIF5_Pos      (17U)
1721 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
1722 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
1723 #define DMA_ISR_HTIF5_Pos      (18U)
1724 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
1725 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
1726 #define DMA_ISR_TEIF5_Pos      (19U)
1727 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
1728 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
1729 #define DMA_ISR_GIF6_Pos       (20U)
1730 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
1731 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag    */
1732 #define DMA_ISR_TCIF6_Pos      (21U)
1733 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
1734 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag   */
1735 #define DMA_ISR_HTIF6_Pos      (22U)
1736 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
1737 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag       */
1738 #define DMA_ISR_TEIF6_Pos      (23U)
1739 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
1740 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag      */
1741 #define DMA_ISR_GIF7_Pos       (24U)
1742 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
1743 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag    */
1744 #define DMA_ISR_TCIF7_Pos      (25U)
1745 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
1746 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag   */
1747 #define DMA_ISR_HTIF7_Pos      (26U)
1748 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
1749 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag       */
1750 #define DMA_ISR_TEIF7_Pos      (27U)
1751 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
1752 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag      */
1753 
1754 /*******************  Bit definition for DMA_IFCR register  *******************/
1755 #define DMA_IFCR_CGIF1_Pos     (0U)
1756 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
1757 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
1758 #define DMA_IFCR_CTCIF1_Pos    (1U)
1759 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
1760 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
1761 #define DMA_IFCR_CHTIF1_Pos    (2U)
1762 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
1763 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
1764 #define DMA_IFCR_CTEIF1_Pos    (3U)
1765 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
1766 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
1767 #define DMA_IFCR_CGIF2_Pos     (4U)
1768 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
1769 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
1770 #define DMA_IFCR_CTCIF2_Pos    (5U)
1771 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
1772 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
1773 #define DMA_IFCR_CHTIF2_Pos    (6U)
1774 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
1775 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
1776 #define DMA_IFCR_CTEIF2_Pos    (7U)
1777 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
1778 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
1779 #define DMA_IFCR_CGIF3_Pos     (8U)
1780 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
1781 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
1782 #define DMA_IFCR_CTCIF3_Pos    (9U)
1783 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
1784 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
1785 #define DMA_IFCR_CHTIF3_Pos    (10U)
1786 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
1787 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
1788 #define DMA_IFCR_CTEIF3_Pos    (11U)
1789 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
1790 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
1791 #define DMA_IFCR_CGIF4_Pos     (12U)
1792 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
1793 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
1794 #define DMA_IFCR_CTCIF4_Pos    (13U)
1795 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
1796 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
1797 #define DMA_IFCR_CHTIF4_Pos    (14U)
1798 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
1799 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
1800 #define DMA_IFCR_CTEIF4_Pos    (15U)
1801 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
1802 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
1803 #define DMA_IFCR_CGIF5_Pos     (16U)
1804 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
1805 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
1806 #define DMA_IFCR_CTCIF5_Pos    (17U)
1807 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
1808 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
1809 #define DMA_IFCR_CHTIF5_Pos    (18U)
1810 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
1811 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
1812 #define DMA_IFCR_CTEIF5_Pos    (19U)
1813 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
1814 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
1815 #define DMA_IFCR_CGIF6_Pos     (20U)
1816 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
1817 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear    */
1818 #define DMA_IFCR_CTCIF6_Pos    (21U)
1819 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
1820 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear   */
1821 #define DMA_IFCR_CHTIF6_Pos    (22U)
1822 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
1823 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear       */
1824 #define DMA_IFCR_CTEIF6_Pos    (23U)
1825 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
1826 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear      */
1827 #define DMA_IFCR_CGIF7_Pos     (24U)
1828 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
1829 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear    */
1830 #define DMA_IFCR_CTCIF7_Pos    (25U)
1831 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
1832 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear   */
1833 #define DMA_IFCR_CHTIF7_Pos    (26U)
1834 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
1835 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear       */
1836 #define DMA_IFCR_CTEIF7_Pos    (27U)
1837 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
1838 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear      */
1839 
1840 /*******************  Bit definition for DMA_CCR register  ********************/
1841 #define DMA_CCR_EN_Pos         (0U)
1842 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
1843 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
1844 #define DMA_CCR_TCIE_Pos       (1U)
1845 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
1846 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
1847 #define DMA_CCR_HTIE_Pos       (2U)
1848 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
1849 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
1850 #define DMA_CCR_TEIE_Pos       (3U)
1851 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
1852 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
1853 #define DMA_CCR_DIR_Pos        (4U)
1854 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
1855 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
1856 #define DMA_CCR_CIRC_Pos       (5U)
1857 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
1858 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
1859 #define DMA_CCR_PINC_Pos       (6U)
1860 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
1861 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
1862 #define DMA_CCR_MINC_Pos       (7U)
1863 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
1864 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
1865 
1866 #define DMA_CCR_PSIZE_Pos      (8U)
1867 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
1868 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
1869 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
1870 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
1871 
1872 #define DMA_CCR_MSIZE_Pos      (10U)
1873 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
1874 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
1875 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
1876 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
1877 
1878 #define DMA_CCR_PL_Pos         (12U)
1879 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
1880 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
1881 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
1882 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
1883 
1884 #define DMA_CCR_MEM2MEM_Pos    (14U)
1885 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
1886 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
1887 
1888 /******************  Bit definition for DMA_CNDTR register  *******************/
1889 #define DMA_CNDTR_NDT_Pos      (0U)
1890 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
1891 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
1892 
1893 /******************  Bit definition for DMA_CPAR register  ********************/
1894 #define DMA_CPAR_PA_Pos        (0U)
1895 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
1896 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
1897 
1898 /******************  Bit definition for DMA_CMAR register  ********************/
1899 #define DMA_CMAR_MA_Pos        (0U)
1900 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
1901 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
1902 
1903 /******************************************************************************/
1904 /*                                                                            */
1905 /*                 External Interrupt/Event Controller (EXTI)                 */
1906 /*                                                                            */
1907 /******************************************************************************/
1908 /*******************  Bit definition for EXTI_IMR register  *******************/
1909 #define EXTI_IMR_MR0_Pos          (0U)
1910 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
1911 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0  */
1912 #define EXTI_IMR_MR1_Pos          (1U)
1913 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
1914 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1  */
1915 #define EXTI_IMR_MR2_Pos          (2U)
1916 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
1917 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2  */
1918 #define EXTI_IMR_MR3_Pos          (3U)
1919 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
1920 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3  */
1921 #define EXTI_IMR_MR4_Pos          (4U)
1922 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
1923 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4  */
1924 #define EXTI_IMR_MR5_Pos          (5U)
1925 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
1926 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5  */
1927 #define EXTI_IMR_MR6_Pos          (6U)
1928 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
1929 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6  */
1930 #define EXTI_IMR_MR7_Pos          (7U)
1931 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
1932 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7  */
1933 #define EXTI_IMR_MR8_Pos          (8U)
1934 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
1935 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8  */
1936 #define EXTI_IMR_MR9_Pos          (9U)
1937 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
1938 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9  */
1939 #define EXTI_IMR_MR10_Pos         (10U)
1940 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
1941 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
1942 #define EXTI_IMR_MR11_Pos         (11U)
1943 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
1944 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
1945 #define EXTI_IMR_MR12_Pos         (12U)
1946 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
1947 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
1948 #define EXTI_IMR_MR13_Pos         (13U)
1949 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
1950 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
1951 #define EXTI_IMR_MR14_Pos         (14U)
1952 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
1953 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
1954 #define EXTI_IMR_MR15_Pos         (15U)
1955 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
1956 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
1957 #define EXTI_IMR_MR16_Pos         (16U)
1958 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
1959 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
1960 #define EXTI_IMR_MR17_Pos         (17U)
1961 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
1962 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
1963 #define EXTI_IMR_MR19_Pos         (19U)
1964 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
1965 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
1966 #define EXTI_IMR_MR20_Pos         (20U)
1967 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
1968 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
1969 #define EXTI_IMR_MR21_Pos         (21U)
1970 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
1971 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
1972 #define EXTI_IMR_MR22_Pos         (22U)
1973 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
1974 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
1975 #define EXTI_IMR_MR23_Pos         (23U)
1976 #define EXTI_IMR_MR23_Msk         (0x1UL << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */
1977 #define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */
1978 #define EXTI_IMR_MR25_Pos         (25U)
1979 #define EXTI_IMR_MR25_Msk         (0x1UL << EXTI_IMR_MR25_Pos)                  /*!< 0x02000000 */
1980 #define EXTI_IMR_MR25             EXTI_IMR_MR25_Msk                            /*!< Interrupt Mask on line 25 */
1981 #define EXTI_IMR_MR26_Pos         (26U)
1982 #define EXTI_IMR_MR26_Msk         (0x1UL << EXTI_IMR_MR26_Pos)                  /*!< 0x04000000 */
1983 #define EXTI_IMR_MR26             EXTI_IMR_MR26_Msk                            /*!< Interrupt Mask on line 26 */
1984 #define EXTI_IMR_MR27_Pos         (27U)
1985 #define EXTI_IMR_MR27_Msk         (0x1UL << EXTI_IMR_MR27_Pos)                  /*!< 0x08000000 */
1986 #define EXTI_IMR_MR27             EXTI_IMR_MR27_Msk                            /*!< Interrupt Mask on line 27 */
1987 #define EXTI_IMR_MR31_Pos         (31U)
1988 #define EXTI_IMR_MR31_Msk         (0x1UL << EXTI_IMR_MR31_Pos)                  /*!< 0x80000000 */
1989 #define EXTI_IMR_MR31             EXTI_IMR_MR31_Msk                            /*!< Interrupt Mask on line 31 */
1990 
1991 /* References Defines */
1992 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
1993 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
1994 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
1995 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
1996 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
1997 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
1998 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
1999 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
2000 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
2001 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
2002 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
2003 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
2004 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
2005 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
2006 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
2007 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
2008 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
2009 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
2010 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
2011 #define  EXTI_IMR_IM20 EXTI_IMR_MR20
2012 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
2013 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
2014 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
2015 #define  EXTI_IMR_IM25 EXTI_IMR_MR25
2016 #define  EXTI_IMR_IM26 EXTI_IMR_MR26
2017 #define  EXTI_IMR_IM27 EXTI_IMR_MR27
2018 #define  EXTI_IMR_IM31 EXTI_IMR_MR31
2019 
2020 #define EXTI_IMR_IM_Pos           (0U)
2021 #define EXTI_IMR_IM_Msk           (0x8EFFFFFFUL << EXTI_IMR_IM_Pos)             /*!< 0x8EFFFFFF */
2022 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
2023 
2024 
2025 /******************  Bit definition for EXTI_EMR register  ********************/
2026 #define EXTI_EMR_MR0_Pos          (0U)
2027 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
2028 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0  */
2029 #define EXTI_EMR_MR1_Pos          (1U)
2030 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
2031 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1  */
2032 #define EXTI_EMR_MR2_Pos          (2U)
2033 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
2034 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2  */
2035 #define EXTI_EMR_MR3_Pos          (3U)
2036 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
2037 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3  */
2038 #define EXTI_EMR_MR4_Pos          (4U)
2039 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
2040 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4  */
2041 #define EXTI_EMR_MR5_Pos          (5U)
2042 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
2043 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5  */
2044 #define EXTI_EMR_MR6_Pos          (6U)
2045 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
2046 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6  */
2047 #define EXTI_EMR_MR7_Pos          (7U)
2048 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
2049 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7  */
2050 #define EXTI_EMR_MR8_Pos          (8U)
2051 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
2052 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8  */
2053 #define EXTI_EMR_MR9_Pos          (9U)
2054 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
2055 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9  */
2056 #define EXTI_EMR_MR10_Pos         (10U)
2057 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
2058 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
2059 #define EXTI_EMR_MR11_Pos         (11U)
2060 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
2061 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
2062 #define EXTI_EMR_MR12_Pos         (12U)
2063 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
2064 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
2065 #define EXTI_EMR_MR13_Pos         (13U)
2066 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
2067 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
2068 #define EXTI_EMR_MR14_Pos         (14U)
2069 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
2070 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
2071 #define EXTI_EMR_MR15_Pos         (15U)
2072 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
2073 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
2074 #define EXTI_EMR_MR16_Pos         (16U)
2075 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
2076 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
2077 #define EXTI_EMR_MR17_Pos         (17U)
2078 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
2079 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
2080 #define EXTI_EMR_MR19_Pos         (19U)
2081 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
2082 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
2083 #define EXTI_EMR_MR20_Pos         (20U)
2084 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
2085 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
2086 #define EXTI_EMR_MR21_Pos         (21U)
2087 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
2088 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
2089 #define EXTI_EMR_MR22_Pos         (22U)
2090 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
2091 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
2092 #define EXTI_EMR_MR23_Pos         (23U)
2093 #define EXTI_EMR_MR23_Msk         (0x1UL << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */
2094 #define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */
2095 #define EXTI_EMR_MR25_Pos         (25U)
2096 #define EXTI_EMR_MR25_Msk         (0x1UL << EXTI_EMR_MR25_Pos)                  /*!< 0x02000000 */
2097 #define EXTI_EMR_MR25             EXTI_EMR_MR25_Msk                            /*!< Event Mask on line 25 */
2098 #define EXTI_EMR_MR26_Pos         (26U)
2099 #define EXTI_EMR_MR26_Msk         (0x1UL << EXTI_EMR_MR26_Pos)                  /*!< 0x04000000 */
2100 #define EXTI_EMR_MR26             EXTI_EMR_MR26_Msk                            /*!< Event Mask on line 26 */
2101 #define EXTI_EMR_MR27_Pos         (27U)
2102 #define EXTI_EMR_MR27_Msk         (0x1UL << EXTI_EMR_MR27_Pos)                  /*!< 0x08000000 */
2103 #define EXTI_EMR_MR27             EXTI_EMR_MR27_Msk                            /*!< Event Mask on line 27 */
2104 #define EXTI_EMR_MR31_Pos         (31U)
2105 #define EXTI_EMR_MR31_Msk         (0x1UL << EXTI_EMR_MR31_Pos)                  /*!< 0x80000000 */
2106 #define EXTI_EMR_MR31             EXTI_EMR_MR31_Msk                            /*!< Event Mask on line 31 */
2107 
2108 /* References Defines */
2109 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
2110 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
2111 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
2112 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
2113 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
2114 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
2115 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
2116 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
2117 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
2118 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
2119 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
2120 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
2121 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
2122 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
2123 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
2124 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
2125 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
2126 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
2127 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
2128 #define  EXTI_EMR_EM20 EXTI_EMR_MR20
2129 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
2130 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
2131 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
2132 #define  EXTI_EMR_EM25 EXTI_EMR_MR25
2133 #define  EXTI_EMR_EM26 EXTI_EMR_MR26
2134 #define  EXTI_EMR_EM27 EXTI_EMR_MR27
2135 #define  EXTI_EMR_EM31 EXTI_EMR_MR31
2136 
2137 /*******************  Bit definition for EXTI_RTSR register  ******************/
2138 #define EXTI_RTSR_TR0_Pos         (0U)
2139 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
2140 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
2141 #define EXTI_RTSR_TR1_Pos         (1U)
2142 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
2143 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
2144 #define EXTI_RTSR_TR2_Pos         (2U)
2145 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
2146 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
2147 #define EXTI_RTSR_TR3_Pos         (3U)
2148 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
2149 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
2150 #define EXTI_RTSR_TR4_Pos         (4U)
2151 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
2152 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
2153 #define EXTI_RTSR_TR5_Pos         (5U)
2154 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
2155 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
2156 #define EXTI_RTSR_TR6_Pos         (6U)
2157 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
2158 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
2159 #define EXTI_RTSR_TR7_Pos         (7U)
2160 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
2161 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
2162 #define EXTI_RTSR_TR8_Pos         (8U)
2163 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
2164 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
2165 #define EXTI_RTSR_TR9_Pos         (9U)
2166 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
2167 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
2168 #define EXTI_RTSR_TR10_Pos        (10U)
2169 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
2170 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
2171 #define EXTI_RTSR_TR11_Pos        (11U)
2172 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
2173 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
2174 #define EXTI_RTSR_TR12_Pos        (12U)
2175 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
2176 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
2177 #define EXTI_RTSR_TR13_Pos        (13U)
2178 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
2179 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
2180 #define EXTI_RTSR_TR14_Pos        (14U)
2181 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
2182 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
2183 #define EXTI_RTSR_TR15_Pos        (15U)
2184 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
2185 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
2186 #define EXTI_RTSR_TR16_Pos        (16U)
2187 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
2188 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
2189 #define EXTI_RTSR_TR17_Pos        (17U)
2190 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
2191 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
2192 #define EXTI_RTSR_TR19_Pos        (19U)
2193 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
2194 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
2195 #define EXTI_RTSR_TR20_Pos        (20U)
2196 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
2197 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
2198 #define EXTI_RTSR_TR21_Pos        (21U)
2199 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
2200 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
2201 #define EXTI_RTSR_TR22_Pos        (22U)
2202 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
2203 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
2204 #define EXTI_RTSR_TR31_Pos        (31U)
2205 #define EXTI_RTSR_TR31_Msk        (0x1UL << EXTI_RTSR_TR31_Pos)                 /*!< 0x80000000 */
2206 #define EXTI_RTSR_TR31            EXTI_RTSR_TR31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
2207 
2208 /* References Defines */
2209 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
2210 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
2211 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
2212 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
2213 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
2214 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
2215 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
2216 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
2217 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
2218 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
2219 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
2220 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
2221 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
2222 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
2223 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
2224 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
2225 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
2226 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
2227 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
2228 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
2229 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
2230 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
2231 #define  EXTI_RTSR_RT31 EXTI_RTSR_TR31
2232 
2233 /*******************  Bit definition for EXTI_FTSR register *******************/
2234 #define EXTI_FTSR_TR0_Pos         (0U)
2235 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
2236 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
2237 #define EXTI_FTSR_TR1_Pos         (1U)
2238 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
2239 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
2240 #define EXTI_FTSR_TR2_Pos         (2U)
2241 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
2242 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
2243 #define EXTI_FTSR_TR3_Pos         (3U)
2244 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
2245 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
2246 #define EXTI_FTSR_TR4_Pos         (4U)
2247 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
2248 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
2249 #define EXTI_FTSR_TR5_Pos         (5U)
2250 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
2251 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
2252 #define EXTI_FTSR_TR6_Pos         (6U)
2253 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
2254 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
2255 #define EXTI_FTSR_TR7_Pos         (7U)
2256 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
2257 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
2258 #define EXTI_FTSR_TR8_Pos         (8U)
2259 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
2260 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
2261 #define EXTI_FTSR_TR9_Pos         (9U)
2262 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
2263 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
2264 #define EXTI_FTSR_TR10_Pos        (10U)
2265 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
2266 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
2267 #define EXTI_FTSR_TR11_Pos        (11U)
2268 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
2269 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
2270 #define EXTI_FTSR_TR12_Pos        (12U)
2271 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
2272 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
2273 #define EXTI_FTSR_TR13_Pos        (13U)
2274 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
2275 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
2276 #define EXTI_FTSR_TR14_Pos        (14U)
2277 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
2278 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
2279 #define EXTI_FTSR_TR15_Pos        (15U)
2280 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
2281 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
2282 #define EXTI_FTSR_TR16_Pos        (16U)
2283 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
2284 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
2285 #define EXTI_FTSR_TR17_Pos        (17U)
2286 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
2287 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
2288 #define EXTI_FTSR_TR19_Pos        (19U)
2289 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
2290 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
2291 #define EXTI_FTSR_TR20_Pos        (20U)
2292 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
2293 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
2294 #define EXTI_FTSR_TR21_Pos        (21U)
2295 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
2296 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
2297 #define EXTI_FTSR_TR22_Pos        (22U)
2298 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
2299 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
2300 #define EXTI_FTSR_TR31_Pos        (31U)
2301 #define EXTI_FTSR_TR31_Msk        (0x1UL << EXTI_FTSR_TR31_Pos)                 /*!< 0x80000000 */
2302 #define EXTI_FTSR_TR31            EXTI_FTSR_TR31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
2303 
2304 /* References Defines */
2305 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
2306 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
2307 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
2308 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
2309 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
2310 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
2311 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
2312 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
2313 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
2314 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
2315 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
2316 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
2317 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
2318 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
2319 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
2320 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
2321 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
2322 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
2323 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
2324 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
2325 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
2326 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
2327 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
2328 
2329 /******************* Bit definition for EXTI_SWIER register *******************/
2330 #define EXTI_SWIER_SWIER0_Pos     (0U)
2331 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
2332 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0  */
2333 #define EXTI_SWIER_SWIER1_Pos     (1U)
2334 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
2335 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1  */
2336 #define EXTI_SWIER_SWIER2_Pos     (2U)
2337 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
2338 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2  */
2339 #define EXTI_SWIER_SWIER3_Pos     (3U)
2340 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
2341 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3  */
2342 #define EXTI_SWIER_SWIER4_Pos     (4U)
2343 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
2344 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4  */
2345 #define EXTI_SWIER_SWIER5_Pos     (5U)
2346 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
2347 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5  */
2348 #define EXTI_SWIER_SWIER6_Pos     (6U)
2349 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
2350 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6  */
2351 #define EXTI_SWIER_SWIER7_Pos     (7U)
2352 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
2353 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7  */
2354 #define EXTI_SWIER_SWIER8_Pos     (8U)
2355 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
2356 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8  */
2357 #define EXTI_SWIER_SWIER9_Pos     (9U)
2358 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
2359 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9  */
2360 #define EXTI_SWIER_SWIER10_Pos    (10U)
2361 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
2362 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
2363 #define EXTI_SWIER_SWIER11_Pos    (11U)
2364 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
2365 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
2366 #define EXTI_SWIER_SWIER12_Pos    (12U)
2367 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
2368 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
2369 #define EXTI_SWIER_SWIER13_Pos    (13U)
2370 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
2371 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
2372 #define EXTI_SWIER_SWIER14_Pos    (14U)
2373 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
2374 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
2375 #define EXTI_SWIER_SWIER15_Pos    (15U)
2376 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
2377 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
2378 #define EXTI_SWIER_SWIER16_Pos    (16U)
2379 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
2380 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
2381 #define EXTI_SWIER_SWIER17_Pos    (17U)
2382 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
2383 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
2384 #define EXTI_SWIER_SWIER19_Pos    (19U)
2385 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
2386 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
2387 #define EXTI_SWIER_SWIER20_Pos    (20U)
2388 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
2389 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
2390 #define EXTI_SWIER_SWIER21_Pos    (21U)
2391 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
2392 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
2393 #define EXTI_SWIER_SWIER22_Pos    (22U)
2394 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
2395 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
2396 #define EXTI_SWIER_SWIER31_Pos    (31U)
2397 #define EXTI_SWIER_SWIER31_Msk    (0x1UL << EXTI_SWIER_SWIER31_Pos)             /*!< 0x80000000 */
2398 #define EXTI_SWIER_SWIER31        EXTI_SWIER_SWIER31_Msk                       /*!< Software Interrupt on line 31 */
2399 
2400 /* References Defines */
2401 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
2402 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
2403 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
2404 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
2405 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
2406 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
2407 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
2408 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
2409 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
2410 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
2411 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
2412 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
2413 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
2414 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
2415 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
2416 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
2417 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
2418 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
2419 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
2420 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
2421 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
2422 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
2423 #define  EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
2424 
2425 /******************  Bit definition for EXTI_PR register  *********************/
2426 #define EXTI_PR_PR0_Pos           (0U)
2427 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
2428 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit 0  */
2429 #define EXTI_PR_PR1_Pos           (1U)
2430 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
2431 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit 1  */
2432 #define EXTI_PR_PR2_Pos           (2U)
2433 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
2434 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit 2  */
2435 #define EXTI_PR_PR3_Pos           (3U)
2436 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
2437 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit 3  */
2438 #define EXTI_PR_PR4_Pos           (4U)
2439 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
2440 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit 4  */
2441 #define EXTI_PR_PR5_Pos           (5U)
2442 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
2443 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit 5  */
2444 #define EXTI_PR_PR6_Pos           (6U)
2445 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
2446 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit 6  */
2447 #define EXTI_PR_PR7_Pos           (7U)
2448 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
2449 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit 7  */
2450 #define EXTI_PR_PR8_Pos           (8U)
2451 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
2452 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit 8  */
2453 #define EXTI_PR_PR9_Pos           (9U)
2454 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
2455 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit 9  */
2456 #define EXTI_PR_PR10_Pos          (10U)
2457 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
2458 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit 10 */
2459 #define EXTI_PR_PR11_Pos          (11U)
2460 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
2461 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit 11 */
2462 #define EXTI_PR_PR12_Pos          (12U)
2463 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
2464 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit 12 */
2465 #define EXTI_PR_PR13_Pos          (13U)
2466 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
2467 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit 13 */
2468 #define EXTI_PR_PR14_Pos          (14U)
2469 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
2470 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit 14 */
2471 #define EXTI_PR_PR15_Pos          (15U)
2472 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
2473 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit 15 */
2474 #define EXTI_PR_PR16_Pos          (16U)
2475 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
2476 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit 16 */
2477 #define EXTI_PR_PR17_Pos          (17U)
2478 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
2479 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit 17 */
2480 #define EXTI_PR_PR19_Pos          (19U)
2481 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
2482 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit 19 */
2483 #define EXTI_PR_PR20_Pos          (20U)
2484 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
2485 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit 20 */
2486 #define EXTI_PR_PR21_Pos          (21U)
2487 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
2488 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit 21 */
2489 #define EXTI_PR_PR22_Pos          (22U)
2490 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
2491 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit 22 */
2492 #define EXTI_PR_PR31_Pos          (31U)
2493 #define EXTI_PR_PR31_Msk          (0x1UL << EXTI_PR_PR31_Pos)                   /*!< 0x80000000 */
2494 #define EXTI_PR_PR31              EXTI_PR_PR31_Msk                             /*!< Pending bit 31 */
2495 
2496 /* References Defines */
2497 #define EXTI_PR_PIF0 EXTI_PR_PR0
2498 #define EXTI_PR_PIF1 EXTI_PR_PR1
2499 #define EXTI_PR_PIF2 EXTI_PR_PR2
2500 #define EXTI_PR_PIF3 EXTI_PR_PR3
2501 #define EXTI_PR_PIF4 EXTI_PR_PR4
2502 #define EXTI_PR_PIF5 EXTI_PR_PR5
2503 #define EXTI_PR_PIF6 EXTI_PR_PR6
2504 #define EXTI_PR_PIF7 EXTI_PR_PR7
2505 #define EXTI_PR_PIF8 EXTI_PR_PR8
2506 #define EXTI_PR_PIF9 EXTI_PR_PR9
2507 #define EXTI_PR_PIF10 EXTI_PR_PR10
2508 #define EXTI_PR_PIF11 EXTI_PR_PR11
2509 #define EXTI_PR_PIF12 EXTI_PR_PR12
2510 #define EXTI_PR_PIF13 EXTI_PR_PR13
2511 #define EXTI_PR_PIF14 EXTI_PR_PR14
2512 #define EXTI_PR_PIF15 EXTI_PR_PR15
2513 #define EXTI_PR_PIF16 EXTI_PR_PR16
2514 #define EXTI_PR_PIF17 EXTI_PR_PR17
2515 #define EXTI_PR_PIF19 EXTI_PR_PR19
2516 #define EXTI_PR_PIF20 EXTI_PR_PR20
2517 #define EXTI_PR_PIF21 EXTI_PR_PR21
2518 #define EXTI_PR_PIF22 EXTI_PR_PR22
2519 #define EXTI_PR_PIF31 EXTI_PR_PR31
2520 
2521 /******************************************************************************/
2522 /*                                                                            */
2523 /*                      FLASH and Option Bytes Registers                      */
2524 /*                                                                            */
2525 /******************************************************************************/
2526 
2527 /*******************  Bit definition for FLASH_ACR register  ******************/
2528 #define FLASH_ACR_LATENCY_Pos             (0U)
2529 #define FLASH_ACR_LATENCY_Msk             (0x1UL << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000001 */
2530 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                /*!< LATENCY bit (Latency) */
2531 
2532 #define FLASH_ACR_PRFTBE_Pos              (4U)
2533 #define FLASH_ACR_PRFTBE_Msk              (0x1UL << FLASH_ACR_PRFTBE_Pos)       /*!< 0x00000010 */
2534 #define FLASH_ACR_PRFTBE                  FLASH_ACR_PRFTBE_Msk                 /*!< Prefetch Buffer Enable */
2535 #define FLASH_ACR_PRFTBS_Pos              (5U)
2536 #define FLASH_ACR_PRFTBS_Msk              (0x1UL << FLASH_ACR_PRFTBS_Pos)       /*!< 0x00000020 */
2537 #define FLASH_ACR_PRFTBS                  FLASH_ACR_PRFTBS_Msk                 /*!< Prefetch Buffer Status */
2538 
2539 /******************  Bit definition for FLASH_KEYR register  ******************/
2540 #define FLASH_KEYR_FKEYR_Pos              (0U)
2541 #define FLASH_KEYR_FKEYR_Msk              (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
2542 #define FLASH_KEYR_FKEYR                  FLASH_KEYR_FKEYR_Msk                 /*!< FPEC Key */
2543 
2544 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
2545 #define FLASH_OPTKEYR_OPTKEYR_Pos         (0U)
2546 #define FLASH_OPTKEYR_OPTKEYR_Msk         (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2547 #define FLASH_OPTKEYR_OPTKEYR             FLASH_OPTKEYR_OPTKEYR_Msk            /*!< Option Byte Key */
2548 
2549 /******************  FLASH Keys  **********************************************/
2550 #define FLASH_KEY1_Pos                    (0U)
2551 #define FLASH_KEY1_Msk                    (0x45670123UL << FLASH_KEY1_Pos)      /*!< 0x45670123 */
2552 #define FLASH_KEY1                        FLASH_KEY1_Msk                       /*!< Flash program erase key1 */
2553 #define FLASH_KEY2_Pos                    (0U)
2554 #define FLASH_KEY2_Msk                    (0xCDEF89ABUL << FLASH_KEY2_Pos)      /*!< 0xCDEF89AB */
2555 #define FLASH_KEY2                        FLASH_KEY2_Msk                       /*!< Flash program erase key2: used with FLASH_PEKEY1
2556                                                                                 to unlock the write access to the FPEC. */
2557 
2558 #define FLASH_OPTKEY1_Pos                 (0U)
2559 #define FLASH_OPTKEY1_Msk                 (0x45670123UL << FLASH_OPTKEY1_Pos)   /*!< 0x45670123 */
2560 #define FLASH_OPTKEY1                     FLASH_OPTKEY1_Msk                    /*!< Flash option key1 */
2561 #define FLASH_OPTKEY2_Pos                 (0U)
2562 #define FLASH_OPTKEY2_Msk                 (0xCDEF89ABUL << FLASH_OPTKEY2_Pos)   /*!< 0xCDEF89AB */
2563 #define FLASH_OPTKEY2                     FLASH_OPTKEY2_Msk                    /*!< Flash option key2: used with FLASH_OPTKEY1 to
2564                                                                                 unlock the write access to the option byte block */
2565 
2566 /******************  Bit definition for FLASH_SR register  *******************/
2567 #define FLASH_SR_BSY_Pos                  (0U)
2568 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)           /*!< 0x00000001 */
2569 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     /*!< Busy */
2570 #define FLASH_SR_PGERR_Pos                (2U)
2571 #define FLASH_SR_PGERR_Msk                (0x1UL << FLASH_SR_PGERR_Pos)         /*!< 0x00000004 */
2572 #define FLASH_SR_PGERR                    FLASH_SR_PGERR_Msk                   /*!< Programming Error */
2573 #define FLASH_SR_WRPRTERR_Pos             (4U)
2574 #define FLASH_SR_WRPRTERR_Msk             (0x1UL << FLASH_SR_WRPRTERR_Pos)      /*!< 0x00000010 */
2575 #define FLASH_SR_WRPRTERR                 FLASH_SR_WRPRTERR_Msk                /*!< Write Protection Error */
2576 #define FLASH_SR_EOP_Pos                  (5U)
2577 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)           /*!< 0x00000020 */
2578 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     /*!< End of operation */
2579 #define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
2580 
2581 /*******************  Bit definition for FLASH_CR register  *******************/
2582 #define FLASH_CR_PG_Pos                   (0U)
2583 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
2584 #define FLASH_CR_PG                       FLASH_CR_PG_Msk                      /*!< Programming */
2585 #define FLASH_CR_PER_Pos                  (1U)
2586 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
2587 #define FLASH_CR_PER                      FLASH_CR_PER_Msk                     /*!< Page Erase */
2588 #define FLASH_CR_MER_Pos                  (2U)
2589 #define FLASH_CR_MER_Msk                  (0x1UL << FLASH_CR_MER_Pos)           /*!< 0x00000004 */
2590 #define FLASH_CR_MER                      FLASH_CR_MER_Msk                     /*!< Mass Erase */
2591 #define FLASH_CR_OPTPG_Pos                (4U)
2592 #define FLASH_CR_OPTPG_Msk                (0x1UL << FLASH_CR_OPTPG_Pos)         /*!< 0x00000010 */
2593 #define FLASH_CR_OPTPG                    FLASH_CR_OPTPG_Msk                   /*!< Option Byte Programming */
2594 #define FLASH_CR_OPTER_Pos                (5U)
2595 #define FLASH_CR_OPTER_Msk                (0x1UL << FLASH_CR_OPTER_Pos)         /*!< 0x00000020 */
2596 #define FLASH_CR_OPTER                    FLASH_CR_OPTER_Msk                   /*!< Option Byte Erase */
2597 #define FLASH_CR_STRT_Pos                 (6U)
2598 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)          /*!< 0x00000040 */
2599 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    /*!< Start */
2600 #define FLASH_CR_LOCK_Pos                 (7U)
2601 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)          /*!< 0x00000080 */
2602 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    /*!< Lock */
2603 #define FLASH_CR_OPTWRE_Pos               (9U)
2604 #define FLASH_CR_OPTWRE_Msk               (0x1UL << FLASH_CR_OPTWRE_Pos)        /*!< 0x00000200 */
2605 #define FLASH_CR_OPTWRE                   FLASH_CR_OPTWRE_Msk                  /*!< Option Bytes Write Enable */
2606 #define FLASH_CR_ERRIE_Pos                (10U)
2607 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)         /*!< 0x00000400 */
2608 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
2609 #define FLASH_CR_EOPIE_Pos                (12U)
2610 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)         /*!< 0x00001000 */
2611 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   /*!< End of operation interrupt enable */
2612 #define FLASH_CR_OBL_LAUNCH_Pos           (13U)
2613 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x00002000 */
2614 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              /*!< Option Bytes Loader Launch */
2615 
2616 /*******************  Bit definition for FLASH_AR register  *******************/
2617 #define FLASH_AR_FAR_Pos                  (0U)
2618 #define FLASH_AR_FAR_Msk                  (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)    /*!< 0xFFFFFFFF */
2619 #define FLASH_AR_FAR                      FLASH_AR_FAR_Msk                     /*!< Flash Address */
2620 
2621 /******************  Bit definition for FLASH_OBR register  *******************/
2622 #define FLASH_OBR_OPTERR_Pos              (0U)
2623 #define FLASH_OBR_OPTERR_Msk              (0x1UL << FLASH_OBR_OPTERR_Pos)       /*!< 0x00000001 */
2624 #define FLASH_OBR_OPTERR                  FLASH_OBR_OPTERR_Msk                 /*!< Option Byte Error */
2625 #define FLASH_OBR_RDPRT1_Pos              (1U)
2626 #define FLASH_OBR_RDPRT1_Msk              (0x1UL << FLASH_OBR_RDPRT1_Pos)       /*!< 0x00000002 */
2627 #define FLASH_OBR_RDPRT1                  FLASH_OBR_RDPRT1_Msk                 /*!< Read protection Level 1 */
2628 #define FLASH_OBR_RDPRT2_Pos              (2U)
2629 #define FLASH_OBR_RDPRT2_Msk              (0x1UL << FLASH_OBR_RDPRT2_Pos)       /*!< 0x00000004 */
2630 #define FLASH_OBR_RDPRT2                  FLASH_OBR_RDPRT2_Msk                 /*!< Read protection Level 2 */
2631 
2632 #define FLASH_OBR_USER_Pos                (8U)
2633 #define FLASH_OBR_USER_Msk                (0x77UL << FLASH_OBR_USER_Pos)        /*!< 0x00007700 */
2634 #define FLASH_OBR_USER                    FLASH_OBR_USER_Msk                   /*!< User Option Bytes */
2635 #define FLASH_OBR_IWDG_SW_Pos             (8U)
2636 #define FLASH_OBR_IWDG_SW_Msk             (0x1UL << FLASH_OBR_IWDG_SW_Pos)      /*!< 0x00000100 */
2637 #define FLASH_OBR_IWDG_SW                 FLASH_OBR_IWDG_SW_Msk                /*!< IWDG SW */
2638 #define FLASH_OBR_nRST_STOP_Pos           (9U)
2639 #define FLASH_OBR_nRST_STOP_Msk           (0x1UL << FLASH_OBR_nRST_STOP_Pos)    /*!< 0x00000200 */
2640 #define FLASH_OBR_nRST_STOP               FLASH_OBR_nRST_STOP_Msk              /*!< nRST_STOP */
2641 #define FLASH_OBR_nRST_STDBY_Pos          (10U)
2642 #define FLASH_OBR_nRST_STDBY_Msk          (0x1UL << FLASH_OBR_nRST_STDBY_Pos)   /*!< 0x00000400 */
2643 #define FLASH_OBR_nRST_STDBY              FLASH_OBR_nRST_STDBY_Msk             /*!< nRST_STDBY */
2644 #define FLASH_OBR_nBOOT1_Pos              (12U)
2645 #define FLASH_OBR_nBOOT1_Msk              (0x1UL << FLASH_OBR_nBOOT1_Pos)       /*!< 0x00001000 */
2646 #define FLASH_OBR_nBOOT1                  FLASH_OBR_nBOOT1_Msk                 /*!< nBOOT1 */
2647 #define FLASH_OBR_VDDA_MONITOR_Pos        (13U)
2648 #define FLASH_OBR_VDDA_MONITOR_Msk        (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
2649 #define FLASH_OBR_VDDA_MONITOR            FLASH_OBR_VDDA_MONITOR_Msk           /*!< VDDA power supply supervisor */
2650 #define FLASH_OBR_RAM_PARITY_CHECK_Pos    (14U)
2651 #define FLASH_OBR_RAM_PARITY_CHECK_Msk    (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
2652 #define FLASH_OBR_RAM_PARITY_CHECK        FLASH_OBR_RAM_PARITY_CHECK_Msk       /*!< RAM parity check */
2653 #define FLASH_OBR_DATA0_Pos               (16U)
2654 #define FLASH_OBR_DATA0_Msk               (0xFFUL << FLASH_OBR_DATA0_Pos)       /*!< 0x00FF0000 */
2655 #define FLASH_OBR_DATA0                   FLASH_OBR_DATA0_Msk                  /*!< Data0 */
2656 #define FLASH_OBR_DATA1_Pos               (24U)
2657 #define FLASH_OBR_DATA1_Msk               (0xFFUL << FLASH_OBR_DATA1_Pos)       /*!< 0xFF000000 */
2658 #define FLASH_OBR_DATA1                   FLASH_OBR_DATA1_Msk                  /*!< Data1 */
2659 
2660 /* Old BOOT1 bit definition, maintained for legacy purpose */
2661 #define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
2662 
2663 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
2664 #define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
2665 
2666 /******************  Bit definition for FLASH_WRPR register  ******************/
2667 #define FLASH_WRPR_WRP_Pos                (0U)
2668 #define FLASH_WRPR_WRP_Msk                (0xFFFFUL << FLASH_WRPR_WRP_Pos)      /*!< 0x0000FFFF */
2669 #define FLASH_WRPR_WRP                    FLASH_WRPR_WRP_Msk                   /*!< Write Protect */
2670 
2671 /*----------------------------------------------------------------------------*/
2672 
2673 /******************  Bit definition for OB_RDP register  **********************/
2674 #define OB_RDP_RDP_Pos       (0U)
2675 #define OB_RDP_RDP_Msk       (0xFFUL << OB_RDP_RDP_Pos)                         /*!< 0x000000FF */
2676 #define OB_RDP_RDP           OB_RDP_RDP_Msk                                    /*!< Read protection option byte */
2677 #define OB_RDP_nRDP_Pos      (8U)
2678 #define OB_RDP_nRDP_Msk      (0xFFUL << OB_RDP_nRDP_Pos)                        /*!< 0x0000FF00 */
2679 #define OB_RDP_nRDP          OB_RDP_nRDP_Msk                                   /*!< Read protection complemented option byte */
2680 
2681 /******************  Bit definition for OB_USER register  *********************/
2682 #define OB_USER_USER_Pos     (16U)
2683 #define OB_USER_USER_Msk     (0xFFUL << OB_USER_USER_Pos)                       /*!< 0x00FF0000 */
2684 #define OB_USER_USER         OB_USER_USER_Msk                                  /*!< User option byte */
2685 #define OB_USER_nUSER_Pos    (24U)
2686 #define OB_USER_nUSER_Msk    (0xFFUL << OB_USER_nUSER_Pos)                      /*!< 0xFF000000 */
2687 #define OB_USER_nUSER        OB_USER_nUSER_Msk                                 /*!< User complemented option byte */
2688 
2689 /******************  Bit definition for OB_WRP0 register  *********************/
2690 #define OB_WRP0_WRP0_Pos     (0U)
2691 #define OB_WRP0_WRP0_Msk     (0xFFUL << OB_WRP0_WRP0_Pos)                       /*!< 0x000000FF */
2692 #define OB_WRP0_WRP0         OB_WRP0_WRP0_Msk                                  /*!< Flash memory write protection option bytes */
2693 #define OB_WRP0_nWRP0_Pos    (8U)
2694 #define OB_WRP0_nWRP0_Msk    (0xFFUL << OB_WRP0_nWRP0_Pos)                      /*!< 0x0000FF00 */
2695 #define OB_WRP0_nWRP0        OB_WRP0_nWRP0_Msk                                 /*!< Flash memory write protection complemented option bytes */
2696 
2697 /******************  Bit definition for OB_WRP1 register  *********************/
2698 #define OB_WRP1_WRP1_Pos     (16U)
2699 #define OB_WRP1_WRP1_Msk     (0xFFUL << OB_WRP1_WRP1_Pos)                       /*!< 0x00FF0000 */
2700 #define OB_WRP1_WRP1         OB_WRP1_WRP1_Msk                                  /*!< Flash memory write protection option bytes */
2701 #define OB_WRP1_nWRP1_Pos    (24U)
2702 #define OB_WRP1_nWRP1_Msk    (0xFFUL << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
2703 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
2704 
2705 /******************  Bit definition for OB_WRP2 register  *********************/
2706 #define OB_WRP2_WRP2_Pos     (0U)
2707 #define OB_WRP2_WRP2_Msk     (0xFFUL << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
2708 #define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
2709 #define OB_WRP2_nWRP2_Pos    (8U)
2710 #define OB_WRP2_nWRP2_Msk    (0xFFUL << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
2711 #define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
2712 
2713 /******************  Bit definition for OB_WRP3 register  *********************/
2714 #define OB_WRP3_WRP3_Pos     (16U)
2715 #define OB_WRP3_WRP3_Msk     (0xFFUL << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
2716 #define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
2717 #define OB_WRP3_nWRP3_Pos    (24U)
2718 #define OB_WRP3_nWRP3_Msk    (0xFFUL << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
2719 #define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
2720 
2721 /******************************************************************************/
2722 /*                                                                            */
2723 /*                       General Purpose IOs (GPIO)                           */
2724 /*                                                                            */
2725 /******************************************************************************/
2726 /*******************  Bit definition for GPIO_MODER register  *****************/
2727 #define GPIO_MODER_MODER0_Pos           (0U)
2728 #define GPIO_MODER_MODER0_Msk           (0x3UL << GPIO_MODER_MODER0_Pos)        /*!< 0x00000003 */
2729 #define GPIO_MODER_MODER0               GPIO_MODER_MODER0_Msk
2730 #define GPIO_MODER_MODER0_0             (0x1UL << GPIO_MODER_MODER0_Pos)        /*!< 0x00000001 */
2731 #define GPIO_MODER_MODER0_1             (0x2UL << GPIO_MODER_MODER0_Pos)        /*!< 0x00000002 */
2732 #define GPIO_MODER_MODER1_Pos           (2U)
2733 #define GPIO_MODER_MODER1_Msk           (0x3UL << GPIO_MODER_MODER1_Pos)        /*!< 0x0000000C */
2734 #define GPIO_MODER_MODER1               GPIO_MODER_MODER1_Msk
2735 #define GPIO_MODER_MODER1_0             (0x1UL << GPIO_MODER_MODER1_Pos)        /*!< 0x00000004 */
2736 #define GPIO_MODER_MODER1_1             (0x2UL << GPIO_MODER_MODER1_Pos)        /*!< 0x00000008 */
2737 #define GPIO_MODER_MODER2_Pos           (4U)
2738 #define GPIO_MODER_MODER2_Msk           (0x3UL << GPIO_MODER_MODER2_Pos)        /*!< 0x00000030 */
2739 #define GPIO_MODER_MODER2               GPIO_MODER_MODER2_Msk
2740 #define GPIO_MODER_MODER2_0             (0x1UL << GPIO_MODER_MODER2_Pos)        /*!< 0x00000010 */
2741 #define GPIO_MODER_MODER2_1             (0x2UL << GPIO_MODER_MODER2_Pos)        /*!< 0x00000020 */
2742 #define GPIO_MODER_MODER3_Pos           (6U)
2743 #define GPIO_MODER_MODER3_Msk           (0x3UL << GPIO_MODER_MODER3_Pos)        /*!< 0x000000C0 */
2744 #define GPIO_MODER_MODER3               GPIO_MODER_MODER3_Msk
2745 #define GPIO_MODER_MODER3_0             (0x1UL << GPIO_MODER_MODER3_Pos)        /*!< 0x00000040 */
2746 #define GPIO_MODER_MODER3_1             (0x2UL << GPIO_MODER_MODER3_Pos)        /*!< 0x00000080 */
2747 #define GPIO_MODER_MODER4_Pos           (8U)
2748 #define GPIO_MODER_MODER4_Msk           (0x3UL << GPIO_MODER_MODER4_Pos)        /*!< 0x00000300 */
2749 #define GPIO_MODER_MODER4               GPIO_MODER_MODER4_Msk
2750 #define GPIO_MODER_MODER4_0             (0x1UL << GPIO_MODER_MODER4_Pos)        /*!< 0x00000100 */
2751 #define GPIO_MODER_MODER4_1             (0x2UL << GPIO_MODER_MODER4_Pos)        /*!< 0x00000200 */
2752 #define GPIO_MODER_MODER5_Pos           (10U)
2753 #define GPIO_MODER_MODER5_Msk           (0x3UL << GPIO_MODER_MODER5_Pos)        /*!< 0x00000C00 */
2754 #define GPIO_MODER_MODER5               GPIO_MODER_MODER5_Msk
2755 #define GPIO_MODER_MODER5_0             (0x1UL << GPIO_MODER_MODER5_Pos)        /*!< 0x00000400 */
2756 #define GPIO_MODER_MODER5_1             (0x2UL << GPIO_MODER_MODER5_Pos)        /*!< 0x00000800 */
2757 #define GPIO_MODER_MODER6_Pos           (12U)
2758 #define GPIO_MODER_MODER6_Msk           (0x3UL << GPIO_MODER_MODER6_Pos)        /*!< 0x00003000 */
2759 #define GPIO_MODER_MODER6               GPIO_MODER_MODER6_Msk
2760 #define GPIO_MODER_MODER6_0             (0x1UL << GPIO_MODER_MODER6_Pos)        /*!< 0x00001000 */
2761 #define GPIO_MODER_MODER6_1             (0x2UL << GPIO_MODER_MODER6_Pos)        /*!< 0x00002000 */
2762 #define GPIO_MODER_MODER7_Pos           (14U)
2763 #define GPIO_MODER_MODER7_Msk           (0x3UL << GPIO_MODER_MODER7_Pos)        /*!< 0x0000C000 */
2764 #define GPIO_MODER_MODER7               GPIO_MODER_MODER7_Msk
2765 #define GPIO_MODER_MODER7_0             (0x1UL << GPIO_MODER_MODER7_Pos)        /*!< 0x00004000 */
2766 #define GPIO_MODER_MODER7_1             (0x2UL << GPIO_MODER_MODER7_Pos)        /*!< 0x00008000 */
2767 #define GPIO_MODER_MODER8_Pos           (16U)
2768 #define GPIO_MODER_MODER8_Msk           (0x3UL << GPIO_MODER_MODER8_Pos)        /*!< 0x00030000 */
2769 #define GPIO_MODER_MODER8               GPIO_MODER_MODER8_Msk
2770 #define GPIO_MODER_MODER8_0             (0x1UL << GPIO_MODER_MODER8_Pos)        /*!< 0x00010000 */
2771 #define GPIO_MODER_MODER8_1             (0x2UL << GPIO_MODER_MODER8_Pos)        /*!< 0x00020000 */
2772 #define GPIO_MODER_MODER9_Pos           (18U)
2773 #define GPIO_MODER_MODER9_Msk           (0x3UL << GPIO_MODER_MODER9_Pos)        /*!< 0x000C0000 */
2774 #define GPIO_MODER_MODER9               GPIO_MODER_MODER9_Msk
2775 #define GPIO_MODER_MODER9_0             (0x1UL << GPIO_MODER_MODER9_Pos)        /*!< 0x00040000 */
2776 #define GPIO_MODER_MODER9_1             (0x2UL << GPIO_MODER_MODER9_Pos)        /*!< 0x00080000 */
2777 #define GPIO_MODER_MODER10_Pos          (20U)
2778 #define GPIO_MODER_MODER10_Msk          (0x3UL << GPIO_MODER_MODER10_Pos)       /*!< 0x00300000 */
2779 #define GPIO_MODER_MODER10              GPIO_MODER_MODER10_Msk
2780 #define GPIO_MODER_MODER10_0            (0x1UL << GPIO_MODER_MODER10_Pos)       /*!< 0x00100000 */
2781 #define GPIO_MODER_MODER10_1            (0x2UL << GPIO_MODER_MODER10_Pos)       /*!< 0x00200000 */
2782 #define GPIO_MODER_MODER11_Pos          (22U)
2783 #define GPIO_MODER_MODER11_Msk          (0x3UL << GPIO_MODER_MODER11_Pos)       /*!< 0x00C00000 */
2784 #define GPIO_MODER_MODER11              GPIO_MODER_MODER11_Msk
2785 #define GPIO_MODER_MODER11_0            (0x1UL << GPIO_MODER_MODER11_Pos)       /*!< 0x00400000 */
2786 #define GPIO_MODER_MODER11_1            (0x2UL << GPIO_MODER_MODER11_Pos)       /*!< 0x00800000 */
2787 #define GPIO_MODER_MODER12_Pos          (24U)
2788 #define GPIO_MODER_MODER12_Msk          (0x3UL << GPIO_MODER_MODER12_Pos)       /*!< 0x03000000 */
2789 #define GPIO_MODER_MODER12              GPIO_MODER_MODER12_Msk
2790 #define GPIO_MODER_MODER12_0            (0x1UL << GPIO_MODER_MODER12_Pos)       /*!< 0x01000000 */
2791 #define GPIO_MODER_MODER12_1            (0x2UL << GPIO_MODER_MODER12_Pos)       /*!< 0x02000000 */
2792 #define GPIO_MODER_MODER13_Pos          (26U)
2793 #define GPIO_MODER_MODER13_Msk          (0x3UL << GPIO_MODER_MODER13_Pos)       /*!< 0x0C000000 */
2794 #define GPIO_MODER_MODER13              GPIO_MODER_MODER13_Msk
2795 #define GPIO_MODER_MODER13_0            (0x1UL << GPIO_MODER_MODER13_Pos)       /*!< 0x04000000 */
2796 #define GPIO_MODER_MODER13_1            (0x2UL << GPIO_MODER_MODER13_Pos)       /*!< 0x08000000 */
2797 #define GPIO_MODER_MODER14_Pos          (28U)
2798 #define GPIO_MODER_MODER14_Msk          (0x3UL << GPIO_MODER_MODER14_Pos)       /*!< 0x30000000 */
2799 #define GPIO_MODER_MODER14              GPIO_MODER_MODER14_Msk
2800 #define GPIO_MODER_MODER14_0            (0x1UL << GPIO_MODER_MODER14_Pos)       /*!< 0x10000000 */
2801 #define GPIO_MODER_MODER14_1            (0x2UL << GPIO_MODER_MODER14_Pos)       /*!< 0x20000000 */
2802 #define GPIO_MODER_MODER15_Pos          (30U)
2803 #define GPIO_MODER_MODER15_Msk          (0x3UL << GPIO_MODER_MODER15_Pos)       /*!< 0xC0000000 */
2804 #define GPIO_MODER_MODER15              GPIO_MODER_MODER15_Msk
2805 #define GPIO_MODER_MODER15_0            (0x1UL << GPIO_MODER_MODER15_Pos)       /*!< 0x40000000 */
2806 #define GPIO_MODER_MODER15_1            (0x2UL << GPIO_MODER_MODER15_Pos)       /*!< 0x80000000 */
2807 
2808 /******************  Bit definition for GPIO_OTYPER register  *****************/
2809 #define GPIO_OTYPER_OT_0                (0x00000001U)
2810 #define GPIO_OTYPER_OT_1                (0x00000002U)
2811 #define GPIO_OTYPER_OT_2                (0x00000004U)
2812 #define GPIO_OTYPER_OT_3                (0x00000008U)
2813 #define GPIO_OTYPER_OT_4                (0x00000010U)
2814 #define GPIO_OTYPER_OT_5                (0x00000020U)
2815 #define GPIO_OTYPER_OT_6                (0x00000040U)
2816 #define GPIO_OTYPER_OT_7                (0x00000080U)
2817 #define GPIO_OTYPER_OT_8                (0x00000100U)
2818 #define GPIO_OTYPER_OT_9                (0x00000200U)
2819 #define GPIO_OTYPER_OT_10               (0x00000400U)
2820 #define GPIO_OTYPER_OT_11               (0x00000800U)
2821 #define GPIO_OTYPER_OT_12               (0x00001000U)
2822 #define GPIO_OTYPER_OT_13               (0x00002000U)
2823 #define GPIO_OTYPER_OT_14               (0x00004000U)
2824 #define GPIO_OTYPER_OT_15               (0x00008000U)
2825 
2826 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
2827 #define GPIO_OSPEEDR_OSPEEDR0_Pos       (0U)
2828 #define GPIO_OSPEEDR_OSPEEDR0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000003 */
2829 #define GPIO_OSPEEDR_OSPEEDR0           GPIO_OSPEEDR_OSPEEDR0_Msk
2830 #define GPIO_OSPEEDR_OSPEEDR0_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000001 */
2831 #define GPIO_OSPEEDR_OSPEEDR0_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000002 */
2832 #define GPIO_OSPEEDR_OSPEEDR1_Pos       (2U)
2833 #define GPIO_OSPEEDR_OSPEEDR1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x0000000C */
2834 #define GPIO_OSPEEDR_OSPEEDR1           GPIO_OSPEEDR_OSPEEDR1_Msk
2835 #define GPIO_OSPEEDR_OSPEEDR1_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x00000004 */
2836 #define GPIO_OSPEEDR_OSPEEDR1_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x00000008 */
2837 #define GPIO_OSPEEDR_OSPEEDR2_Pos       (4U)
2838 #define GPIO_OSPEEDR_OSPEEDR2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000030 */
2839 #define GPIO_OSPEEDR_OSPEEDR2           GPIO_OSPEEDR_OSPEEDR2_Msk
2840 #define GPIO_OSPEEDR_OSPEEDR2_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000010 */
2841 #define GPIO_OSPEEDR_OSPEEDR2_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000020 */
2842 #define GPIO_OSPEEDR_OSPEEDR3_Pos       (6U)
2843 #define GPIO_OSPEEDR_OSPEEDR3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x000000C0 */
2844 #define GPIO_OSPEEDR_OSPEEDR3           GPIO_OSPEEDR_OSPEEDR3_Msk
2845 #define GPIO_OSPEEDR_OSPEEDR3_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x00000040 */
2846 #define GPIO_OSPEEDR_OSPEEDR3_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x00000080 */
2847 #define GPIO_OSPEEDR_OSPEEDR4_Pos       (8U)
2848 #define GPIO_OSPEEDR_OSPEEDR4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000300 */
2849 #define GPIO_OSPEEDR_OSPEEDR4           GPIO_OSPEEDR_OSPEEDR4_Msk
2850 #define GPIO_OSPEEDR_OSPEEDR4_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000100 */
2851 #define GPIO_OSPEEDR_OSPEEDR4_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000200 */
2852 #define GPIO_OSPEEDR_OSPEEDR5_Pos       (10U)
2853 #define GPIO_OSPEEDR_OSPEEDR5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000C00 */
2854 #define GPIO_OSPEEDR_OSPEEDR5           GPIO_OSPEEDR_OSPEEDR5_Msk
2855 #define GPIO_OSPEEDR_OSPEEDR5_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000400 */
2856 #define GPIO_OSPEEDR_OSPEEDR5_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000800 */
2857 #define GPIO_OSPEEDR_OSPEEDR6_Pos       (12U)
2858 #define GPIO_OSPEEDR_OSPEEDR6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00003000 */
2859 #define GPIO_OSPEEDR_OSPEEDR6           GPIO_OSPEEDR_OSPEEDR6_Msk
2860 #define GPIO_OSPEEDR_OSPEEDR6_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00001000 */
2861 #define GPIO_OSPEEDR_OSPEEDR6_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00002000 */
2862 #define GPIO_OSPEEDR_OSPEEDR7_Pos       (14U)
2863 #define GPIO_OSPEEDR_OSPEEDR7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x0000C000 */
2864 #define GPIO_OSPEEDR_OSPEEDR7           GPIO_OSPEEDR_OSPEEDR7_Msk
2865 #define GPIO_OSPEEDR_OSPEEDR7_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x00004000 */
2866 #define GPIO_OSPEEDR_OSPEEDR7_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x00008000 */
2867 #define GPIO_OSPEEDR_OSPEEDR8_Pos       (16U)
2868 #define GPIO_OSPEEDR_OSPEEDR8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00030000 */
2869 #define GPIO_OSPEEDR_OSPEEDR8           GPIO_OSPEEDR_OSPEEDR8_Msk
2870 #define GPIO_OSPEEDR_OSPEEDR8_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00010000 */
2871 #define GPIO_OSPEEDR_OSPEEDR8_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00020000 */
2872 #define GPIO_OSPEEDR_OSPEEDR9_Pos       (18U)
2873 #define GPIO_OSPEEDR_OSPEEDR9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x000C0000 */
2874 #define GPIO_OSPEEDR_OSPEEDR9           GPIO_OSPEEDR_OSPEEDR9_Msk
2875 #define GPIO_OSPEEDR_OSPEEDR9_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x00040000 */
2876 #define GPIO_OSPEEDR_OSPEEDR9_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x00080000 */
2877 #define GPIO_OSPEEDR_OSPEEDR10_Pos      (20U)
2878 #define GPIO_OSPEEDR_OSPEEDR10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00300000 */
2879 #define GPIO_OSPEEDR_OSPEEDR10          GPIO_OSPEEDR_OSPEEDR10_Msk
2880 #define GPIO_OSPEEDR_OSPEEDR10_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00100000 */
2881 #define GPIO_OSPEEDR_OSPEEDR10_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00200000 */
2882 #define GPIO_OSPEEDR_OSPEEDR11_Pos      (22U)
2883 #define GPIO_OSPEEDR_OSPEEDR11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00C00000 */
2884 #define GPIO_OSPEEDR_OSPEEDR11          GPIO_OSPEEDR_OSPEEDR11_Msk
2885 #define GPIO_OSPEEDR_OSPEEDR11_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00400000 */
2886 #define GPIO_OSPEEDR_OSPEEDR11_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00800000 */
2887 #define GPIO_OSPEEDR_OSPEEDR12_Pos      (24U)
2888 #define GPIO_OSPEEDR_OSPEEDR12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x03000000 */
2889 #define GPIO_OSPEEDR_OSPEEDR12          GPIO_OSPEEDR_OSPEEDR12_Msk
2890 #define GPIO_OSPEEDR_OSPEEDR12_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x01000000 */
2891 #define GPIO_OSPEEDR_OSPEEDR12_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x02000000 */
2892 #define GPIO_OSPEEDR_OSPEEDR13_Pos      (26U)
2893 #define GPIO_OSPEEDR_OSPEEDR13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x0C000000 */
2894 #define GPIO_OSPEEDR_OSPEEDR13          GPIO_OSPEEDR_OSPEEDR13_Msk
2895 #define GPIO_OSPEEDR_OSPEEDR13_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x04000000 */
2896 #define GPIO_OSPEEDR_OSPEEDR13_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x08000000 */
2897 #define GPIO_OSPEEDR_OSPEEDR14_Pos      (28U)
2898 #define GPIO_OSPEEDR_OSPEEDR14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x30000000 */
2899 #define GPIO_OSPEEDR_OSPEEDR14          GPIO_OSPEEDR_OSPEEDR14_Msk
2900 #define GPIO_OSPEEDR_OSPEEDR14_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x10000000 */
2901 #define GPIO_OSPEEDR_OSPEEDR14_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x20000000 */
2902 #define GPIO_OSPEEDR_OSPEEDR15_Pos      (30U)
2903 #define GPIO_OSPEEDR_OSPEEDR15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0xC0000000 */
2904 #define GPIO_OSPEEDR_OSPEEDR15          GPIO_OSPEEDR_OSPEEDR15_Msk
2905 #define GPIO_OSPEEDR_OSPEEDR15_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0x40000000 */
2906 #define GPIO_OSPEEDR_OSPEEDR15_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0x80000000 */
2907 
2908 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
2909 #define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
2910 #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
2911 #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
2912 #define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
2913 #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
2914 #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
2915 #define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
2916 #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
2917 #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
2918 #define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
2919 #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
2920 #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
2921 #define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
2922 #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
2923 #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
2924 #define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
2925 #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
2926 #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
2927 #define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
2928 #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
2929 #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
2930 #define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
2931 #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
2932 #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
2933 #define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
2934 #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
2935 #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
2936 #define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
2937 #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
2938 #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
2939 #define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
2940 #define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
2941 #define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
2942 #define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
2943 #define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
2944 #define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
2945 #define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
2946 #define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
2947 #define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
2948 #define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
2949 #define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
2950 #define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
2951 #define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
2952 #define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
2953 #define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
2954 #define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
2955 #define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
2956 #define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
2957 
2958 /*******************  Bit definition for GPIO_PUPDR register ******************/
2959 #define GPIO_PUPDR_PUPDR0_Pos           (0U)
2960 #define GPIO_PUPDR_PUPDR0_Msk           (0x3UL << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000003 */
2961 #define GPIO_PUPDR_PUPDR0               GPIO_PUPDR_PUPDR0_Msk
2962 #define GPIO_PUPDR_PUPDR0_0             (0x1UL << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000001 */
2963 #define GPIO_PUPDR_PUPDR0_1             (0x2UL << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000002 */
2964 #define GPIO_PUPDR_PUPDR1_Pos           (2U)
2965 #define GPIO_PUPDR_PUPDR1_Msk           (0x3UL << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x0000000C */
2966 #define GPIO_PUPDR_PUPDR1               GPIO_PUPDR_PUPDR1_Msk
2967 #define GPIO_PUPDR_PUPDR1_0             (0x1UL << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x00000004 */
2968 #define GPIO_PUPDR_PUPDR1_1             (0x2UL << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x00000008 */
2969 #define GPIO_PUPDR_PUPDR2_Pos           (4U)
2970 #define GPIO_PUPDR_PUPDR2_Msk           (0x3UL << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000030 */
2971 #define GPIO_PUPDR_PUPDR2               GPIO_PUPDR_PUPDR2_Msk
2972 #define GPIO_PUPDR_PUPDR2_0             (0x1UL << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000010 */
2973 #define GPIO_PUPDR_PUPDR2_1             (0x2UL << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000020 */
2974 #define GPIO_PUPDR_PUPDR3_Pos           (6U)
2975 #define GPIO_PUPDR_PUPDR3_Msk           (0x3UL << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x000000C0 */
2976 #define GPIO_PUPDR_PUPDR3               GPIO_PUPDR_PUPDR3_Msk
2977 #define GPIO_PUPDR_PUPDR3_0             (0x1UL << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x00000040 */
2978 #define GPIO_PUPDR_PUPDR3_1             (0x2UL << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x00000080 */
2979 #define GPIO_PUPDR_PUPDR4_Pos           (8U)
2980 #define GPIO_PUPDR_PUPDR4_Msk           (0x3UL << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000300 */
2981 #define GPIO_PUPDR_PUPDR4               GPIO_PUPDR_PUPDR4_Msk
2982 #define GPIO_PUPDR_PUPDR4_0             (0x1UL << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000100 */
2983 #define GPIO_PUPDR_PUPDR4_1             (0x2UL << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000200 */
2984 #define GPIO_PUPDR_PUPDR5_Pos           (10U)
2985 #define GPIO_PUPDR_PUPDR5_Msk           (0x3UL << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000C00 */
2986 #define GPIO_PUPDR_PUPDR5               GPIO_PUPDR_PUPDR5_Msk
2987 #define GPIO_PUPDR_PUPDR5_0             (0x1UL << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000400 */
2988 #define GPIO_PUPDR_PUPDR5_1             (0x2UL << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000800 */
2989 #define GPIO_PUPDR_PUPDR6_Pos           (12U)
2990 #define GPIO_PUPDR_PUPDR6_Msk           (0x3UL << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00003000 */
2991 #define GPIO_PUPDR_PUPDR6               GPIO_PUPDR_PUPDR6_Msk
2992 #define GPIO_PUPDR_PUPDR6_0             (0x1UL << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00001000 */
2993 #define GPIO_PUPDR_PUPDR6_1             (0x2UL << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00002000 */
2994 #define GPIO_PUPDR_PUPDR7_Pos           (14U)
2995 #define GPIO_PUPDR_PUPDR7_Msk           (0x3UL << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x0000C000 */
2996 #define GPIO_PUPDR_PUPDR7               GPIO_PUPDR_PUPDR7_Msk
2997 #define GPIO_PUPDR_PUPDR7_0             (0x1UL << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x00004000 */
2998 #define GPIO_PUPDR_PUPDR7_1             (0x2UL << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x00008000 */
2999 #define GPIO_PUPDR_PUPDR8_Pos           (16U)
3000 #define GPIO_PUPDR_PUPDR8_Msk           (0x3UL << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00030000 */
3001 #define GPIO_PUPDR_PUPDR8               GPIO_PUPDR_PUPDR8_Msk
3002 #define GPIO_PUPDR_PUPDR8_0             (0x1UL << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00010000 */
3003 #define GPIO_PUPDR_PUPDR8_1             (0x2UL << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00020000 */
3004 #define GPIO_PUPDR_PUPDR9_Pos           (18U)
3005 #define GPIO_PUPDR_PUPDR9_Msk           (0x3UL << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x000C0000 */
3006 #define GPIO_PUPDR_PUPDR9               GPIO_PUPDR_PUPDR9_Msk
3007 #define GPIO_PUPDR_PUPDR9_0             (0x1UL << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x00040000 */
3008 #define GPIO_PUPDR_PUPDR9_1             (0x2UL << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x00080000 */
3009 #define GPIO_PUPDR_PUPDR10_Pos          (20U)
3010 #define GPIO_PUPDR_PUPDR10_Msk          (0x3UL << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00300000 */
3011 #define GPIO_PUPDR_PUPDR10              GPIO_PUPDR_PUPDR10_Msk
3012 #define GPIO_PUPDR_PUPDR10_0            (0x1UL << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00100000 */
3013 #define GPIO_PUPDR_PUPDR10_1            (0x2UL << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00200000 */
3014 #define GPIO_PUPDR_PUPDR11_Pos          (22U)
3015 #define GPIO_PUPDR_PUPDR11_Msk          (0x3UL << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00C00000 */
3016 #define GPIO_PUPDR_PUPDR11              GPIO_PUPDR_PUPDR11_Msk
3017 #define GPIO_PUPDR_PUPDR11_0            (0x1UL << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00400000 */
3018 #define GPIO_PUPDR_PUPDR11_1            (0x2UL << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00800000 */
3019 #define GPIO_PUPDR_PUPDR12_Pos          (24U)
3020 #define GPIO_PUPDR_PUPDR12_Msk          (0x3UL << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x03000000 */
3021 #define GPIO_PUPDR_PUPDR12              GPIO_PUPDR_PUPDR12_Msk
3022 #define GPIO_PUPDR_PUPDR12_0            (0x1UL << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x01000000 */
3023 #define GPIO_PUPDR_PUPDR12_1            (0x2UL << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x02000000 */
3024 #define GPIO_PUPDR_PUPDR13_Pos          (26U)
3025 #define GPIO_PUPDR_PUPDR13_Msk          (0x3UL << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x0C000000 */
3026 #define GPIO_PUPDR_PUPDR13              GPIO_PUPDR_PUPDR13_Msk
3027 #define GPIO_PUPDR_PUPDR13_0            (0x1UL << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x04000000 */
3028 #define GPIO_PUPDR_PUPDR13_1            (0x2UL << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x08000000 */
3029 #define GPIO_PUPDR_PUPDR14_Pos          (28U)
3030 #define GPIO_PUPDR_PUPDR14_Msk          (0x3UL << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x30000000 */
3031 #define GPIO_PUPDR_PUPDR14              GPIO_PUPDR_PUPDR14_Msk
3032 #define GPIO_PUPDR_PUPDR14_0            (0x1UL << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x10000000 */
3033 #define GPIO_PUPDR_PUPDR14_1            (0x2UL << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x20000000 */
3034 #define GPIO_PUPDR_PUPDR15_Pos          (30U)
3035 #define GPIO_PUPDR_PUPDR15_Msk          (0x3UL << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0xC0000000 */
3036 #define GPIO_PUPDR_PUPDR15              GPIO_PUPDR_PUPDR15_Msk
3037 #define GPIO_PUPDR_PUPDR15_0            (0x1UL << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0x40000000 */
3038 #define GPIO_PUPDR_PUPDR15_1            (0x2UL << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0x80000000 */
3039 
3040 /*******************  Bit definition for GPIO_IDR register  *******************/
3041 #define GPIO_IDR_0                      (0x00000001U)
3042 #define GPIO_IDR_1                      (0x00000002U)
3043 #define GPIO_IDR_2                      (0x00000004U)
3044 #define GPIO_IDR_3                      (0x00000008U)
3045 #define GPIO_IDR_4                      (0x00000010U)
3046 #define GPIO_IDR_5                      (0x00000020U)
3047 #define GPIO_IDR_6                      (0x00000040U)
3048 #define GPIO_IDR_7                      (0x00000080U)
3049 #define GPIO_IDR_8                      (0x00000100U)
3050 #define GPIO_IDR_9                      (0x00000200U)
3051 #define GPIO_IDR_10                     (0x00000400U)
3052 #define GPIO_IDR_11                     (0x00000800U)
3053 #define GPIO_IDR_12                     (0x00001000U)
3054 #define GPIO_IDR_13                     (0x00002000U)
3055 #define GPIO_IDR_14                     (0x00004000U)
3056 #define GPIO_IDR_15                     (0x00008000U)
3057 
3058 /******************  Bit definition for GPIO_ODR register  ********************/
3059 #define GPIO_ODR_0                      (0x00000001U)
3060 #define GPIO_ODR_1                      (0x00000002U)
3061 #define GPIO_ODR_2                      (0x00000004U)
3062 #define GPIO_ODR_3                      (0x00000008U)
3063 #define GPIO_ODR_4                      (0x00000010U)
3064 #define GPIO_ODR_5                      (0x00000020U)
3065 #define GPIO_ODR_6                      (0x00000040U)
3066 #define GPIO_ODR_7                      (0x00000080U)
3067 #define GPIO_ODR_8                      (0x00000100U)
3068 #define GPIO_ODR_9                      (0x00000200U)
3069 #define GPIO_ODR_10                     (0x00000400U)
3070 #define GPIO_ODR_11                     (0x00000800U)
3071 #define GPIO_ODR_12                     (0x00001000U)
3072 #define GPIO_ODR_13                     (0x00002000U)
3073 #define GPIO_ODR_14                     (0x00004000U)
3074 #define GPIO_ODR_15                     (0x00008000U)
3075 
3076 /****************** Bit definition for GPIO_BSRR register  ********************/
3077 #define GPIO_BSRR_BS_0                  (0x00000001U)
3078 #define GPIO_BSRR_BS_1                  (0x00000002U)
3079 #define GPIO_BSRR_BS_2                  (0x00000004U)
3080 #define GPIO_BSRR_BS_3                  (0x00000008U)
3081 #define GPIO_BSRR_BS_4                  (0x00000010U)
3082 #define GPIO_BSRR_BS_5                  (0x00000020U)
3083 #define GPIO_BSRR_BS_6                  (0x00000040U)
3084 #define GPIO_BSRR_BS_7                  (0x00000080U)
3085 #define GPIO_BSRR_BS_8                  (0x00000100U)
3086 #define GPIO_BSRR_BS_9                  (0x00000200U)
3087 #define GPIO_BSRR_BS_10                 (0x00000400U)
3088 #define GPIO_BSRR_BS_11                 (0x00000800U)
3089 #define GPIO_BSRR_BS_12                 (0x00001000U)
3090 #define GPIO_BSRR_BS_13                 (0x00002000U)
3091 #define GPIO_BSRR_BS_14                 (0x00004000U)
3092 #define GPIO_BSRR_BS_15                 (0x00008000U)
3093 #define GPIO_BSRR_BR_0                  (0x00010000U)
3094 #define GPIO_BSRR_BR_1                  (0x00020000U)
3095 #define GPIO_BSRR_BR_2                  (0x00040000U)
3096 #define GPIO_BSRR_BR_3                  (0x00080000U)
3097 #define GPIO_BSRR_BR_4                  (0x00100000U)
3098 #define GPIO_BSRR_BR_5                  (0x00200000U)
3099 #define GPIO_BSRR_BR_6                  (0x00400000U)
3100 #define GPIO_BSRR_BR_7                  (0x00800000U)
3101 #define GPIO_BSRR_BR_8                  (0x01000000U)
3102 #define GPIO_BSRR_BR_9                  (0x02000000U)
3103 #define GPIO_BSRR_BR_10                 (0x04000000U)
3104 #define GPIO_BSRR_BR_11                 (0x08000000U)
3105 #define GPIO_BSRR_BR_12                 (0x10000000U)
3106 #define GPIO_BSRR_BR_13                 (0x20000000U)
3107 #define GPIO_BSRR_BR_14                 (0x40000000U)
3108 #define GPIO_BSRR_BR_15                 (0x80000000U)
3109 
3110 /****************** Bit definition for GPIO_LCKR register  ********************/
3111 #define GPIO_LCKR_LCK0_Pos              (0U)
3112 #define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
3113 #define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk
3114 #define GPIO_LCKR_LCK1_Pos              (1U)
3115 #define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
3116 #define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk
3117 #define GPIO_LCKR_LCK2_Pos              (2U)
3118 #define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
3119 #define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk
3120 #define GPIO_LCKR_LCK3_Pos              (3U)
3121 #define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
3122 #define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk
3123 #define GPIO_LCKR_LCK4_Pos              (4U)
3124 #define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
3125 #define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk
3126 #define GPIO_LCKR_LCK5_Pos              (5U)
3127 #define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
3128 #define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk
3129 #define GPIO_LCKR_LCK6_Pos              (6U)
3130 #define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
3131 #define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk
3132 #define GPIO_LCKR_LCK7_Pos              (7U)
3133 #define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
3134 #define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk
3135 #define GPIO_LCKR_LCK8_Pos              (8U)
3136 #define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
3137 #define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk
3138 #define GPIO_LCKR_LCK9_Pos              (9U)
3139 #define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
3140 #define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk
3141 #define GPIO_LCKR_LCK10_Pos             (10U)
3142 #define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
3143 #define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk
3144 #define GPIO_LCKR_LCK11_Pos             (11U)
3145 #define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
3146 #define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk
3147 #define GPIO_LCKR_LCK12_Pos             (12U)
3148 #define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
3149 #define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk
3150 #define GPIO_LCKR_LCK13_Pos             (13U)
3151 #define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
3152 #define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk
3153 #define GPIO_LCKR_LCK14_Pos             (14U)
3154 #define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
3155 #define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk
3156 #define GPIO_LCKR_LCK15_Pos             (15U)
3157 #define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
3158 #define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk
3159 #define GPIO_LCKR_LCKK_Pos              (16U)
3160 #define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
3161 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk
3162 
3163 /****************** Bit definition for GPIO_AFRL register  ********************/
3164 #define GPIO_AFRL_AFSEL0_Pos            (0U)
3165 #define GPIO_AFRL_AFSEL0_Msk            (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
3166 #define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk
3167 #define GPIO_AFRL_AFSEL1_Pos            (4U)
3168 #define GPIO_AFRL_AFSEL1_Msk            (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
3169 #define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk
3170 #define GPIO_AFRL_AFSEL2_Pos            (8U)
3171 #define GPIO_AFRL_AFSEL2_Msk            (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
3172 #define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk
3173 #define GPIO_AFRL_AFSEL3_Pos            (12U)
3174 #define GPIO_AFRL_AFSEL3_Msk            (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
3175 #define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk
3176 #define GPIO_AFRL_AFSEL4_Pos            (16U)
3177 #define GPIO_AFRL_AFSEL4_Msk            (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
3178 #define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk
3179 #define GPIO_AFRL_AFSEL5_Pos            (20U)
3180 #define GPIO_AFRL_AFSEL5_Msk            (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
3181 #define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk
3182 #define GPIO_AFRL_AFSEL6_Pos            (24U)
3183 #define GPIO_AFRL_AFSEL6_Msk            (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
3184 #define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk
3185 #define GPIO_AFRL_AFSEL7_Pos            (28U)
3186 #define GPIO_AFRL_AFSEL7_Msk            (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
3187 #define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk
3188 
3189 /* Legacy aliases */
3190 #define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos
3191 #define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
3192 #define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
3193 #define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
3194 #define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
3195 #define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
3196 #define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
3197 #define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
3198 #define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
3199 #define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
3200 #define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
3201 #define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
3202 #define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
3203 #define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
3204 #define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
3205 #define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
3206 #define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
3207 #define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
3208 #define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
3209 #define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
3210 #define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
3211 #define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
3212 #define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
3213 #define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
3214 
3215 /****************** Bit definition for GPIO_AFRH register  ********************/
3216 #define GPIO_AFRH_AFSEL8_Pos            (0U)
3217 #define GPIO_AFRH_AFSEL8_Msk            (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
3218 #define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk
3219 #define GPIO_AFRH_AFSEL9_Pos            (4U)
3220 #define GPIO_AFRH_AFSEL9_Msk            (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
3221 #define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk
3222 #define GPIO_AFRH_AFSEL10_Pos           (8U)
3223 #define GPIO_AFRH_AFSEL10_Msk           (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
3224 #define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk
3225 #define GPIO_AFRH_AFSEL11_Pos           (12U)
3226 #define GPIO_AFRH_AFSEL11_Msk           (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
3227 #define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk
3228 #define GPIO_AFRH_AFSEL12_Pos           (16U)
3229 #define GPIO_AFRH_AFSEL12_Msk           (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
3230 #define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk
3231 #define GPIO_AFRH_AFSEL13_Pos           (20U)
3232 #define GPIO_AFRH_AFSEL13_Msk           (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
3233 #define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk
3234 #define GPIO_AFRH_AFSEL14_Pos           (24U)
3235 #define GPIO_AFRH_AFSEL14_Msk           (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
3236 #define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk
3237 #define GPIO_AFRH_AFSEL15_Pos           (28U)
3238 #define GPIO_AFRH_AFSEL15_Msk           (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
3239 #define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk
3240 
3241 /* Legacy aliases */
3242 #define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
3243 #define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
3244 #define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
3245 #define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
3246 #define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
3247 #define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
3248 #define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
3249 #define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
3250 #define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
3251 #define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
3252 #define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
3253 #define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
3254 #define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
3255 #define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
3256 #define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
3257 #define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
3258 #define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
3259 #define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
3260 #define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
3261 #define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
3262 #define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
3263 #define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
3264 #define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
3265 #define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
3266 
3267 /****************** Bit definition for GPIO_BRR register  *********************/
3268 #define GPIO_BRR_BR_0                   (0x00000001U)
3269 #define GPIO_BRR_BR_1                   (0x00000002U)
3270 #define GPIO_BRR_BR_2                   (0x00000004U)
3271 #define GPIO_BRR_BR_3                   (0x00000008U)
3272 #define GPIO_BRR_BR_4                   (0x00000010U)
3273 #define GPIO_BRR_BR_5                   (0x00000020U)
3274 #define GPIO_BRR_BR_6                   (0x00000040U)
3275 #define GPIO_BRR_BR_7                   (0x00000080U)
3276 #define GPIO_BRR_BR_8                   (0x00000100U)
3277 #define GPIO_BRR_BR_9                   (0x00000200U)
3278 #define GPIO_BRR_BR_10                  (0x00000400U)
3279 #define GPIO_BRR_BR_11                  (0x00000800U)
3280 #define GPIO_BRR_BR_12                  (0x00001000U)
3281 #define GPIO_BRR_BR_13                  (0x00002000U)
3282 #define GPIO_BRR_BR_14                  (0x00004000U)
3283 #define GPIO_BRR_BR_15                  (0x00008000U)
3284 
3285 /******************************************************************************/
3286 /*                                                                            */
3287 /*                   Inter-integrated Circuit Interface (I2C)                 */
3288 /*                                                                            */
3289 /******************************************************************************/
3290 
3291 /*******************  Bit definition for I2C_CR1 register  *******************/
3292 #define I2C_CR1_PE_Pos               (0U)
3293 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
3294 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
3295 #define I2C_CR1_TXIE_Pos             (1U)
3296 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
3297 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
3298 #define I2C_CR1_RXIE_Pos             (2U)
3299 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
3300 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
3301 #define I2C_CR1_ADDRIE_Pos           (3U)
3302 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
3303 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
3304 #define I2C_CR1_NACKIE_Pos           (4U)
3305 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
3306 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
3307 #define I2C_CR1_STOPIE_Pos           (5U)
3308 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
3309 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
3310 #define I2C_CR1_TCIE_Pos             (6U)
3311 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
3312 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
3313 #define I2C_CR1_ERRIE_Pos            (7U)
3314 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
3315 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
3316 #define I2C_CR1_DNF_Pos              (8U)
3317 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
3318 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
3319 #define I2C_CR1_ANFOFF_Pos           (12U)
3320 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
3321 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
3322 #define I2C_CR1_SWRST_Pos            (13U)
3323 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
3324 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
3325 #define I2C_CR1_TXDMAEN_Pos          (14U)
3326 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
3327 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
3328 #define I2C_CR1_RXDMAEN_Pos          (15U)
3329 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
3330 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
3331 #define I2C_CR1_SBC_Pos              (16U)
3332 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
3333 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
3334 #define I2C_CR1_NOSTRETCH_Pos        (17U)
3335 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
3336 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
3337 #define I2C_CR1_WUPEN_Pos            (18U)
3338 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
3339 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
3340 #define I2C_CR1_GCEN_Pos             (19U)
3341 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
3342 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
3343 #define I2C_CR1_SMBHEN_Pos           (20U)
3344 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
3345 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
3346 #define I2C_CR1_SMBDEN_Pos           (21U)
3347 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
3348 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
3349 #define I2C_CR1_ALERTEN_Pos          (22U)
3350 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
3351 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
3352 #define I2C_CR1_PECEN_Pos            (23U)
3353 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
3354 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
3355 
3356 /******************  Bit definition for I2C_CR2 register  ********************/
3357 #define I2C_CR2_SADD_Pos             (0U)
3358 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
3359 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
3360 #define I2C_CR2_RD_WRN_Pos           (10U)
3361 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
3362 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
3363 #define I2C_CR2_ADD10_Pos            (11U)
3364 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
3365 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
3366 #define I2C_CR2_HEAD10R_Pos          (12U)
3367 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
3368 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
3369 #define I2C_CR2_START_Pos            (13U)
3370 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
3371 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
3372 #define I2C_CR2_STOP_Pos             (14U)
3373 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
3374 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
3375 #define I2C_CR2_NACK_Pos             (15U)
3376 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
3377 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
3378 #define I2C_CR2_NBYTES_Pos           (16U)
3379 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
3380 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
3381 #define I2C_CR2_RELOAD_Pos           (24U)
3382 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
3383 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
3384 #define I2C_CR2_AUTOEND_Pos          (25U)
3385 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
3386 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
3387 #define I2C_CR2_PECBYTE_Pos          (26U)
3388 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
3389 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
3390 
3391 /*******************  Bit definition for I2C_OAR1 register  ******************/
3392 #define I2C_OAR1_OA1_Pos             (0U)
3393 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
3394 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
3395 #define I2C_OAR1_OA1MODE_Pos         (10U)
3396 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
3397 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
3398 #define I2C_OAR1_OA1EN_Pos           (15U)
3399 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
3400 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
3401 
3402 /*******************  Bit definition for I2C_OAR2 register  ******************/
3403 #define I2C_OAR2_OA2_Pos             (1U)
3404 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
3405 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
3406 #define I2C_OAR2_OA2MSK_Pos          (8U)
3407 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
3408 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
3409 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
3410 #define I2C_OAR2_OA2MASK01_Pos       (8U)
3411 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
3412 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
3413 #define I2C_OAR2_OA2MASK02_Pos       (9U)
3414 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
3415 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3416 #define I2C_OAR2_OA2MASK03_Pos       (8U)
3417 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
3418 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3419 #define I2C_OAR2_OA2MASK04_Pos       (10U)
3420 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
3421 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3422 #define I2C_OAR2_OA2MASK05_Pos       (8U)
3423 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
3424 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3425 #define I2C_OAR2_OA2MASK06_Pos       (9U)
3426 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
3427 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
3428 #define I2C_OAR2_OA2MASK07_Pos       (8U)
3429 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
3430 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
3431 #define I2C_OAR2_OA2EN_Pos           (15U)
3432 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
3433 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
3434 
3435 /*******************  Bit definition for I2C_TIMINGR register ****************/
3436 #define I2C_TIMINGR_SCLL_Pos         (0U)
3437 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
3438 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
3439 #define I2C_TIMINGR_SCLH_Pos         (8U)
3440 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
3441 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
3442 #define I2C_TIMINGR_SDADEL_Pos       (16U)
3443 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
3444 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
3445 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
3446 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
3447 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
3448 #define I2C_TIMINGR_PRESC_Pos        (28U)
3449 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
3450 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
3451 
3452 /******************* Bit definition for I2C_TIMEOUTR register ****************/
3453 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
3454 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
3455 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
3456 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
3457 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
3458 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
3459 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
3460 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
3461 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
3462 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
3463 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
3464 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
3465 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
3466 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
3467 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
3468 
3469 /******************  Bit definition for I2C_ISR register  ********************/
3470 #define I2C_ISR_TXE_Pos              (0U)
3471 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
3472 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
3473 #define I2C_ISR_TXIS_Pos             (1U)
3474 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
3475 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
3476 #define I2C_ISR_RXNE_Pos             (2U)
3477 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
3478 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
3479 #define I2C_ISR_ADDR_Pos             (3U)
3480 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
3481 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
3482 #define I2C_ISR_NACKF_Pos            (4U)
3483 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
3484 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
3485 #define I2C_ISR_STOPF_Pos            (5U)
3486 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
3487 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
3488 #define I2C_ISR_TC_Pos               (6U)
3489 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
3490 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
3491 #define I2C_ISR_TCR_Pos              (7U)
3492 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
3493 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
3494 #define I2C_ISR_BERR_Pos             (8U)
3495 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
3496 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
3497 #define I2C_ISR_ARLO_Pos             (9U)
3498 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
3499 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
3500 #define I2C_ISR_OVR_Pos              (10U)
3501 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
3502 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
3503 #define I2C_ISR_PECERR_Pos           (11U)
3504 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
3505 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
3506 #define I2C_ISR_TIMEOUT_Pos          (12U)
3507 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
3508 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
3509 #define I2C_ISR_ALERT_Pos            (13U)
3510 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
3511 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
3512 #define I2C_ISR_BUSY_Pos             (15U)
3513 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
3514 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
3515 #define I2C_ISR_DIR_Pos              (16U)
3516 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
3517 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
3518 #define I2C_ISR_ADDCODE_Pos          (17U)
3519 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
3520 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
3521 
3522 /******************  Bit definition for I2C_ICR register  ********************/
3523 #define I2C_ICR_ADDRCF_Pos           (3U)
3524 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
3525 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
3526 #define I2C_ICR_NACKCF_Pos           (4U)
3527 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
3528 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
3529 #define I2C_ICR_STOPCF_Pos           (5U)
3530 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
3531 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
3532 #define I2C_ICR_BERRCF_Pos           (8U)
3533 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
3534 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
3535 #define I2C_ICR_ARLOCF_Pos           (9U)
3536 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
3537 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
3538 #define I2C_ICR_OVRCF_Pos            (10U)
3539 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
3540 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
3541 #define I2C_ICR_PECCF_Pos            (11U)
3542 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
3543 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
3544 #define I2C_ICR_TIMOUTCF_Pos         (12U)
3545 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
3546 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
3547 #define I2C_ICR_ALERTCF_Pos          (13U)
3548 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
3549 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
3550 
3551 /******************  Bit definition for I2C_PECR register  *******************/
3552 #define I2C_PECR_PEC_Pos             (0U)
3553 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
3554 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
3555 
3556 /******************  Bit definition for I2C_RXDR register  *********************/
3557 #define I2C_RXDR_RXDATA_Pos          (0U)
3558 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
3559 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
3560 
3561 /******************  Bit definition for I2C_TXDR register  *******************/
3562 #define I2C_TXDR_TXDATA_Pos          (0U)
3563 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
3564 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
3565 
3566 /*****************************************************************************/
3567 /*                                                                           */
3568 /*                        Independent WATCHDOG (IWDG)                        */
3569 /*                                                                           */
3570 /*****************************************************************************/
3571 /*******************  Bit definition for IWDG_KR register  *******************/
3572 #define IWDG_KR_KEY_Pos      (0U)
3573 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
3574 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
3575 
3576 /*******************  Bit definition for IWDG_PR register  *******************/
3577 #define IWDG_PR_PR_Pos       (0U)
3578 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
3579 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
3580 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x01 */
3581 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x02 */
3582 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x04 */
3583 
3584 /*******************  Bit definition for IWDG_RLR register  ******************/
3585 #define IWDG_RLR_RL_Pos      (0U)
3586 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
3587 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
3588 
3589 /*******************  Bit definition for IWDG_SR register  *******************/
3590 #define IWDG_SR_PVU_Pos      (0U)
3591 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
3592 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
3593 #define IWDG_SR_RVU_Pos      (1U)
3594 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
3595 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
3596 #define IWDG_SR_WVU_Pos      (2U)
3597 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
3598 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
3599 
3600 /*******************  Bit definition for IWDG_KR register  *******************/
3601 #define IWDG_WINR_WIN_Pos    (0U)
3602 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
3603 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
3604 
3605 /*****************************************************************************/
3606 /*                                                                           */
3607 /*                          Power Control (PWR)                              */
3608 /*                                                                           */
3609 /*****************************************************************************/
3610 
3611 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
3612 
3613 
3614 /********************  Bit definition for PWR_CR register  *******************/
3615 #define PWR_CR_LPDS_Pos            (0U)
3616 #define PWR_CR_LPDS_Msk            (0x1UL << PWR_CR_LPDS_Pos)                   /*!< 0x00000001 */
3617 #define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< Low-power Deepsleep */
3618 #define PWR_CR_PDDS_Pos            (1U)
3619 #define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
3620 #define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
3621 #define PWR_CR_CWUF_Pos            (2U)
3622 #define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
3623 #define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
3624 #define PWR_CR_CSBF_Pos            (3U)
3625 #define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
3626 #define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
3627 #define PWR_CR_PVDE_Pos            (4U)
3628 #define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
3629 #define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
3630 
3631 #define PWR_CR_PLS_Pos             (5U)
3632 #define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
3633 #define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
3634 #define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
3635 #define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
3636 #define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
3637 
3638 /*!< PVD level configuration */
3639 #define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
3640 #define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
3641 #define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
3642 #define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
3643 #define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
3644 #define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
3645 #define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
3646 #define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
3647 
3648 #define PWR_CR_DBP_Pos             (8U)
3649 #define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
3650 #define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
3651 
3652 /*******************  Bit definition for PWR_CSR register  *******************/
3653 #define PWR_CSR_WUF_Pos            (0U)
3654 #define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
3655 #define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
3656 #define PWR_CSR_SBF_Pos            (1U)
3657 #define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
3658 #define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
3659 #define PWR_CSR_PVDO_Pos           (2U)
3660 #define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
3661 #define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
3662 #define PWR_CSR_VREFINTRDYF_Pos    (3U)
3663 #define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
3664 #define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
3665 
3666 #define PWR_CSR_EWUP1_Pos          (8U)
3667 #define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
3668 #define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
3669 #define PWR_CSR_EWUP2_Pos          (9U)
3670 #define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
3671 #define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
3672 #define PWR_CSR_EWUP3_Pos          (10U)
3673 #define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
3674 #define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
3675 #define PWR_CSR_EWUP4_Pos          (11U)
3676 #define PWR_CSR_EWUP4_Msk          (0x1UL << PWR_CSR_EWUP4_Pos)                 /*!< 0x00000800 */
3677 #define PWR_CSR_EWUP4              PWR_CSR_EWUP4_Msk                           /*!< Enable WKUP pin 4 */
3678 #define PWR_CSR_EWUP5_Pos          (12U)
3679 #define PWR_CSR_EWUP5_Msk          (0x1UL << PWR_CSR_EWUP5_Pos)                 /*!< 0x00001000 */
3680 #define PWR_CSR_EWUP5              PWR_CSR_EWUP5_Msk                           /*!< Enable WKUP pin 5 */
3681 #define PWR_CSR_EWUP6_Pos          (13U)
3682 #define PWR_CSR_EWUP6_Msk          (0x1UL << PWR_CSR_EWUP6_Pos)                 /*!< 0x00002000 */
3683 #define PWR_CSR_EWUP6              PWR_CSR_EWUP6_Msk                           /*!< Enable WKUP pin 6 */
3684 #define PWR_CSR_EWUP7_Pos          (14U)
3685 #define PWR_CSR_EWUP7_Msk          (0x1UL << PWR_CSR_EWUP7_Pos)                 /*!< 0x00004000 */
3686 #define PWR_CSR_EWUP7              PWR_CSR_EWUP7_Msk                           /*!< Enable WKUP pin 7 */
3687 #define PWR_CSR_EWUP8_Pos          (15U)
3688 #define PWR_CSR_EWUP8_Msk          (0x1UL << PWR_CSR_EWUP8_Pos)                 /*!< 0x00008000 */
3689 #define PWR_CSR_EWUP8              PWR_CSR_EWUP8_Msk                           /*!< Enable WKUP pin 8 */
3690 
3691 /*****************************************************************************/
3692 /*                                                                           */
3693 /*                         Reset and Clock Control                           */
3694 /*                                                                           */
3695 /*****************************************************************************/
3696 /*
3697 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 series)
3698 */
3699 #define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
3700 #define RCC_PLLSRC_PREDIV1_SUPPORT  /*!< PREDIV support used as PLL source input  */
3701 
3702 /********************  Bit definition for RCC_CR register  *******************/
3703 #define RCC_CR_HSION_Pos                         (0U)
3704 #define RCC_CR_HSION_Msk                         (0x1UL << RCC_CR_HSION_Pos)    /*!< 0x00000001 */
3705 #define RCC_CR_HSION                             RCC_CR_HSION_Msk              /*!< Internal High Speed clock enable */
3706 #define RCC_CR_HSIRDY_Pos                        (1U)
3707 #define RCC_CR_HSIRDY_Msk                        (0x1UL << RCC_CR_HSIRDY_Pos)   /*!< 0x00000002 */
3708 #define RCC_CR_HSIRDY                            RCC_CR_HSIRDY_Msk             /*!< Internal High Speed clock ready flag */
3709 
3710 #define RCC_CR_HSITRIM_Pos                       (3U)
3711 #define RCC_CR_HSITRIM_Msk                       (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
3712 #define RCC_CR_HSITRIM                           RCC_CR_HSITRIM_Msk            /*!< Internal High Speed clock trimming */
3713 #define RCC_CR_HSITRIM_0                         (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
3714 #define RCC_CR_HSITRIM_1                         (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
3715 #define RCC_CR_HSITRIM_2                         (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
3716 #define RCC_CR_HSITRIM_3                         (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
3717 #define RCC_CR_HSITRIM_4                         (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
3718 
3719 #define RCC_CR_HSICAL_Pos                        (8U)
3720 #define RCC_CR_HSICAL_Msk                        (0xFFUL << RCC_CR_HSICAL_Pos)  /*!< 0x0000FF00 */
3721 #define RCC_CR_HSICAL                            RCC_CR_HSICAL_Msk             /*!< Internal High Speed clock Calibration */
3722 #define RCC_CR_HSICAL_0                          (0x01UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000100 */
3723 #define RCC_CR_HSICAL_1                          (0x02UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000200 */
3724 #define RCC_CR_HSICAL_2                          (0x04UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000400 */
3725 #define RCC_CR_HSICAL_3                          (0x08UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000800 */
3726 #define RCC_CR_HSICAL_4                          (0x10UL << RCC_CR_HSICAL_Pos)  /*!< 0x00001000 */
3727 #define RCC_CR_HSICAL_5                          (0x20UL << RCC_CR_HSICAL_Pos)  /*!< 0x00002000 */
3728 #define RCC_CR_HSICAL_6                          (0x40UL << RCC_CR_HSICAL_Pos)  /*!< 0x00004000 */
3729 #define RCC_CR_HSICAL_7                          (0x80UL << RCC_CR_HSICAL_Pos)  /*!< 0x00008000 */
3730 
3731 #define RCC_CR_HSEON_Pos                         (16U)
3732 #define RCC_CR_HSEON_Msk                         (0x1UL << RCC_CR_HSEON_Pos)    /*!< 0x00010000 */
3733 #define RCC_CR_HSEON                             RCC_CR_HSEON_Msk              /*!< External High Speed clock enable */
3734 #define RCC_CR_HSERDY_Pos                        (17U)
3735 #define RCC_CR_HSERDY_Msk                        (0x1UL << RCC_CR_HSERDY_Pos)   /*!< 0x00020000 */
3736 #define RCC_CR_HSERDY                            RCC_CR_HSERDY_Msk             /*!< External High Speed clock ready flag */
3737 #define RCC_CR_HSEBYP_Pos                        (18U)
3738 #define RCC_CR_HSEBYP_Msk                        (0x1UL << RCC_CR_HSEBYP_Pos)   /*!< 0x00040000 */
3739 #define RCC_CR_HSEBYP                            RCC_CR_HSEBYP_Msk             /*!< External High Speed clock Bypass */
3740 #define RCC_CR_CSSON_Pos                         (19U)
3741 #define RCC_CR_CSSON_Msk                         (0x1UL << RCC_CR_CSSON_Pos)    /*!< 0x00080000 */
3742 #define RCC_CR_CSSON                             RCC_CR_CSSON_Msk              /*!< Clock Security System enable */
3743 #define RCC_CR_PLLON_Pos                         (24U)
3744 #define RCC_CR_PLLON_Msk                         (0x1UL << RCC_CR_PLLON_Pos)    /*!< 0x01000000 */
3745 #define RCC_CR_PLLON                             RCC_CR_PLLON_Msk              /*!< PLL enable */
3746 #define RCC_CR_PLLRDY_Pos                        (25U)
3747 #define RCC_CR_PLLRDY_Msk                        (0x1UL << RCC_CR_PLLRDY_Pos)   /*!< 0x02000000 */
3748 #define RCC_CR_PLLRDY                            RCC_CR_PLLRDY_Msk             /*!< PLL clock ready flag */
3749 
3750 /********************  Bit definition for RCC_CFGR register  *****************/
3751 /*!< SW configuration */
3752 #define RCC_CFGR_SW_Pos                          (0U)
3753 #define RCC_CFGR_SW_Msk                          (0x3UL << RCC_CFGR_SW_Pos)     /*!< 0x00000003 */
3754 #define RCC_CFGR_SW                              RCC_CFGR_SW_Msk               /*!< SW[1:0] bits (System clock Switch) */
3755 #define RCC_CFGR_SW_0                            (0x1UL << RCC_CFGR_SW_Pos)     /*!< 0x00000001 */
3756 #define RCC_CFGR_SW_1                            (0x2UL << RCC_CFGR_SW_Pos)     /*!< 0x00000002 */
3757 
3758 #define RCC_CFGR_SW_HSI                          (0x00000000U)                 /*!< HSI selected as system clock */
3759 #define RCC_CFGR_SW_HSE                          (0x00000001U)                 /*!< HSE selected as system clock */
3760 #define RCC_CFGR_SW_PLL                          (0x00000002U)                 /*!< PLL selected as system clock */
3761 #define RCC_CFGR_SW_HSI48                        (0x00000003U)                 /*!< HSI48 selected as system clock */
3762 
3763 /*!< SWS configuration */
3764 #define RCC_CFGR_SWS_Pos                         (2U)
3765 #define RCC_CFGR_SWS_Msk                         (0x3UL << RCC_CFGR_SWS_Pos)    /*!< 0x0000000C */
3766 #define RCC_CFGR_SWS                             RCC_CFGR_SWS_Msk              /*!< SWS[1:0] bits (System Clock Switch Status) */
3767 #define RCC_CFGR_SWS_0                           (0x1UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000004 */
3768 #define RCC_CFGR_SWS_1                           (0x2UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000008 */
3769 
3770 #define RCC_CFGR_SWS_HSI                         (0x00000000U)                 /*!< HSI oscillator used as system clock */
3771 #define RCC_CFGR_SWS_HSE                         (0x00000004U)                 /*!< HSE oscillator used as system clock */
3772 #define RCC_CFGR_SWS_PLL                         (0x00000008U)                 /*!< PLL used as system clock */
3773 #define RCC_CFGR_SWS_HSI48                       (0x0000000CU)                 /*!< HSI48 oscillator used as system clock */
3774 
3775 /*!< HPRE configuration */
3776 #define RCC_CFGR_HPRE_Pos                        (4U)
3777 #define RCC_CFGR_HPRE_Msk                        (0xFUL << RCC_CFGR_HPRE_Pos)   /*!< 0x000000F0 */
3778 #define RCC_CFGR_HPRE                            RCC_CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB prescaler) */
3779 #define RCC_CFGR_HPRE_0                          (0x1UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000010 */
3780 #define RCC_CFGR_HPRE_1                          (0x2UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000020 */
3781 #define RCC_CFGR_HPRE_2                          (0x4UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000040 */
3782 #define RCC_CFGR_HPRE_3                          (0x8UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000080 */
3783 
3784 #define RCC_CFGR_HPRE_DIV1                       (0x00000000U)                 /*!< SYSCLK not divided */
3785 #define RCC_CFGR_HPRE_DIV2                       (0x00000080U)                 /*!< SYSCLK divided by 2 */
3786 #define RCC_CFGR_HPRE_DIV4                       (0x00000090U)                 /*!< SYSCLK divided by 4 */
3787 #define RCC_CFGR_HPRE_DIV8                       (0x000000A0U)                 /*!< SYSCLK divided by 8 */
3788 #define RCC_CFGR_HPRE_DIV16                      (0x000000B0U)                 /*!< SYSCLK divided by 16 */
3789 #define RCC_CFGR_HPRE_DIV64                      (0x000000C0U)                 /*!< SYSCLK divided by 64 */
3790 #define RCC_CFGR_HPRE_DIV128                     (0x000000D0U)                 /*!< SYSCLK divided by 128 */
3791 #define RCC_CFGR_HPRE_DIV256                     (0x000000E0U)                 /*!< SYSCLK divided by 256 */
3792 #define RCC_CFGR_HPRE_DIV512                     (0x000000F0U)                 /*!< SYSCLK divided by 512 */
3793 
3794 /*!< PPRE configuration */
3795 #define RCC_CFGR_PPRE_Pos                        (8U)
3796 #define RCC_CFGR_PPRE_Msk                        (0x7UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000700 */
3797 #define RCC_CFGR_PPRE                            RCC_CFGR_PPRE_Msk             /*!< PRE[2:0] bits (APB prescaler) */
3798 #define RCC_CFGR_PPRE_0                          (0x1UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000100 */
3799 #define RCC_CFGR_PPRE_1                          (0x2UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000200 */
3800 #define RCC_CFGR_PPRE_2                          (0x4UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000400 */
3801 
3802 #define RCC_CFGR_PPRE_DIV1                       (0x00000000U)                 /*!< HCLK not divided */
3803 #define RCC_CFGR_PPRE_DIV2_Pos                   (10U)
3804 #define RCC_CFGR_PPRE_DIV2_Msk                   (0x1UL << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
3805 #define RCC_CFGR_PPRE_DIV2                       RCC_CFGR_PPRE_DIV2_Msk        /*!< HCLK divided by 2 */
3806 #define RCC_CFGR_PPRE_DIV4_Pos                   (8U)
3807 #define RCC_CFGR_PPRE_DIV4_Msk                   (0x5UL << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
3808 #define RCC_CFGR_PPRE_DIV4                       RCC_CFGR_PPRE_DIV4_Msk        /*!< HCLK divided by 4 */
3809 #define RCC_CFGR_PPRE_DIV8_Pos                   (9U)
3810 #define RCC_CFGR_PPRE_DIV8_Msk                   (0x3UL << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
3811 #define RCC_CFGR_PPRE_DIV8                       RCC_CFGR_PPRE_DIV8_Msk        /*!< HCLK divided by 8 */
3812 #define RCC_CFGR_PPRE_DIV16_Pos                  (8U)
3813 #define RCC_CFGR_PPRE_DIV16_Msk                  (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
3814 #define RCC_CFGR_PPRE_DIV16                      RCC_CFGR_PPRE_DIV16_Msk       /*!< HCLK divided by 16 */
3815 
3816 /*!< ADCPPRE configuration */
3817 #define RCC_CFGR_ADCPRE_Pos                      (14U)
3818 #define RCC_CFGR_ADCPRE_Msk                      (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
3819 #define RCC_CFGR_ADCPRE                          RCC_CFGR_ADCPRE_Msk           /*!< ADCPRE bit (ADC prescaler) */
3820 
3821 #define RCC_CFGR_ADCPRE_DIV2                     (0x00000000U)                 /*!< PCLK divided by 2 */
3822 #define RCC_CFGR_ADCPRE_DIV4                     (0x00004000U)                 /*!< PCLK divided by 4 */
3823 
3824 #define RCC_CFGR_PLLSRC_Pos                      (15U)
3825 #define RCC_CFGR_PLLSRC_Msk                      (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
3826 #define RCC_CFGR_PLLSRC                          RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */
3827 #define RCC_CFGR_PLLSRC_HSI_DIV2                 (0x00000000U)                 /*!< HSI clock divided by 2 selected as PLL entry clock source */
3828 #define RCC_CFGR_PLLSRC_HSI_PREDIV               (0x00008000U)                 /*!< HSI/PREDIV clock selected as PLL entry clock source */
3829 #define RCC_CFGR_PLLSRC_HSE_PREDIV               (0x00010000U)                 /*!< HSE/PREDIV clock selected as PLL entry clock source */
3830 #define RCC_CFGR_PLLSRC_HSI48_PREDIV             (0x00018000U)                 /*!< HSI48/PREDIV clock selected as PLL entry clock source */
3831 
3832 #define RCC_CFGR_PLLXTPRE_Pos                    (17U)
3833 #define RCC_CFGR_PLLXTPRE_Msk                    (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
3834 #define RCC_CFGR_PLLXTPRE                        RCC_CFGR_PLLXTPRE_Msk         /*!< HSE divider for PLL entry */
3835 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1        (0x00000000U)                 /*!< HSE/PREDIV clock not divided for PLL entry */
3836 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2        (0x00020000U)                 /*!< HSE/PREDIV clock divided by 2 for PLL entry */
3837 
3838 /*!< PLLMUL configuration */
3839 #define RCC_CFGR_PLLMUL_Pos                      (18U)
3840 #define RCC_CFGR_PLLMUL_Msk                      (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
3841 #define RCC_CFGR_PLLMUL                          RCC_CFGR_PLLMUL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
3842 #define RCC_CFGR_PLLMUL_0                        (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
3843 #define RCC_CFGR_PLLMUL_1                        (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
3844 #define RCC_CFGR_PLLMUL_2                        (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
3845 #define RCC_CFGR_PLLMUL_3                        (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
3846 
3847 #define RCC_CFGR_PLLMUL2                         (0x00000000U)                 /*!< PLL input clock*2 */
3848 #define RCC_CFGR_PLLMUL3                         (0x00040000U)                 /*!< PLL input clock*3 */
3849 #define RCC_CFGR_PLLMUL4                         (0x00080000U)                 /*!< PLL input clock*4 */
3850 #define RCC_CFGR_PLLMUL5                         (0x000C0000U)                 /*!< PLL input clock*5 */
3851 #define RCC_CFGR_PLLMUL6                         (0x00100000U)                 /*!< PLL input clock*6 */
3852 #define RCC_CFGR_PLLMUL7                         (0x00140000U)                 /*!< PLL input clock*7 */
3853 #define RCC_CFGR_PLLMUL8                         (0x00180000U)                 /*!< PLL input clock*8 */
3854 #define RCC_CFGR_PLLMUL9                         (0x001C0000U)                 /*!< PLL input clock*9 */
3855 #define RCC_CFGR_PLLMUL10                        (0x00200000U)                 /*!< PLL input clock10 */
3856 #define RCC_CFGR_PLLMUL11                        (0x00240000U)                 /*!< PLL input clock*11 */
3857 #define RCC_CFGR_PLLMUL12                        (0x00280000U)                 /*!< PLL input clock*12 */
3858 #define RCC_CFGR_PLLMUL13                        (0x002C0000U)                 /*!< PLL input clock*13 */
3859 #define RCC_CFGR_PLLMUL14                        (0x00300000U)                 /*!< PLL input clock*14 */
3860 #define RCC_CFGR_PLLMUL15                        (0x00340000U)                 /*!< PLL input clock*15 */
3861 #define RCC_CFGR_PLLMUL16                        (0x00380000U)                 /*!< PLL input clock*16 */
3862 
3863 /*!< MCO configuration */
3864 #define RCC_CFGR_MCO_Pos                         (24U)
3865 #define RCC_CFGR_MCO_Msk                         (0xFUL << RCC_CFGR_MCO_Pos)    /*!< 0x0F000000 */
3866 #define RCC_CFGR_MCO                             RCC_CFGR_MCO_Msk              /*!< MCO[3:0] bits (Microcontroller Clock Output) */
3867 #define RCC_CFGR_MCO_0                           (0x1UL << RCC_CFGR_MCO_Pos)    /*!< 0x01000000 */
3868 #define RCC_CFGR_MCO_1                           (0x2UL << RCC_CFGR_MCO_Pos)    /*!< 0x02000000 */
3869 #define RCC_CFGR_MCO_2                           (0x4UL << RCC_CFGR_MCO_Pos)    /*!< 0x04000000 */
3870 #define RCC_CFGR_MCO_3                           (0x08000000U)                 /*!< Bit 3 */
3871 
3872 #define RCC_CFGR_MCO_NOCLOCK                     (0x00000000U)                 /*!< No clock */
3873 #define RCC_CFGR_MCO_HSI14                       (0x01000000U)                 /*!< HSI14 clock selected as MCO source */
3874 #define RCC_CFGR_MCO_LSI                         (0x02000000U)                 /*!< LSI clock selected as MCO source */
3875 #define RCC_CFGR_MCO_LSE                         (0x03000000U)                 /*!< LSE clock selected as MCO source */
3876 #define RCC_CFGR_MCO_SYSCLK                      (0x04000000U)                 /*!< System clock selected as MCO source */
3877 #define RCC_CFGR_MCO_HSI                         (0x05000000U)                 /*!< HSI clock selected as MCO source */
3878 #define RCC_CFGR_MCO_HSE                         (0x06000000U)                 /*!< HSE clock selected as MCO source  */
3879 #define RCC_CFGR_MCO_PLL                         (0x07000000U)                 /*!< PLL clock divided by 2 selected as MCO source */
3880 #define RCC_CFGR_MCO_HSI48                       (0x08000000U)                 /*!< HSI48 clock selected as MCO source */
3881 
3882 #define RCC_CFGR_MCOPRE_Pos                      (28U)
3883 #define RCC_CFGR_MCOPRE_Msk                      (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
3884 #define RCC_CFGR_MCOPRE                          RCC_CFGR_MCOPRE_Msk           /*!< MCO prescaler  */
3885 #define RCC_CFGR_MCOPRE_DIV1                     (0x00000000U)                 /*!< MCO is divided by 1  */
3886 #define RCC_CFGR_MCOPRE_DIV2                     (0x10000000U)                 /*!< MCO is divided by 2  */
3887 #define RCC_CFGR_MCOPRE_DIV4                     (0x20000000U)                 /*!< MCO is divided by 4  */
3888 #define RCC_CFGR_MCOPRE_DIV8                     (0x30000000U)                 /*!< MCO is divided by 8  */
3889 #define RCC_CFGR_MCOPRE_DIV16                    (0x40000000U)                 /*!< MCO is divided by 16  */
3890 #define RCC_CFGR_MCOPRE_DIV32                    (0x50000000U)                 /*!< MCO is divided by 32  */
3891 #define RCC_CFGR_MCOPRE_DIV64                    (0x60000000U)                 /*!< MCO is divided by 64  */
3892 #define RCC_CFGR_MCOPRE_DIV128                   (0x70000000U)                 /*!< MCO is divided by 128  */
3893 
3894 #define RCC_CFGR_PLLNODIV_Pos                    (31U)
3895 #define RCC_CFGR_PLLNODIV_Msk                    (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
3896 #define RCC_CFGR_PLLNODIV                        RCC_CFGR_PLLNODIV_Msk         /*!< PLL is not divided to MCO  */
3897 
3898 /* Reference defines */
3899 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
3900 #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
3901 #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
3902 #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
3903 #define RCC_CFGR_MCOSEL_3                    RCC_CFGR_MCO_3
3904 #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
3905 #define RCC_CFGR_MCOSEL_HSI14                RCC_CFGR_MCO_HSI14
3906 #define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCO_LSI
3907 #define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCO_LSE
3908 #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
3909 #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
3910 #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
3911 #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLL
3912 #define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCO_HSI48
3913 
3914 /*!<******************  Bit definition for RCC_CIR register  *****************/
3915 #define RCC_CIR_LSIRDYF_Pos                      (0U)
3916 #define RCC_CIR_LSIRDYF_Msk                      (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
3917 #define RCC_CIR_LSIRDYF                          RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
3918 #define RCC_CIR_LSERDYF_Pos                      (1U)
3919 #define RCC_CIR_LSERDYF_Msk                      (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
3920 #define RCC_CIR_LSERDYF                          RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
3921 #define RCC_CIR_HSIRDYF_Pos                      (2U)
3922 #define RCC_CIR_HSIRDYF_Msk                      (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
3923 #define RCC_CIR_HSIRDYF                          RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
3924 #define RCC_CIR_HSERDYF_Pos                      (3U)
3925 #define RCC_CIR_HSERDYF_Msk                      (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
3926 #define RCC_CIR_HSERDYF                          RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
3927 #define RCC_CIR_PLLRDYF_Pos                      (4U)
3928 #define RCC_CIR_PLLRDYF_Msk                      (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
3929 #define RCC_CIR_PLLRDYF                          RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
3930 #define RCC_CIR_HSI14RDYF_Pos                    (5U)
3931 #define RCC_CIR_HSI14RDYF_Msk                    (0x1UL << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
3932 #define RCC_CIR_HSI14RDYF                        RCC_CIR_HSI14RDYF_Msk         /*!< HSI14 Ready Interrupt flag */
3933 #define RCC_CIR_HSI48RDYF_Pos                    (6U)
3934 #define RCC_CIR_HSI48RDYF_Msk                    (0x1UL << RCC_CIR_HSI48RDYF_Pos) /*!< 0x00000040 */
3935 #define RCC_CIR_HSI48RDYF                        RCC_CIR_HSI48RDYF_Msk         /*!< HSI48 Ready Interrupt flag */
3936 #define RCC_CIR_CSSF_Pos                         (7U)
3937 #define RCC_CIR_CSSF_Msk                         (0x1UL << RCC_CIR_CSSF_Pos)    /*!< 0x00000080 */
3938 #define RCC_CIR_CSSF                             RCC_CIR_CSSF_Msk              /*!< Clock Security System Interrupt flag */
3939 #define RCC_CIR_LSIRDYIE_Pos                     (8U)
3940 #define RCC_CIR_LSIRDYIE_Msk                     (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
3941 #define RCC_CIR_LSIRDYIE                         RCC_CIR_LSIRDYIE_Msk          /*!< LSI Ready Interrupt Enable */
3942 #define RCC_CIR_LSERDYIE_Pos                     (9U)
3943 #define RCC_CIR_LSERDYIE_Msk                     (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
3944 #define RCC_CIR_LSERDYIE                         RCC_CIR_LSERDYIE_Msk          /*!< LSE Ready Interrupt Enable */
3945 #define RCC_CIR_HSIRDYIE_Pos                     (10U)
3946 #define RCC_CIR_HSIRDYIE_Msk                     (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
3947 #define RCC_CIR_HSIRDYIE                         RCC_CIR_HSIRDYIE_Msk          /*!< HSI Ready Interrupt Enable */
3948 #define RCC_CIR_HSERDYIE_Pos                     (11U)
3949 #define RCC_CIR_HSERDYIE_Msk                     (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
3950 #define RCC_CIR_HSERDYIE                         RCC_CIR_HSERDYIE_Msk          /*!< HSE Ready Interrupt Enable */
3951 #define RCC_CIR_PLLRDYIE_Pos                     (12U)
3952 #define RCC_CIR_PLLRDYIE_Msk                     (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
3953 #define RCC_CIR_PLLRDYIE                         RCC_CIR_PLLRDYIE_Msk          /*!< PLL Ready Interrupt Enable */
3954 #define RCC_CIR_HSI14RDYIE_Pos                   (13U)
3955 #define RCC_CIR_HSI14RDYIE_Msk                   (0x1UL << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
3956 #define RCC_CIR_HSI14RDYIE                       RCC_CIR_HSI14RDYIE_Msk        /*!< HSI14 Ready Interrupt Enable */
3957 #define RCC_CIR_HSI48RDYIE_Pos                   (14U)
3958 #define RCC_CIR_HSI48RDYIE_Msk                   (0x1UL << RCC_CIR_HSI48RDYIE_Pos) /*!< 0x00004000 */
3959 #define RCC_CIR_HSI48RDYIE                       RCC_CIR_HSI48RDYIE_Msk        /*!< HSI48 Ready Interrupt Enable */
3960 #define RCC_CIR_LSIRDYC_Pos                      (16U)
3961 #define RCC_CIR_LSIRDYC_Msk                      (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
3962 #define RCC_CIR_LSIRDYC                          RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
3963 #define RCC_CIR_LSERDYC_Pos                      (17U)
3964 #define RCC_CIR_LSERDYC_Msk                      (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
3965 #define RCC_CIR_LSERDYC                          RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
3966 #define RCC_CIR_HSIRDYC_Pos                      (18U)
3967 #define RCC_CIR_HSIRDYC_Msk                      (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
3968 #define RCC_CIR_HSIRDYC                          RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
3969 #define RCC_CIR_HSERDYC_Pos                      (19U)
3970 #define RCC_CIR_HSERDYC_Msk                      (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
3971 #define RCC_CIR_HSERDYC                          RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
3972 #define RCC_CIR_PLLRDYC_Pos                      (20U)
3973 #define RCC_CIR_PLLRDYC_Msk                      (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
3974 #define RCC_CIR_PLLRDYC                          RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
3975 #define RCC_CIR_HSI14RDYC_Pos                    (21U)
3976 #define RCC_CIR_HSI14RDYC_Msk                    (0x1UL << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
3977 #define RCC_CIR_HSI14RDYC                        RCC_CIR_HSI14RDYC_Msk         /*!< HSI14 Ready Interrupt Clear */
3978 #define RCC_CIR_HSI48RDYC_Pos                    (22U)
3979 #define RCC_CIR_HSI48RDYC_Msk                    (0x1UL << RCC_CIR_HSI48RDYC_Pos) /*!< 0x00400000 */
3980 #define RCC_CIR_HSI48RDYC                        RCC_CIR_HSI48RDYC_Msk         /*!< HSI48 Ready Interrupt Clear */
3981 #define RCC_CIR_CSSC_Pos                         (23U)
3982 #define RCC_CIR_CSSC_Msk                         (0x1UL << RCC_CIR_CSSC_Pos)    /*!< 0x00800000 */
3983 #define RCC_CIR_CSSC                             RCC_CIR_CSSC_Msk              /*!< Clock Security System Interrupt Clear */
3984 
3985 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
3986 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)
3987 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
3988 #define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
3989 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)
3990 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
3991 #define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
3992 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)
3993 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
3994 #define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
3995 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)
3996 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
3997 #define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
3998 #define RCC_APB2RSTR_USART1RST_Pos               (14U)
3999 #define RCC_APB2RSTR_USART1RST_Msk               (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
4000 #define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
4001 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)
4002 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
4003 #define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
4004 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)
4005 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
4006 #define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
4007 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)
4008 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
4009 #define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
4010 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)
4011 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
4012 #define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
4013 
4014 /*!< Old ADC1 reset bit definition maintained for legacy purpose */
4015 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
4016 
4017 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
4018 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)
4019 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
4020 #define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
4021 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)
4022 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
4023 #define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
4024 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)
4025 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
4026 #define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
4027 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)
4028 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
4029 #define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
4030 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)
4031 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
4032 #define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
4033 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)
4034 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
4035 #define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
4036 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)
4037 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
4038 #define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
4039 #define RCC_APB1RSTR_USART2RST_Pos               (17U)
4040 #define RCC_APB1RSTR_USART2RST_Msk               (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
4041 #define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
4042 #define RCC_APB1RSTR_USART3RST_Pos               (18U)
4043 #define RCC_APB1RSTR_USART3RST_Msk               (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
4044 #define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
4045 #define RCC_APB1RSTR_USART4RST_Pos               (19U)
4046 #define RCC_APB1RSTR_USART4RST_Msk               (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
4047 #define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 reset */
4048 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)
4049 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
4050 #define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
4051 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)
4052 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
4053 #define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
4054 #define RCC_APB1RSTR_CRSRST_Pos                  (27U)
4055 #define RCC_APB1RSTR_CRSRST_Msk                  (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
4056 #define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS reset */
4057 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)
4058 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
4059 #define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
4060 #define RCC_APB1RSTR_DACRST_Pos                  (29U)
4061 #define RCC_APB1RSTR_DACRST_Msk                  (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
4062 #define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC reset */
4063 #define RCC_APB1RSTR_CECRST_Pos                  (30U)
4064 #define RCC_APB1RSTR_CECRST_Msk                  (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
4065 #define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
4066 
4067 /******************  Bit definition for RCC_AHBENR register  *****************/
4068 #define RCC_AHBENR_DMAEN_Pos                     (0U)
4069 #define RCC_AHBENR_DMAEN_Msk                     (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
4070 #define RCC_AHBENR_DMAEN                         RCC_AHBENR_DMAEN_Msk          /*!< DMA1 clock enable */
4071 #define RCC_AHBENR_SRAMEN_Pos                    (2U)
4072 #define RCC_AHBENR_SRAMEN_Msk                    (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
4073 #define RCC_AHBENR_SRAMEN                        RCC_AHBENR_SRAMEN_Msk         /*!< SRAM interface clock enable */
4074 #define RCC_AHBENR_FLITFEN_Pos                   (4U)
4075 #define RCC_AHBENR_FLITFEN_Msk                   (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
4076 #define RCC_AHBENR_FLITFEN                       RCC_AHBENR_FLITFEN_Msk        /*!< FLITF clock enable */
4077 #define RCC_AHBENR_CRCEN_Pos                     (6U)
4078 #define RCC_AHBENR_CRCEN_Msk                     (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
4079 #define RCC_AHBENR_CRCEN                         RCC_AHBENR_CRCEN_Msk          /*!< CRC clock enable */
4080 #define RCC_AHBENR_GPIOAEN_Pos                   (17U)
4081 #define RCC_AHBENR_GPIOAEN_Msk                   (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
4082 #define RCC_AHBENR_GPIOAEN                       RCC_AHBENR_GPIOAEN_Msk        /*!< GPIOA clock enable */
4083 #define RCC_AHBENR_GPIOBEN_Pos                   (18U)
4084 #define RCC_AHBENR_GPIOBEN_Msk                   (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
4085 #define RCC_AHBENR_GPIOBEN                       RCC_AHBENR_GPIOBEN_Msk        /*!< GPIOB clock enable */
4086 #define RCC_AHBENR_GPIOCEN_Pos                   (19U)
4087 #define RCC_AHBENR_GPIOCEN_Msk                   (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
4088 #define RCC_AHBENR_GPIOCEN                       RCC_AHBENR_GPIOCEN_Msk        /*!< GPIOC clock enable */
4089 #define RCC_AHBENR_GPIODEN_Pos                   (20U)
4090 #define RCC_AHBENR_GPIODEN_Msk                   (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
4091 #define RCC_AHBENR_GPIODEN                       RCC_AHBENR_GPIODEN_Msk        /*!< GPIOD clock enable */
4092 #define RCC_AHBENR_GPIOEEN_Pos                   (21U)
4093 #define RCC_AHBENR_GPIOEEN_Msk                   (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
4094 #define RCC_AHBENR_GPIOEEN                       RCC_AHBENR_GPIOEEN_Msk        /*!< GPIOE clock enable */
4095 #define RCC_AHBENR_GPIOFEN_Pos                   (22U)
4096 #define RCC_AHBENR_GPIOFEN_Msk                   (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
4097 #define RCC_AHBENR_GPIOFEN                       RCC_AHBENR_GPIOFEN_Msk        /*!< GPIOF clock enable */
4098 #define RCC_AHBENR_TSCEN_Pos                     (24U)
4099 #define RCC_AHBENR_TSCEN_Msk                     (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
4100 #define RCC_AHBENR_TSCEN                         RCC_AHBENR_TSCEN_Msk          /*!< TS controller clock enable */
4101 
4102 /* Old Bit definition maintained for legacy purpose */
4103 #define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
4104 #define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
4105 
4106 /*****************  Bit definition for RCC_APB2ENR register  *****************/
4107 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos             (0U)
4108 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
4109 #define RCC_APB2ENR_SYSCFGCOMPEN                 RCC_APB2ENR_SYSCFGCOMPEN_Msk  /*!< SYSCFG and comparator clock enable */
4110 #define RCC_APB2ENR_ADCEN_Pos                    (9U)
4111 #define RCC_APB2ENR_ADCEN_Msk                    (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
4112 #define RCC_APB2ENR_ADCEN                        RCC_APB2ENR_ADCEN_Msk         /*!< ADC1 clock enable */
4113 #define RCC_APB2ENR_TIM1EN_Pos                   (11U)
4114 #define RCC_APB2ENR_TIM1EN_Msk                   (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
4115 #define RCC_APB2ENR_TIM1EN                       RCC_APB2ENR_TIM1EN_Msk        /*!< TIM1 clock enable */
4116 #define RCC_APB2ENR_SPI1EN_Pos                   (12U)
4117 #define RCC_APB2ENR_SPI1EN_Msk                   (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
4118 #define RCC_APB2ENR_SPI1EN                       RCC_APB2ENR_SPI1EN_Msk        /*!< SPI1 clock enable */
4119 #define RCC_APB2ENR_USART1EN_Pos                 (14U)
4120 #define RCC_APB2ENR_USART1EN_Msk                 (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
4121 #define RCC_APB2ENR_USART1EN                     RCC_APB2ENR_USART1EN_Msk      /*!< USART1 clock enable */
4122 #define RCC_APB2ENR_TIM15EN_Pos                  (16U)
4123 #define RCC_APB2ENR_TIM15EN_Msk                  (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
4124 #define RCC_APB2ENR_TIM15EN                      RCC_APB2ENR_TIM15EN_Msk       /*!< TIM15 clock enable */
4125 #define RCC_APB2ENR_TIM16EN_Pos                  (17U)
4126 #define RCC_APB2ENR_TIM16EN_Msk                  (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
4127 #define RCC_APB2ENR_TIM16EN                      RCC_APB2ENR_TIM16EN_Msk       /*!< TIM16 clock enable */
4128 #define RCC_APB2ENR_TIM17EN_Pos                  (18U)
4129 #define RCC_APB2ENR_TIM17EN_Msk                  (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
4130 #define RCC_APB2ENR_TIM17EN                      RCC_APB2ENR_TIM17EN_Msk       /*!< TIM17 clock enable */
4131 #define RCC_APB2ENR_DBGMCUEN_Pos                 (22U)
4132 #define RCC_APB2ENR_DBGMCUEN_Msk                 (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
4133 #define RCC_APB2ENR_DBGMCUEN                     RCC_APB2ENR_DBGMCUEN_Msk      /*!< DBGMCU clock enable */
4134 
4135 /* Old Bit definition maintained for legacy purpose */
4136 #define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
4137 #define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
4138 
4139 /*****************  Bit definition for RCC_APB1ENR register  *****************/
4140 #define RCC_APB1ENR_TIM2EN_Pos                   (0U)
4141 #define RCC_APB1ENR_TIM2EN_Msk                   (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
4142 #define RCC_APB1ENR_TIM2EN                       RCC_APB1ENR_TIM2EN_Msk        /*!< Timer 2 clock enable */
4143 #define RCC_APB1ENR_TIM3EN_Pos                   (1U)
4144 #define RCC_APB1ENR_TIM3EN_Msk                   (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
4145 #define RCC_APB1ENR_TIM3EN                       RCC_APB1ENR_TIM3EN_Msk        /*!< Timer 3 clock enable */
4146 #define RCC_APB1ENR_TIM6EN_Pos                   (4U)
4147 #define RCC_APB1ENR_TIM6EN_Msk                   (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
4148 #define RCC_APB1ENR_TIM6EN                       RCC_APB1ENR_TIM6EN_Msk        /*!< Timer 6 clock enable */
4149 #define RCC_APB1ENR_TIM7EN_Pos                   (5U)
4150 #define RCC_APB1ENR_TIM7EN_Msk                   (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
4151 #define RCC_APB1ENR_TIM7EN                       RCC_APB1ENR_TIM7EN_Msk        /*!< Timer 7 clock enable */
4152 #define RCC_APB1ENR_TIM14EN_Pos                  (8U)
4153 #define RCC_APB1ENR_TIM14EN_Msk                  (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
4154 #define RCC_APB1ENR_TIM14EN                      RCC_APB1ENR_TIM14EN_Msk       /*!< Timer 14 clock enable */
4155 #define RCC_APB1ENR_WWDGEN_Pos                   (11U)
4156 #define RCC_APB1ENR_WWDGEN_Msk                   (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
4157 #define RCC_APB1ENR_WWDGEN                       RCC_APB1ENR_WWDGEN_Msk        /*!< Window Watchdog clock enable */
4158 #define RCC_APB1ENR_SPI2EN_Pos                   (14U)
4159 #define RCC_APB1ENR_SPI2EN_Msk                   (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
4160 #define RCC_APB1ENR_SPI2EN                       RCC_APB1ENR_SPI2EN_Msk        /*!< SPI2 clock enable */
4161 #define RCC_APB1ENR_USART2EN_Pos                 (17U)
4162 #define RCC_APB1ENR_USART2EN_Msk                 (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
4163 #define RCC_APB1ENR_USART2EN                     RCC_APB1ENR_USART2EN_Msk      /*!< USART2 clock enable */
4164 #define RCC_APB1ENR_USART3EN_Pos                 (18U)
4165 #define RCC_APB1ENR_USART3EN_Msk                 (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
4166 #define RCC_APB1ENR_USART3EN                     RCC_APB1ENR_USART3EN_Msk      /*!< USART3 clock enable */
4167 #define RCC_APB1ENR_USART4EN_Pos                 (19U)
4168 #define RCC_APB1ENR_USART4EN_Msk                 (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
4169 #define RCC_APB1ENR_USART4EN                     RCC_APB1ENR_USART4EN_Msk      /*!< USART4 clock enable */
4170 #define RCC_APB1ENR_I2C1EN_Pos                   (21U)
4171 #define RCC_APB1ENR_I2C1EN_Msk                   (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
4172 #define RCC_APB1ENR_I2C1EN                       RCC_APB1ENR_I2C1EN_Msk        /*!< I2C1 clock enable */
4173 #define RCC_APB1ENR_I2C2EN_Pos                   (22U)
4174 #define RCC_APB1ENR_I2C2EN_Msk                   (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
4175 #define RCC_APB1ENR_I2C2EN                       RCC_APB1ENR_I2C2EN_Msk        /*!< I2C2 clock enable */
4176 #define RCC_APB1ENR_CRSEN_Pos                    (27U)
4177 #define RCC_APB1ENR_CRSEN_Msk                    (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
4178 #define RCC_APB1ENR_CRSEN                        RCC_APB1ENR_CRSEN_Msk         /*!< CRS clock enable */
4179 #define RCC_APB1ENR_PWREN_Pos                    (28U)
4180 #define RCC_APB1ENR_PWREN_Msk                    (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
4181 #define RCC_APB1ENR_PWREN                        RCC_APB1ENR_PWREN_Msk         /*!< PWR clock enable */
4182 #define RCC_APB1ENR_DACEN_Pos                    (29U)
4183 #define RCC_APB1ENR_DACEN_Msk                    (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
4184 #define RCC_APB1ENR_DACEN                        RCC_APB1ENR_DACEN_Msk         /*!< DAC clock enable */
4185 #define RCC_APB1ENR_CECEN_Pos                    (30U)
4186 #define RCC_APB1ENR_CECEN_Msk                    (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
4187 #define RCC_APB1ENR_CECEN                        RCC_APB1ENR_CECEN_Msk         /*!< CEC clock enable */
4188 
4189 /*******************  Bit definition for RCC_BDCR register  ******************/
4190 #define RCC_BDCR_LSEON_Pos                       (0U)
4191 #define RCC_BDCR_LSEON_Msk                       (0x1UL << RCC_BDCR_LSEON_Pos)  /*!< 0x00000001 */
4192 #define RCC_BDCR_LSEON                           RCC_BDCR_LSEON_Msk            /*!< External Low Speed oscillator enable */
4193 #define RCC_BDCR_LSERDY_Pos                      (1U)
4194 #define RCC_BDCR_LSERDY_Msk                      (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
4195 #define RCC_BDCR_LSERDY                          RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
4196 #define RCC_BDCR_LSEBYP_Pos                      (2U)
4197 #define RCC_BDCR_LSEBYP_Msk                      (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
4198 #define RCC_BDCR_LSEBYP                          RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */
4199 
4200 #define RCC_BDCR_LSEDRV_Pos                      (3U)
4201 #define RCC_BDCR_LSEDRV_Msk                      (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
4202 #define RCC_BDCR_LSEDRV                          RCC_BDCR_LSEDRV_Msk           /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
4203 #define RCC_BDCR_LSEDRV_0                        (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
4204 #define RCC_BDCR_LSEDRV_1                        (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
4205 
4206 #define RCC_BDCR_RTCSEL_Pos                      (8U)
4207 #define RCC_BDCR_RTCSEL_Msk                      (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
4208 #define RCC_BDCR_RTCSEL                          RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
4209 #define RCC_BDCR_RTCSEL_0                        (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
4210 #define RCC_BDCR_RTCSEL_1                        (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
4211 
4212 /*!< RTC configuration */
4213 #define RCC_BDCR_RTCSEL_NOCLOCK                  (0x00000000U)                 /*!< No clock */
4214 #define RCC_BDCR_RTCSEL_LSE                      (0x00000100U)                 /*!< LSE oscillator clock used as RTC clock */
4215 #define RCC_BDCR_RTCSEL_LSI                      (0x00000200U)                 /*!< LSI oscillator clock used as RTC clock */
4216 #define RCC_BDCR_RTCSEL_HSE                      (0x00000300U)                 /*!< HSE oscillator clock divided by 128 used as RTC clock */
4217 
4218 #define RCC_BDCR_RTCEN_Pos                       (15U)
4219 #define RCC_BDCR_RTCEN_Msk                       (0x1UL << RCC_BDCR_RTCEN_Pos)  /*!< 0x00008000 */
4220 #define RCC_BDCR_RTCEN                           RCC_BDCR_RTCEN_Msk            /*!< RTC clock enable */
4221 #define RCC_BDCR_BDRST_Pos                       (16U)
4222 #define RCC_BDCR_BDRST_Msk                       (0x1UL << RCC_BDCR_BDRST_Pos)  /*!< 0x00010000 */
4223 #define RCC_BDCR_BDRST                           RCC_BDCR_BDRST_Msk            /*!< Backup domain software reset  */
4224 
4225 /*******************  Bit definition for RCC_CSR register  *******************/
4226 #define RCC_CSR_LSION_Pos                        (0U)
4227 #define RCC_CSR_LSION_Msk                        (0x1UL << RCC_CSR_LSION_Pos)   /*!< 0x00000001 */
4228 #define RCC_CSR_LSION                            RCC_CSR_LSION_Msk             /*!< Internal Low Speed oscillator enable */
4229 #define RCC_CSR_LSIRDY_Pos                       (1U)
4230 #define RCC_CSR_LSIRDY_Msk                       (0x1UL << RCC_CSR_LSIRDY_Pos)  /*!< 0x00000002 */
4231 #define RCC_CSR_LSIRDY                           RCC_CSR_LSIRDY_Msk            /*!< Internal Low Speed oscillator Ready */
4232 #define RCC_CSR_V18PWRRSTF_Pos                   (23U)
4233 #define RCC_CSR_V18PWRRSTF_Msk                   (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
4234 #define RCC_CSR_V18PWRRSTF                       RCC_CSR_V18PWRRSTF_Msk        /*!< V1.8 power domain reset flag */
4235 #define RCC_CSR_RMVF_Pos                         (24U)
4236 #define RCC_CSR_RMVF_Msk                         (0x1UL << RCC_CSR_RMVF_Pos)    /*!< 0x01000000 */
4237 #define RCC_CSR_RMVF                             RCC_CSR_RMVF_Msk              /*!< Remove reset flag */
4238 #define RCC_CSR_OBLRSTF_Pos                      (25U)
4239 #define RCC_CSR_OBLRSTF_Msk                      (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
4240 #define RCC_CSR_OBLRSTF                          RCC_CSR_OBLRSTF_Msk           /*!< OBL reset flag */
4241 #define RCC_CSR_PINRSTF_Pos                      (26U)
4242 #define RCC_CSR_PINRSTF_Msk                      (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
4243 #define RCC_CSR_PINRSTF                          RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
4244 #define RCC_CSR_PORRSTF_Pos                      (27U)
4245 #define RCC_CSR_PORRSTF_Msk                      (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
4246 #define RCC_CSR_PORRSTF                          RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
4247 #define RCC_CSR_SFTRSTF_Pos                      (28U)
4248 #define RCC_CSR_SFTRSTF_Msk                      (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
4249 #define RCC_CSR_SFTRSTF                          RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
4250 #define RCC_CSR_IWDGRSTF_Pos                     (29U)
4251 #define RCC_CSR_IWDGRSTF_Msk                     (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
4252 #define RCC_CSR_IWDGRSTF                         RCC_CSR_IWDGRSTF_Msk          /*!< Independent Watchdog reset flag */
4253 #define RCC_CSR_WWDGRSTF_Pos                     (30U)
4254 #define RCC_CSR_WWDGRSTF_Msk                     (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
4255 #define RCC_CSR_WWDGRSTF                         RCC_CSR_WWDGRSTF_Msk          /*!< Window watchdog reset flag */
4256 #define RCC_CSR_LPWRRSTF_Pos                     (31U)
4257 #define RCC_CSR_LPWRRSTF_Msk                     (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
4258 #define RCC_CSR_LPWRRSTF                         RCC_CSR_LPWRRSTF_Msk          /*!< Low-Power reset flag */
4259 
4260 /* Old Bit definition maintained for legacy purpose */
4261 #define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
4262 
4263 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
4264 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)
4265 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
4266 #define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
4267 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)
4268 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
4269 #define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
4270 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)
4271 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
4272 #define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
4273 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)
4274 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
4275 #define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
4276 #define RCC_AHBRSTR_GPIOERST_Pos                 (21U)
4277 #define RCC_AHBRSTR_GPIOERST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
4278 #define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE reset */
4279 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)
4280 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
4281 #define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
4282 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)
4283 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
4284 #define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
4285 
4286 /* Old Bit definition maintained for legacy purpose */
4287 #define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
4288 
4289 /*******************  Bit definition for RCC_CFGR2 register  *****************/
4290 /*!< PREDIV configuration */
4291 #define RCC_CFGR2_PREDIV_Pos                     (0U)
4292 #define RCC_CFGR2_PREDIV_Msk                     (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
4293 #define RCC_CFGR2_PREDIV                         RCC_CFGR2_PREDIV_Msk          /*!< PREDIV[3:0] bits */
4294 #define RCC_CFGR2_PREDIV_0                       (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
4295 #define RCC_CFGR2_PREDIV_1                       (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
4296 #define RCC_CFGR2_PREDIV_2                       (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
4297 #define RCC_CFGR2_PREDIV_3                       (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
4298 
4299 #define RCC_CFGR2_PREDIV_DIV1                    (0x00000000U)                 /*!< PREDIV input clock not divided */
4300 #define RCC_CFGR2_PREDIV_DIV2                    (0x00000001U)                 /*!< PREDIV input clock divided by 2 */
4301 #define RCC_CFGR2_PREDIV_DIV3                    (0x00000002U)                 /*!< PREDIV input clock divided by 3 */
4302 #define RCC_CFGR2_PREDIV_DIV4                    (0x00000003U)                 /*!< PREDIV input clock divided by 4 */
4303 #define RCC_CFGR2_PREDIV_DIV5                    (0x00000004U)                 /*!< PREDIV input clock divided by 5 */
4304 #define RCC_CFGR2_PREDIV_DIV6                    (0x00000005U)                 /*!< PREDIV input clock divided by 6 */
4305 #define RCC_CFGR2_PREDIV_DIV7                    (0x00000006U)                 /*!< PREDIV input clock divided by 7 */
4306 #define RCC_CFGR2_PREDIV_DIV8                    (0x00000007U)                 /*!< PREDIV input clock divided by 8 */
4307 #define RCC_CFGR2_PREDIV_DIV9                    (0x00000008U)                 /*!< PREDIV input clock divided by 9 */
4308 #define RCC_CFGR2_PREDIV_DIV10                   (0x00000009U)                 /*!< PREDIV input clock divided by 10 */
4309 #define RCC_CFGR2_PREDIV_DIV11                   (0x0000000AU)                 /*!< PREDIV input clock divided by 11 */
4310 #define RCC_CFGR2_PREDIV_DIV12                   (0x0000000BU)                 /*!< PREDIV input clock divided by 12 */
4311 #define RCC_CFGR2_PREDIV_DIV13                   (0x0000000CU)                 /*!< PREDIV input clock divided by 13 */
4312 #define RCC_CFGR2_PREDIV_DIV14                   (0x0000000DU)                 /*!< PREDIV input clock divided by 14 */
4313 #define RCC_CFGR2_PREDIV_DIV15                   (0x0000000EU)                 /*!< PREDIV input clock divided by 15 */
4314 #define RCC_CFGR2_PREDIV_DIV16                   (0x0000000FU)                 /*!< PREDIV input clock divided by 16 */
4315 
4316 /*******************  Bit definition for RCC_CFGR3 register  *****************/
4317 /*!< USART1 Clock source selection */
4318 #define RCC_CFGR3_USART1SW_Pos                   (0U)
4319 #define RCC_CFGR3_USART1SW_Msk                   (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
4320 #define RCC_CFGR3_USART1SW                       RCC_CFGR3_USART1SW_Msk        /*!< USART1SW[1:0] bits */
4321 #define RCC_CFGR3_USART1SW_0                     (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
4322 #define RCC_CFGR3_USART1SW_1                     (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
4323 
4324 #define RCC_CFGR3_USART1SW_PCLK                  (0x00000000U)                 /*!< PCLK clock used as USART1 clock source */
4325 #define RCC_CFGR3_USART1SW_SYSCLK                (0x00000001U)                 /*!< System clock selected as USART1 clock source */
4326 #define RCC_CFGR3_USART1SW_LSE                   (0x00000002U)                 /*!< LSE oscillator clock used as USART1 clock source */
4327 #define RCC_CFGR3_USART1SW_HSI                   (0x00000003U)                 /*!< HSI oscillator clock used as USART1 clock source */
4328 
4329 /*!< I2C1 Clock source selection */
4330 #define RCC_CFGR3_I2C1SW_Pos                     (4U)
4331 #define RCC_CFGR3_I2C1SW_Msk                     (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
4332 #define RCC_CFGR3_I2C1SW                         RCC_CFGR3_I2C1SW_Msk          /*!< I2C1SW bits */
4333 
4334 #define RCC_CFGR3_I2C1SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C1 clock source */
4335 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos              (4U)
4336 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk              (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
4337 #define RCC_CFGR3_I2C1SW_SYSCLK                  RCC_CFGR3_I2C1SW_SYSCLK_Msk   /*!< System clock selected as I2C1 clock source */
4338 
4339 /*!< CEC Clock source selection */
4340 #define RCC_CFGR3_CECSW_Pos                      (6U)
4341 #define RCC_CFGR3_CECSW_Msk                      (0x1UL << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */
4342 #define RCC_CFGR3_CECSW                          RCC_CFGR3_CECSW_Msk           /*!< CECSW bits */
4343 
4344 #define RCC_CFGR3_CECSW_HSI_DIV244               (0x00000000U)                 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
4345 #define RCC_CFGR3_CECSW_LSE_Pos                  (6U)
4346 #define RCC_CFGR3_CECSW_LSE_Msk                  (0x1UL << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */
4347 #define RCC_CFGR3_CECSW_LSE                      RCC_CFGR3_CECSW_LSE_Msk       /*!< LSE clock selected as HDMI CEC entry clock source */
4348 
4349 /*!< USART2 Clock source selection */
4350 #define RCC_CFGR3_USART2SW_Pos                   (16U)
4351 #define RCC_CFGR3_USART2SW_Msk                   (0x3UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
4352 #define RCC_CFGR3_USART2SW                       RCC_CFGR3_USART2SW_Msk        /*!< USART2SW[1:0] bits */
4353 #define RCC_CFGR3_USART2SW_0                     (0x1UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
4354 #define RCC_CFGR3_USART2SW_1                     (0x2UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
4355 
4356 #define RCC_CFGR3_USART2SW_PCLK                  (0x00000000U)                 /*!< PCLK clock used as USART2 clock source */
4357 #define RCC_CFGR3_USART2SW_SYSCLK                (0x00010000U)                 /*!< System clock selected as USART2 clock source */
4358 #define RCC_CFGR3_USART2SW_LSE                   (0x00020000U)                 /*!< LSE oscillator clock used as USART2 clock source */
4359 #define RCC_CFGR3_USART2SW_HSI                   (0x00030000U)                 /*!< HSI oscillator clock used as USART2 clock source */
4360 
4361 /*******************  Bit definition for RCC_CR2 register  *******************/
4362 #define RCC_CR2_HSI14ON_Pos                      (0U)
4363 #define RCC_CR2_HSI14ON_Msk                      (0x1UL << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
4364 #define RCC_CR2_HSI14ON                          RCC_CR2_HSI14ON_Msk           /*!< Internal High Speed 14MHz clock enable */
4365 #define RCC_CR2_HSI14RDY_Pos                     (1U)
4366 #define RCC_CR2_HSI14RDY_Msk                     (0x1UL << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
4367 #define RCC_CR2_HSI14RDY                         RCC_CR2_HSI14RDY_Msk          /*!< Internal High Speed 14MHz clock ready flag */
4368 #define RCC_CR2_HSI14DIS_Pos                     (2U)
4369 #define RCC_CR2_HSI14DIS_Msk                     (0x1UL << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
4370 #define RCC_CR2_HSI14DIS                         RCC_CR2_HSI14DIS_Msk          /*!< Internal High Speed 14MHz clock disable */
4371 #define RCC_CR2_HSI14TRIM_Pos                    (3U)
4372 #define RCC_CR2_HSI14TRIM_Msk                    (0x1FUL << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
4373 #define RCC_CR2_HSI14TRIM                        RCC_CR2_HSI14TRIM_Msk         /*!< Internal High Speed 14MHz clock trimming */
4374 #define RCC_CR2_HSI14CAL_Pos                     (8U)
4375 #define RCC_CR2_HSI14CAL_Msk                     (0xFFUL << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
4376 #define RCC_CR2_HSI14CAL                         RCC_CR2_HSI14CAL_Msk          /*!< Internal High Speed 14MHz clock Calibration */
4377 #define RCC_CR2_HSI48ON_Pos                      (16U)
4378 #define RCC_CR2_HSI48ON_Msk                      (0x1UL << RCC_CR2_HSI48ON_Pos) /*!< 0x00010000 */
4379 #define RCC_CR2_HSI48ON                          RCC_CR2_HSI48ON_Msk           /*!< Internal High Speed 48MHz clock enable */
4380 #define RCC_CR2_HSI48RDY_Pos                     (17U)
4381 #define RCC_CR2_HSI48RDY_Msk                     (0x1UL << RCC_CR2_HSI48RDY_Pos) /*!< 0x00020000 */
4382 #define RCC_CR2_HSI48RDY                         RCC_CR2_HSI48RDY_Msk          /*!< Internal High Speed 48MHz clock ready flag */
4383 #define RCC_CR2_HSI48CAL_Pos                     (24U)
4384 #define RCC_CR2_HSI48CAL_Msk                     (0xFFUL << RCC_CR2_HSI48CAL_Pos) /*!< 0xFF000000 */
4385 #define RCC_CR2_HSI48CAL                         RCC_CR2_HSI48CAL_Msk          /*!< Internal High Speed 48MHz clock Calibration */
4386 
4387 /*****************************************************************************/
4388 /*                                                                           */
4389 /*                           Real-Time Clock (RTC)                           */
4390 /*                                                                           */
4391 /*****************************************************************************/
4392 /*
4393 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 series)
4394 */
4395 #define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
4396 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
4397 #define RTC_TAMPER3_SUPPORT  /*!< TAMPER 3 feature support */
4398 #define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */
4399 #define RTC_WAKEUP_SUPPORT   /*!< WAKEUP feature support */
4400 
4401 /********************  Bits definition for RTC_TR register  ******************/
4402 #define RTC_TR_PM_Pos                (22U)
4403 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
4404 #define RTC_TR_PM                    RTC_TR_PM_Msk
4405 #define RTC_TR_HT_Pos                (20U)
4406 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
4407 #define RTC_TR_HT                    RTC_TR_HT_Msk
4408 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
4409 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
4410 #define RTC_TR_HU_Pos                (16U)
4411 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
4412 #define RTC_TR_HU                    RTC_TR_HU_Msk
4413 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
4414 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
4415 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
4416 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
4417 #define RTC_TR_MNT_Pos               (12U)
4418 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
4419 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
4420 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
4421 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
4422 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
4423 #define RTC_TR_MNU_Pos               (8U)
4424 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
4425 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
4426 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
4427 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
4428 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
4429 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
4430 #define RTC_TR_ST_Pos                (4U)
4431 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
4432 #define RTC_TR_ST                    RTC_TR_ST_Msk
4433 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
4434 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
4435 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
4436 #define RTC_TR_SU_Pos                (0U)
4437 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
4438 #define RTC_TR_SU                    RTC_TR_SU_Msk
4439 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
4440 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
4441 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
4442 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
4443 
4444 /********************  Bits definition for RTC_DR register  ******************/
4445 #define RTC_DR_YT_Pos                (20U)
4446 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
4447 #define RTC_DR_YT                    RTC_DR_YT_Msk
4448 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
4449 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
4450 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
4451 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
4452 #define RTC_DR_YU_Pos                (16U)
4453 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
4454 #define RTC_DR_YU                    RTC_DR_YU_Msk
4455 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
4456 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
4457 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
4458 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
4459 #define RTC_DR_WDU_Pos               (13U)
4460 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
4461 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
4462 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
4463 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
4464 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
4465 #define RTC_DR_MT_Pos                (12U)
4466 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
4467 #define RTC_DR_MT                    RTC_DR_MT_Msk
4468 #define RTC_DR_MU_Pos                (8U)
4469 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
4470 #define RTC_DR_MU                    RTC_DR_MU_Msk
4471 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
4472 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
4473 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
4474 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
4475 #define RTC_DR_DT_Pos                (4U)
4476 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
4477 #define RTC_DR_DT                    RTC_DR_DT_Msk
4478 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
4479 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
4480 #define RTC_DR_DU_Pos                (0U)
4481 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
4482 #define RTC_DR_DU                    RTC_DR_DU_Msk
4483 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
4484 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
4485 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
4486 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
4487 
4488 /********************  Bits definition for RTC_CR register  ******************/
4489 #define RTC_CR_COE_Pos               (23U)
4490 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                  /*!< 0x00800000 */
4491 #define RTC_CR_COE                   RTC_CR_COE_Msk
4492 #define RTC_CR_OSEL_Pos              (21U)
4493 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
4494 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
4495 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
4496 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
4497 #define RTC_CR_POL_Pos               (20U)
4498 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
4499 #define RTC_CR_POL                   RTC_CR_POL_Msk
4500 #define RTC_CR_COSEL_Pos             (19U)
4501 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
4502 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
4503 #define RTC_CR_BKP_Pos               (18U)
4504 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
4505 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
4506 #define RTC_CR_SUB1H_Pos             (17U)
4507 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
4508 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
4509 #define RTC_CR_ADD1H_Pos             (16U)
4510 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
4511 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
4512 #define RTC_CR_TSIE_Pos              (15U)
4513 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                 /*!< 0x00008000 */
4514 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
4515 #define RTC_CR_WUTIE_Pos             (14U)
4516 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)                /*!< 0x00004000 */
4517 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
4518 #define RTC_CR_ALRAIE_Pos            (12U)
4519 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)               /*!< 0x00001000 */
4520 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
4521 #define RTC_CR_TSE_Pos               (11U)
4522 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                  /*!< 0x00000800 */
4523 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
4524 #define RTC_CR_WUTE_Pos              (10U)
4525 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                 /*!< 0x00000400 */
4526 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
4527 #define RTC_CR_ALRAE_Pos             (8U)
4528 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
4529 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
4530 #define RTC_CR_FMT_Pos               (6U)
4531 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
4532 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
4533 #define RTC_CR_BYPSHAD_Pos           (5U)
4534 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
4535 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
4536 #define RTC_CR_REFCKON_Pos           (4U)
4537 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
4538 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
4539 #define RTC_CR_TSEDGE_Pos            (3U)
4540 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
4541 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
4542 #define RTC_CR_WUCKSEL_Pos           (0U)
4543 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000007 */
4544 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
4545 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000001 */
4546 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
4547 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
4548 
4549 /* Legacy defines */
4550 #define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
4551 #define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
4552 #define RTC_CR_BCK                   RTC_CR_BKP
4553 
4554 /********************  Bits definition for RTC_ISR register  *****************/
4555 #define RTC_ISR_RECALPF_Pos          (16U)
4556 #define RTC_ISR_RECALPF_Msk          (0x1UL << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
4557 #define RTC_ISR_RECALPF              RTC_ISR_RECALPF_Msk
4558 #define RTC_ISR_TAMP3F_Pos           (15U)
4559 #define RTC_ISR_TAMP3F_Msk           (0x1UL << RTC_ISR_TAMP3F_Pos)              /*!< 0x00008000 */
4560 #define RTC_ISR_TAMP3F               RTC_ISR_TAMP3F_Msk
4561 #define RTC_ISR_TAMP2F_Pos           (14U)
4562 #define RTC_ISR_TAMP2F_Msk           (0x1UL << RTC_ISR_TAMP2F_Pos)              /*!< 0x00004000 */
4563 #define RTC_ISR_TAMP2F               RTC_ISR_TAMP2F_Msk
4564 #define RTC_ISR_TAMP1F_Pos           (13U)
4565 #define RTC_ISR_TAMP1F_Msk           (0x1UL << RTC_ISR_TAMP1F_Pos)              /*!< 0x00002000 */
4566 #define RTC_ISR_TAMP1F               RTC_ISR_TAMP1F_Msk
4567 #define RTC_ISR_TSOVF_Pos            (12U)
4568 #define RTC_ISR_TSOVF_Msk            (0x1UL << RTC_ISR_TSOVF_Pos)               /*!< 0x00001000 */
4569 #define RTC_ISR_TSOVF                RTC_ISR_TSOVF_Msk
4570 #define RTC_ISR_TSF_Pos              (11U)
4571 #define RTC_ISR_TSF_Msk              (0x1UL << RTC_ISR_TSF_Pos)                 /*!< 0x00000800 */
4572 #define RTC_ISR_TSF                  RTC_ISR_TSF_Msk
4573 #define RTC_ISR_WUTF_Pos             (10U)
4574 #define RTC_ISR_WUTF_Msk             (0x1UL << RTC_ISR_WUTF_Pos)                /*!< 0x00000400 */
4575 #define RTC_ISR_WUTF                 RTC_ISR_WUTF_Msk
4576 #define RTC_ISR_ALRAF_Pos            (8U)
4577 #define RTC_ISR_ALRAF_Msk            (0x1UL << RTC_ISR_ALRAF_Pos)               /*!< 0x00000100 */
4578 #define RTC_ISR_ALRAF                RTC_ISR_ALRAF_Msk
4579 #define RTC_ISR_INIT_Pos             (7U)
4580 #define RTC_ISR_INIT_Msk             (0x1UL << RTC_ISR_INIT_Pos)                /*!< 0x00000080 */
4581 #define RTC_ISR_INIT                 RTC_ISR_INIT_Msk
4582 #define RTC_ISR_INITF_Pos            (6U)
4583 #define RTC_ISR_INITF_Msk            (0x1UL << RTC_ISR_INITF_Pos)               /*!< 0x00000040 */
4584 #define RTC_ISR_INITF                RTC_ISR_INITF_Msk
4585 #define RTC_ISR_RSF_Pos              (5U)
4586 #define RTC_ISR_RSF_Msk              (0x1UL << RTC_ISR_RSF_Pos)                 /*!< 0x00000020 */
4587 #define RTC_ISR_RSF                  RTC_ISR_RSF_Msk
4588 #define RTC_ISR_INITS_Pos            (4U)
4589 #define RTC_ISR_INITS_Msk            (0x1UL << RTC_ISR_INITS_Pos)               /*!< 0x00000010 */
4590 #define RTC_ISR_INITS                RTC_ISR_INITS_Msk
4591 #define RTC_ISR_SHPF_Pos             (3U)
4592 #define RTC_ISR_SHPF_Msk             (0x1UL << RTC_ISR_SHPF_Pos)                /*!< 0x00000008 */
4593 #define RTC_ISR_SHPF                 RTC_ISR_SHPF_Msk
4594 #define RTC_ISR_WUTWF_Pos            (2U)
4595 #define RTC_ISR_WUTWF_Msk            (0x1UL << RTC_ISR_WUTWF_Pos)               /*!< 0x00000004 */
4596 #define RTC_ISR_WUTWF                RTC_ISR_WUTWF_Msk
4597 #define RTC_ISR_ALRAWF_Pos           (0U)
4598 #define RTC_ISR_ALRAWF_Msk           (0x1UL << RTC_ISR_ALRAWF_Pos)              /*!< 0x00000001 */
4599 #define RTC_ISR_ALRAWF               RTC_ISR_ALRAWF_Msk
4600 
4601 /********************  Bits definition for RTC_PRER register  ****************/
4602 #define RTC_PRER_PREDIV_A_Pos        (16U)
4603 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
4604 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
4605 #define RTC_PRER_PREDIV_S_Pos        (0U)
4606 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
4607 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
4608 
4609 /********************  Bits definition for RTC_WUTR register  ****************/
4610 #define RTC_WUTR_WUT_Pos             (0U)
4611 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)             /*!< 0x0000FFFF */
4612 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
4613 
4614 /********************  Bits definition for RTC_ALRMAR register  **************/
4615 #define RTC_ALRMAR_MSK4_Pos          (31U)
4616 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)             /*!< 0x80000000 */
4617 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
4618 #define RTC_ALRMAR_WDSEL_Pos         (30U)
4619 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)            /*!< 0x40000000 */
4620 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
4621 #define RTC_ALRMAR_DT_Pos            (28U)
4622 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)               /*!< 0x30000000 */
4623 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
4624 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)               /*!< 0x10000000 */
4625 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)               /*!< 0x20000000 */
4626 #define RTC_ALRMAR_DU_Pos            (24U)
4627 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)               /*!< 0x0F000000 */
4628 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
4629 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)               /*!< 0x01000000 */
4630 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)               /*!< 0x02000000 */
4631 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)               /*!< 0x04000000 */
4632 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)               /*!< 0x08000000 */
4633 #define RTC_ALRMAR_MSK3_Pos          (23U)
4634 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)             /*!< 0x00800000 */
4635 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
4636 #define RTC_ALRMAR_PM_Pos            (22U)
4637 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)               /*!< 0x00400000 */
4638 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
4639 #define RTC_ALRMAR_HT_Pos            (20U)
4640 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00300000 */
4641 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
4642 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00100000 */
4643 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00200000 */
4644 #define RTC_ALRMAR_HU_Pos            (16U)
4645 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)               /*!< 0x000F0000 */
4646 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
4647 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00010000 */
4648 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00020000 */
4649 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00040000 */
4650 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00080000 */
4651 #define RTC_ALRMAR_MSK2_Pos          (15U)
4652 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)             /*!< 0x00008000 */
4653 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
4654 #define RTC_ALRMAR_MNT_Pos           (12U)
4655 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00007000 */
4656 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
4657 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00001000 */
4658 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00002000 */
4659 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00004000 */
4660 #define RTC_ALRMAR_MNU_Pos           (8U)
4661 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000F00 */
4662 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
4663 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000100 */
4664 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000200 */
4665 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000400 */
4666 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000800 */
4667 #define RTC_ALRMAR_MSK1_Pos          (7U)
4668 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)             /*!< 0x00000080 */
4669 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
4670 #define RTC_ALRMAR_ST_Pos            (4U)
4671 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000070 */
4672 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
4673 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000010 */
4674 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000020 */
4675 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000040 */
4676 #define RTC_ALRMAR_SU_Pos            (0U)
4677 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)               /*!< 0x0000000F */
4678 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
4679 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000001 */
4680 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000002 */
4681 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000004 */
4682 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000008 */
4683 
4684 /********************  Bits definition for RTC_WPR register  *****************/
4685 #define RTC_WPR_KEY_Pos              (0U)
4686 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
4687 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
4688 
4689 /********************  Bits definition for RTC_SSR register  *****************/
4690 #define RTC_SSR_SS_Pos               (0U)
4691 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
4692 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
4693 
4694 /********************  Bits definition for RTC_SHIFTR register  **************/
4695 #define RTC_SHIFTR_SUBFS_Pos         (0U)
4696 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
4697 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
4698 #define RTC_SHIFTR_ADD1S_Pos         (31U)
4699 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
4700 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
4701 
4702 /********************  Bits definition for RTC_TSTR register  ****************/
4703 #define RTC_TSTR_PM_Pos              (22U)
4704 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                 /*!< 0x00400000 */
4705 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
4706 #define RTC_TSTR_HT_Pos              (20U)
4707 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                 /*!< 0x00300000 */
4708 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
4709 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                 /*!< 0x00100000 */
4710 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                 /*!< 0x00200000 */
4711 #define RTC_TSTR_HU_Pos              (16U)
4712 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                 /*!< 0x000F0000 */
4713 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
4714 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                 /*!< 0x00010000 */
4715 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                 /*!< 0x00020000 */
4716 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                 /*!< 0x00040000 */
4717 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                 /*!< 0x00080000 */
4718 #define RTC_TSTR_MNT_Pos             (12U)
4719 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)                /*!< 0x00007000 */
4720 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
4721 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)                /*!< 0x00001000 */
4722 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)                /*!< 0x00002000 */
4723 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
4724 #define RTC_TSTR_MNU_Pos             (8U)
4725 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
4726 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
4727 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
4728 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
4729 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
4730 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
4731 #define RTC_TSTR_ST_Pos              (4U)
4732 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
4733 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
4734 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
4735 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
4736 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
4737 #define RTC_TSTR_SU_Pos              (0U)
4738 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
4739 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
4740 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
4741 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
4742 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
4743 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
4744 
4745 /********************  Bits definition for RTC_TSDR register  ****************/
4746 #define RTC_TSDR_WDU_Pos             (13U)
4747 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)                /*!< 0x0000E000 */
4748 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
4749 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)                /*!< 0x00002000 */
4750 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)                /*!< 0x00004000 */
4751 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)                /*!< 0x00008000 */
4752 #define RTC_TSDR_MT_Pos              (12U)
4753 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                 /*!< 0x00001000 */
4754 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
4755 #define RTC_TSDR_MU_Pos              (8U)
4756 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                 /*!< 0x00000F00 */
4757 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
4758 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000100 */
4759 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000200 */
4760 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000400 */
4761 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000800 */
4762 #define RTC_TSDR_DT_Pos              (4U)
4763 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000030 */
4764 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
4765 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000010 */
4766 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000020 */
4767 #define RTC_TSDR_DU_Pos              (0U)
4768 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                 /*!< 0x0000000F */
4769 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
4770 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000001 */
4771 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000002 */
4772 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000004 */
4773 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000008 */
4774 
4775 /********************  Bits definition for RTC_TSSSR register  ***************/
4776 #define RTC_TSSSR_SS_Pos             (0U)
4777 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
4778 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
4779 
4780 /********************  Bits definition for RTC_CALR register  ****************/
4781 #define RTC_CALR_CALP_Pos            (15U)
4782 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
4783 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
4784 #define RTC_CALR_CALW8_Pos           (14U)
4785 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
4786 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
4787 #define RTC_CALR_CALW16_Pos          (13U)
4788 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
4789 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
4790 #define RTC_CALR_CALM_Pos            (0U)
4791 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
4792 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
4793 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
4794 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
4795 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
4796 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
4797 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
4798 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
4799 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
4800 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
4801 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
4802 
4803 /********************  Bits definition for RTC_TAFCR register  ***************/
4804 #define RTC_TAFCR_PC15MODE_Pos       (23U)
4805 #define RTC_TAFCR_PC15MODE_Msk       (0x1UL << RTC_TAFCR_PC15MODE_Pos)          /*!< 0x00800000 */
4806 #define RTC_TAFCR_PC15MODE           RTC_TAFCR_PC15MODE_Msk
4807 #define RTC_TAFCR_PC15VALUE_Pos      (22U)
4808 #define RTC_TAFCR_PC15VALUE_Msk      (0x1UL << RTC_TAFCR_PC15VALUE_Pos)         /*!< 0x00400000 */
4809 #define RTC_TAFCR_PC15VALUE          RTC_TAFCR_PC15VALUE_Msk
4810 #define RTC_TAFCR_PC14MODE_Pos       (21U)
4811 #define RTC_TAFCR_PC14MODE_Msk       (0x1UL << RTC_TAFCR_PC14MODE_Pos)          /*!< 0x00200000 */
4812 #define RTC_TAFCR_PC14MODE           RTC_TAFCR_PC14MODE_Msk
4813 #define RTC_TAFCR_PC14VALUE_Pos      (20U)
4814 #define RTC_TAFCR_PC14VALUE_Msk      (0x1UL << RTC_TAFCR_PC14VALUE_Pos)         /*!< 0x00100000 */
4815 #define RTC_TAFCR_PC14VALUE          RTC_TAFCR_PC14VALUE_Msk
4816 #define RTC_TAFCR_PC13MODE_Pos       (19U)
4817 #define RTC_TAFCR_PC13MODE_Msk       (0x1UL << RTC_TAFCR_PC13MODE_Pos)          /*!< 0x00080000 */
4818 #define RTC_TAFCR_PC13MODE           RTC_TAFCR_PC13MODE_Msk
4819 #define RTC_TAFCR_PC13VALUE_Pos      (18U)
4820 #define RTC_TAFCR_PC13VALUE_Msk      (0x1UL << RTC_TAFCR_PC13VALUE_Pos)         /*!< 0x00040000 */
4821 #define RTC_TAFCR_PC13VALUE          RTC_TAFCR_PC13VALUE_Msk
4822 #define RTC_TAFCR_TAMPPUDIS_Pos      (15U)
4823 #define RTC_TAFCR_TAMPPUDIS_Msk      (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)         /*!< 0x00008000 */
4824 #define RTC_TAFCR_TAMPPUDIS          RTC_TAFCR_TAMPPUDIS_Msk
4825 #define RTC_TAFCR_TAMPPRCH_Pos       (13U)
4826 #define RTC_TAFCR_TAMPPRCH_Msk       (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00006000 */
4827 #define RTC_TAFCR_TAMPPRCH           RTC_TAFCR_TAMPPRCH_Msk
4828 #define RTC_TAFCR_TAMPPRCH_0         (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00002000 */
4829 #define RTC_TAFCR_TAMPPRCH_1         (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00004000 */
4830 #define RTC_TAFCR_TAMPFLT_Pos        (11U)
4831 #define RTC_TAFCR_TAMPFLT_Msk        (0x3UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001800 */
4832 #define RTC_TAFCR_TAMPFLT            RTC_TAFCR_TAMPFLT_Msk
4833 #define RTC_TAFCR_TAMPFLT_0          (0x1UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00000800 */
4834 #define RTC_TAFCR_TAMPFLT_1          (0x2UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001000 */
4835 #define RTC_TAFCR_TAMPFREQ_Pos       (8U)
4836 #define RTC_TAFCR_TAMPFREQ_Msk       (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000700 */
4837 #define RTC_TAFCR_TAMPFREQ           RTC_TAFCR_TAMPFREQ_Msk
4838 #define RTC_TAFCR_TAMPFREQ_0         (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000100 */
4839 #define RTC_TAFCR_TAMPFREQ_1         (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000200 */
4840 #define RTC_TAFCR_TAMPFREQ_2         (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000400 */
4841 #define RTC_TAFCR_TAMPTS_Pos         (7U)
4842 #define RTC_TAFCR_TAMPTS_Msk         (0x1UL << RTC_TAFCR_TAMPTS_Pos)            /*!< 0x00000080 */
4843 #define RTC_TAFCR_TAMPTS             RTC_TAFCR_TAMPTS_Msk
4844 #define RTC_TAFCR_TAMP3TRG_Pos       (6U)
4845 #define RTC_TAFCR_TAMP3TRG_Msk       (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)          /*!< 0x00000040 */
4846 #define RTC_TAFCR_TAMP3TRG           RTC_TAFCR_TAMP3TRG_Msk
4847 #define RTC_TAFCR_TAMP3E_Pos         (5U)
4848 #define RTC_TAFCR_TAMP3E_Msk         (0x1UL << RTC_TAFCR_TAMP3E_Pos)            /*!< 0x00000020 */
4849 #define RTC_TAFCR_TAMP3E             RTC_TAFCR_TAMP3E_Msk
4850 #define RTC_TAFCR_TAMP2TRG_Pos       (4U)
4851 #define RTC_TAFCR_TAMP2TRG_Msk       (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)          /*!< 0x00000010 */
4852 #define RTC_TAFCR_TAMP2TRG           RTC_TAFCR_TAMP2TRG_Msk
4853 #define RTC_TAFCR_TAMP2E_Pos         (3U)
4854 #define RTC_TAFCR_TAMP2E_Msk         (0x1UL << RTC_TAFCR_TAMP2E_Pos)            /*!< 0x00000008 */
4855 #define RTC_TAFCR_TAMP2E             RTC_TAFCR_TAMP2E_Msk
4856 #define RTC_TAFCR_TAMPIE_Pos         (2U)
4857 #define RTC_TAFCR_TAMPIE_Msk         (0x1UL << RTC_TAFCR_TAMPIE_Pos)            /*!< 0x00000004 */
4858 #define RTC_TAFCR_TAMPIE             RTC_TAFCR_TAMPIE_Msk
4859 #define RTC_TAFCR_TAMP1TRG_Pos       (1U)
4860 #define RTC_TAFCR_TAMP1TRG_Msk       (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)          /*!< 0x00000002 */
4861 #define RTC_TAFCR_TAMP1TRG           RTC_TAFCR_TAMP1TRG_Msk
4862 #define RTC_TAFCR_TAMP1E_Pos         (0U)
4863 #define RTC_TAFCR_TAMP1E_Msk         (0x1UL << RTC_TAFCR_TAMP1E_Pos)            /*!< 0x00000001 */
4864 #define RTC_TAFCR_TAMP1E             RTC_TAFCR_TAMP1E_Msk
4865 
4866 /* Reference defines */
4867 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
4868 
4869 /********************  Bits definition for RTC_ALRMASSR register  ************/
4870 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
4871 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
4872 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
4873 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x01000000 */
4874 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x02000000 */
4875 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x04000000 */
4876 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x08000000 */
4877 #define RTC_ALRMASSR_SS_Pos          (0U)
4878 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
4879 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
4880 
4881 /********************  Bits definition for RTC_BKP0R register  ***************/
4882 #define RTC_BKP0R_Pos                (0U)
4883 #define RTC_BKP0R_Msk                (0xFFFFFFFFUL << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
4884 #define RTC_BKP0R                    RTC_BKP0R_Msk
4885 
4886 /********************  Bits definition for RTC_BKP1R register  ***************/
4887 #define RTC_BKP1R_Pos                (0U)
4888 #define RTC_BKP1R_Msk                (0xFFFFFFFFUL << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
4889 #define RTC_BKP1R                    RTC_BKP1R_Msk
4890 
4891 /********************  Bits definition for RTC_BKP2R register  ***************/
4892 #define RTC_BKP2R_Pos                (0U)
4893 #define RTC_BKP2R_Msk                (0xFFFFFFFFUL << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
4894 #define RTC_BKP2R                    RTC_BKP2R_Msk
4895 
4896 /********************  Bits definition for RTC_BKP3R register  ***************/
4897 #define RTC_BKP3R_Pos                (0U)
4898 #define RTC_BKP3R_Msk                (0xFFFFFFFFUL << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
4899 #define RTC_BKP3R                    RTC_BKP3R_Msk
4900 
4901 /********************  Bits definition for RTC_BKP4R register  ***************/
4902 #define RTC_BKP4R_Pos                (0U)
4903 #define RTC_BKP4R_Msk                (0xFFFFFFFFUL << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
4904 #define RTC_BKP4R                    RTC_BKP4R_Msk
4905 
4906 /******************** Number of backup registers ******************************/
4907 #define RTC_BKP_NUMBER                       0x00000005U
4908 
4909 /*****************************************************************************/
4910 /*                                                                           */
4911 /*                        Serial Peripheral Interface (SPI)                  */
4912 /*                                                                           */
4913 /*****************************************************************************/
4914 
4915 /*
4916  * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
4917  */
4918 #define SPI_I2S_SUPPORT                       /*!< I2S support */
4919 
4920 /*******************  Bit definition for SPI_CR1 register  *******************/
4921 #define SPI_CR1_CPHA_Pos            (0U)
4922 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
4923 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
4924 #define SPI_CR1_CPOL_Pos            (1U)
4925 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
4926 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
4927 #define SPI_CR1_MSTR_Pos            (2U)
4928 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
4929 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
4930 #define SPI_CR1_BR_Pos              (3U)
4931 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
4932 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
4933 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
4934 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
4935 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
4936 #define SPI_CR1_SPE_Pos             (6U)
4937 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
4938 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
4939 #define SPI_CR1_LSBFIRST_Pos        (7U)
4940 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
4941 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
4942 #define SPI_CR1_SSI_Pos             (8U)
4943 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
4944 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
4945 #define SPI_CR1_SSM_Pos             (9U)
4946 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
4947 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
4948 #define SPI_CR1_RXONLY_Pos          (10U)
4949 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
4950 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
4951 #define SPI_CR1_CRCL_Pos            (11U)
4952 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
4953 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
4954 #define SPI_CR1_CRCNEXT_Pos         (12U)
4955 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
4956 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
4957 #define SPI_CR1_CRCEN_Pos           (13U)
4958 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
4959 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
4960 #define SPI_CR1_BIDIOE_Pos          (14U)
4961 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
4962 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
4963 #define SPI_CR1_BIDIMODE_Pos        (15U)
4964 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
4965 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
4966 
4967 /*******************  Bit definition for SPI_CR2 register  *******************/
4968 #define SPI_CR2_RXDMAEN_Pos         (0U)
4969 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
4970 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
4971 #define SPI_CR2_TXDMAEN_Pos         (1U)
4972 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
4973 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
4974 #define SPI_CR2_SSOE_Pos            (2U)
4975 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
4976 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
4977 #define SPI_CR2_NSSP_Pos            (3U)
4978 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
4979 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
4980 #define SPI_CR2_FRF_Pos             (4U)
4981 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
4982 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
4983 #define SPI_CR2_ERRIE_Pos           (5U)
4984 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
4985 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
4986 #define SPI_CR2_RXNEIE_Pos          (6U)
4987 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
4988 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
4989 #define SPI_CR2_TXEIE_Pos           (7U)
4990 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
4991 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
4992 #define SPI_CR2_DS_Pos              (8U)
4993 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
4994 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
4995 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
4996 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
4997 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
4998 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
4999 #define SPI_CR2_FRXTH_Pos           (12U)
5000 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
5001 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
5002 #define SPI_CR2_LDMARX_Pos          (13U)
5003 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
5004 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
5005 #define SPI_CR2_LDMATX_Pos          (14U)
5006 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
5007 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
5008 
5009 /********************  Bit definition for SPI_SR register  *******************/
5010 #define SPI_SR_RXNE_Pos             (0U)
5011 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
5012 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
5013 #define SPI_SR_TXE_Pos              (1U)
5014 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
5015 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
5016 #define SPI_SR_CHSIDE_Pos           (2U)
5017 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
5018 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
5019 #define SPI_SR_UDR_Pos              (3U)
5020 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
5021 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
5022 #define SPI_SR_CRCERR_Pos           (4U)
5023 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
5024 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
5025 #define SPI_SR_MODF_Pos             (5U)
5026 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
5027 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
5028 #define SPI_SR_OVR_Pos              (6U)
5029 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
5030 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
5031 #define SPI_SR_BSY_Pos              (7U)
5032 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
5033 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
5034 #define SPI_SR_FRE_Pos              (8U)
5035 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
5036 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
5037 #define SPI_SR_FRLVL_Pos            (9U)
5038 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
5039 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
5040 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
5041 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
5042 #define SPI_SR_FTLVL_Pos            (11U)
5043 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
5044 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
5045 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
5046 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
5047 
5048 /********************  Bit definition for SPI_DR register  *******************/
5049 #define SPI_DR_DR_Pos               (0U)
5050 #define SPI_DR_DR_Msk               (0xFFFFFFFFUL << SPI_DR_DR_Pos)             /*!< 0xFFFFFFFF */
5051 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
5052 
5053 /*******************  Bit definition for SPI_CRCPR register  *****************/
5054 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
5055 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos)     /*!< 0xFFFFFFFF */
5056 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
5057 
5058 /******************  Bit definition for SPI_RXCRCR register  *****************/
5059 #define SPI_RXCRCR_RXCRC_Pos        (0U)
5060 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos)      /*!< 0xFFFFFFFF */
5061 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
5062 
5063 /******************  Bit definition for SPI_TXCRCR register  *****************/
5064 #define SPI_TXCRCR_TXCRC_Pos        (0U)
5065 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos)      /*!< 0xFFFFFFFF */
5066 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
5067 
5068 /******************  Bit definition for SPI_I2SCFGR register  ****************/
5069 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
5070 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
5071 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
5072 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
5073 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
5074 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
5075 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
5076 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
5077 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
5078 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
5079 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
5080 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
5081 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
5082 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
5083 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
5084 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
5085 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
5086 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
5087 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
5088 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
5089 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
5090 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5091 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
5092 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
5093 #define SPI_I2SCFGR_I2SE_Pos        (10U)
5094 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
5095 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
5096 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
5097 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
5098 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
5099 
5100 /******************  Bit definition for SPI_I2SPR register  ******************/
5101 #define SPI_I2SPR_I2SDIV_Pos        (0U)
5102 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
5103 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
5104 #define SPI_I2SPR_ODD_Pos           (8U)
5105 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
5106 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
5107 #define SPI_I2SPR_MCKOE_Pos         (9U)
5108 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
5109 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
5110 
5111 /*****************************************************************************/
5112 /*                                                                           */
5113 /*                       System Configuration (SYSCFG)                       */
5114 /*                                                                           */
5115 /*****************************************************************************/
5116 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
5117 #define SYSCFG_CFGR1_MEM_MODE_Pos            (0U)
5118 #define SYSCFG_CFGR1_MEM_MODE_Msk            (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
5119 #define SYSCFG_CFGR1_MEM_MODE                SYSCFG_CFGR1_MEM_MODE_Msk           /*!< SYSCFG_Memory Remap Config */
5120 #define SYSCFG_CFGR1_MEM_MODE_0              (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
5121 #define SYSCFG_CFGR1_MEM_MODE_1              (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
5122 
5123 #define SYSCFG_CFGR1_DMA_RMP_Pos             (8U)
5124 #define SYSCFG_CFGR1_DMA_RMP_Msk             (0x7F007FUL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x7F007F00 */
5125 #define SYSCFG_CFGR1_DMA_RMP                 SYSCFG_CFGR1_DMA_RMP_Msk          /*!< DMA remap mask */
5126 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos         (8U)
5127 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk         (0x1UL << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
5128 #define SYSCFG_CFGR1_ADC_DMA_RMP             SYSCFG_CFGR1_ADC_DMA_RMP_Msk      /*!< ADC DMA remap */
5129 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos    (9U)
5130 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk    (0x1UL << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
5131 #define SYSCFG_CFGR1_USART1TX_DMA_RMP        SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
5132 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos    (10U)
5133 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk    (0x1UL << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
5134 #define SYSCFG_CFGR1_USART1RX_DMA_RMP        SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
5135 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos       (11U)
5136 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk       (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
5137 #define SYSCFG_CFGR1_TIM16_DMA_RMP           SYSCFG_CFGR1_TIM16_DMA_RMP_Msk    /*!< Timer 16 DMA remap */
5138 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos       (12U)
5139 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk       (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
5140 #define SYSCFG_CFGR1_TIM17_DMA_RMP           SYSCFG_CFGR1_TIM17_DMA_RMP_Msk    /*!< Timer 17 DMA remap */
5141 #define SYSCFG_CFGR1_TIM16_DMA_RMP2_Pos      (13U)
5142 #define SYSCFG_CFGR1_TIM16_DMA_RMP2_Msk      (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP2_Pos) /*!< 0x00002000 */
5143 #define SYSCFG_CFGR1_TIM16_DMA_RMP2          SYSCFG_CFGR1_TIM16_DMA_RMP2_Msk   /*!< Timer 16 DMA remap 2  */
5144 #define SYSCFG_CFGR1_TIM17_DMA_RMP2_Pos      (14U)
5145 #define SYSCFG_CFGR1_TIM17_DMA_RMP2_Msk      (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP2_Pos) /*!< 0x00004000 */
5146 #define SYSCFG_CFGR1_TIM17_DMA_RMP2          SYSCFG_CFGR1_TIM17_DMA_RMP2_Msk   /*!< Timer 17 DMA remap 2  */
5147 #define SYSCFG_CFGR1_SPI2_DMA_RMP_Pos        (24U)
5148 #define SYSCFG_CFGR1_SPI2_DMA_RMP_Msk        (0x1UL << SYSCFG_CFGR1_SPI2_DMA_RMP_Pos) /*!< 0x01000000 */
5149 #define SYSCFG_CFGR1_SPI2_DMA_RMP            SYSCFG_CFGR1_SPI2_DMA_RMP_Msk     /*!< SPI2 DMA remap  */
5150 #define SYSCFG_CFGR1_USART2_DMA_RMP_Pos      (25U)
5151 #define SYSCFG_CFGR1_USART2_DMA_RMP_Msk      (0x1UL << SYSCFG_CFGR1_USART2_DMA_RMP_Pos) /*!< 0x02000000 */
5152 #define SYSCFG_CFGR1_USART2_DMA_RMP          SYSCFG_CFGR1_USART2_DMA_RMP_Msk   /*!< USART2 DMA remap  */
5153 #define SYSCFG_CFGR1_USART3_DMA_RMP_Pos      (26U)
5154 #define SYSCFG_CFGR1_USART3_DMA_RMP_Msk      (0x1UL << SYSCFG_CFGR1_USART3_DMA_RMP_Pos) /*!< 0x04000000 */
5155 #define SYSCFG_CFGR1_USART3_DMA_RMP          SYSCFG_CFGR1_USART3_DMA_RMP_Msk   /*!< USART3 DMA remap  */
5156 #define SYSCFG_CFGR1_I2C1_DMA_RMP_Pos        (27U)
5157 #define SYSCFG_CFGR1_I2C1_DMA_RMP_Msk        (0x1UL << SYSCFG_CFGR1_I2C1_DMA_RMP_Pos) /*!< 0x08000000 */
5158 #define SYSCFG_CFGR1_I2C1_DMA_RMP            SYSCFG_CFGR1_I2C1_DMA_RMP_Msk     /*!< I2C1 DMA remap  */
5159 #define SYSCFG_CFGR1_TIM1_DMA_RMP_Pos        (28U)
5160 #define SYSCFG_CFGR1_TIM1_DMA_RMP_Msk        (0x1UL << SYSCFG_CFGR1_TIM1_DMA_RMP_Pos) /*!< 0x10000000 */
5161 #define SYSCFG_CFGR1_TIM1_DMA_RMP            SYSCFG_CFGR1_TIM1_DMA_RMP_Msk     /*!< TIM1 DMA remap  */
5162 #define SYSCFG_CFGR1_TIM2_DMA_RMP_Pos        (29U)
5163 #define SYSCFG_CFGR1_TIM2_DMA_RMP_Msk        (0x1UL << SYSCFG_CFGR1_TIM2_DMA_RMP_Pos) /*!< 0x20000000 */
5164 #define SYSCFG_CFGR1_TIM2_DMA_RMP            SYSCFG_CFGR1_TIM2_DMA_RMP_Msk     /*!< TIM2 DMA remap  */
5165 #define SYSCFG_CFGR1_TIM3_DMA_RMP_Pos        (30U)
5166 #define SYSCFG_CFGR1_TIM3_DMA_RMP_Msk        (0x1UL << SYSCFG_CFGR1_TIM3_DMA_RMP_Pos) /*!< 0x40000000 */
5167 #define SYSCFG_CFGR1_TIM3_DMA_RMP            SYSCFG_CFGR1_TIM3_DMA_RMP_Msk     /*!< TIM3 DMA remap  */
5168 
5169 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos         (16U)
5170 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
5171 #define SYSCFG_CFGR1_I2C_FMP_PB6             SYSCFG_CFGR1_I2C_FMP_PB6_Msk      /*!< I2C PB6 Fast mode plus */
5172 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos         (17U)
5173 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
5174 #define SYSCFG_CFGR1_I2C_FMP_PB7             SYSCFG_CFGR1_I2C_FMP_PB7_Msk      /*!< I2C PB7 Fast mode plus */
5175 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos         (18U)
5176 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
5177 #define SYSCFG_CFGR1_I2C_FMP_PB8             SYSCFG_CFGR1_I2C_FMP_PB8_Msk      /*!< I2C PB8 Fast mode plus */
5178 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos         (19U)
5179 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
5180 #define SYSCFG_CFGR1_I2C_FMP_PB9             SYSCFG_CFGR1_I2C_FMP_PB9_Msk      /*!< I2C PB9 Fast mode plus */
5181 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos        (20U)
5182 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk        (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
5183 #define SYSCFG_CFGR1_I2C_FMP_I2C1            SYSCFG_CFGR1_I2C_FMP_I2C1_Msk     /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */
5184 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Pos        (21U)
5185 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Msk        (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C2_Pos) /*!< 0x00200000 */
5186 #define SYSCFG_CFGR1_I2C_FMP_I2C2            SYSCFG_CFGR1_I2C_FMP_I2C2_Msk     /*!< Enable I2C2 Fast mode plus  */
5187 
5188 /*****************  Bit definition for SYSCFG_EXTICR1 register  **************/
5189 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
5190 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
5191 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!< EXTI 0 configuration */
5192 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
5193 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
5194 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!< EXTI 1 configuration */
5195 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
5196 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
5197 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!< EXTI 2 configuration */
5198 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
5199 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
5200 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!< EXTI 3 configuration */
5201 
5202 /**
5203   * @brief  EXTI0 configuration
5204   */
5205 #define SYSCFG_EXTICR1_EXTI0_PA              (0x00000000U)                     /*!< PA[0] pin */
5206 #define SYSCFG_EXTICR1_EXTI0_PB              (0x00000001U)                     /*!< PB[0] pin */
5207 #define SYSCFG_EXTICR1_EXTI0_PC              (0x00000002U)                     /*!< PC[0] pin */
5208 #define SYSCFG_EXTICR1_EXTI0_PD              (0x00000003U)                     /*!< PD[0] pin */
5209 #define SYSCFG_EXTICR1_EXTI0_PE              (0x00000004U)                     /*!< PE[0] pin */
5210 #define SYSCFG_EXTICR1_EXTI0_PF              (0x00000005U)                     /*!< PF[0] pin */
5211 
5212 /**
5213   * @brief  EXTI1 configuration
5214   */
5215 #define SYSCFG_EXTICR1_EXTI1_PA              (0x00000000U)                     /*!< PA[1] pin */
5216 #define SYSCFG_EXTICR1_EXTI1_PB              (0x00000010U)                     /*!< PB[1] pin */
5217 #define SYSCFG_EXTICR1_EXTI1_PC              (0x00000020U)                     /*!< PC[1] pin */
5218 #define SYSCFG_EXTICR1_EXTI1_PD              (0x00000030U)                     /*!< PD[1] pin */
5219 #define SYSCFG_EXTICR1_EXTI1_PE              (0x00000040U)                     /*!< PE[1] pin */
5220 #define SYSCFG_EXTICR1_EXTI1_PF              (0x00000050U)                     /*!< PF[1] pin */
5221 
5222 /**
5223   * @brief  EXTI2 configuration
5224   */
5225 #define SYSCFG_EXTICR1_EXTI2_PA              (0x00000000U)                     /*!< PA[2] pin */
5226 #define SYSCFG_EXTICR1_EXTI2_PB              (0x00000100U)                     /*!< PB[2] pin */
5227 #define SYSCFG_EXTICR1_EXTI2_PC              (0x00000200U)                     /*!< PC[2] pin */
5228 #define SYSCFG_EXTICR1_EXTI2_PD              (0x00000300U)                     /*!< PD[2] pin */
5229 #define SYSCFG_EXTICR1_EXTI2_PE              (0x00000400U)                     /*!< PE[2] pin */
5230 #define SYSCFG_EXTICR1_EXTI2_PF              (0x00000500U)                     /*!< PF[2] pin */
5231 
5232 /**
5233   * @brief  EXTI3 configuration
5234   */
5235 #define SYSCFG_EXTICR1_EXTI3_PA              (0x00000000U)                     /*!< PA[3] pin */
5236 #define SYSCFG_EXTICR1_EXTI3_PB              (0x00001000U)                     /*!< PB[3] pin */
5237 #define SYSCFG_EXTICR1_EXTI3_PC              (0x00002000U)                     /*!< PC[3] pin */
5238 #define SYSCFG_EXTICR1_EXTI3_PD              (0x00003000U)                     /*!< PD[3] pin */
5239 #define SYSCFG_EXTICR1_EXTI3_PE              (0x00004000U)                     /*!< PE[3] pin */
5240 #define SYSCFG_EXTICR1_EXTI3_PF              (0x00005000U)                     /*!< PF[3] pin */
5241 
5242 /*****************  Bit definition for SYSCFG_EXTICR2 register  **************/
5243 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
5244 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
5245 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!< EXTI 4 configuration */
5246 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
5247 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
5248 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!< EXTI 5 configuration */
5249 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
5250 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
5251 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!< EXTI 6 configuration */
5252 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
5253 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
5254 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!< EXTI 7 configuration */
5255 
5256 /**
5257   * @brief  EXTI4 configuration
5258   */
5259 #define SYSCFG_EXTICR2_EXTI4_PA              (0x00000000U)                     /*!< PA[4] pin */
5260 #define SYSCFG_EXTICR2_EXTI4_PB              (0x00000001U)                     /*!< PB[4] pin */
5261 #define SYSCFG_EXTICR2_EXTI4_PC              (0x00000002U)                     /*!< PC[4] pin */
5262 #define SYSCFG_EXTICR2_EXTI4_PD              (0x00000003U)                     /*!< PD[4] pin */
5263 #define SYSCFG_EXTICR2_EXTI4_PE              (0x00000004U)                     /*!< PE[4] pin */
5264 #define SYSCFG_EXTICR2_EXTI4_PF              (0x00000005U)                     /*!< PF[4] pin */
5265 
5266 /**
5267   * @brief  EXTI5 configuration
5268   */
5269 #define SYSCFG_EXTICR2_EXTI5_PA              (0x00000000U)                     /*!< PA[5] pin */
5270 #define SYSCFG_EXTICR2_EXTI5_PB              (0x00000010U)                     /*!< PB[5] pin */
5271 #define SYSCFG_EXTICR2_EXTI5_PC              (0x00000020U)                     /*!< PC[5] pin */
5272 #define SYSCFG_EXTICR2_EXTI5_PD              (0x00000030U)                     /*!< PD[5] pin */
5273 #define SYSCFG_EXTICR2_EXTI5_PE              (0x00000040U)                     /*!< PE[5] pin */
5274 #define SYSCFG_EXTICR2_EXTI5_PF              (0x00000050U)                     /*!< PF[5] pin */
5275 
5276 /**
5277   * @brief  EXTI6 configuration
5278   */
5279 #define SYSCFG_EXTICR2_EXTI6_PA              (0x00000000U)                     /*!< PA[6] pin */
5280 #define SYSCFG_EXTICR2_EXTI6_PB              (0x00000100U)                     /*!< PB[6] pin */
5281 #define SYSCFG_EXTICR2_EXTI6_PC              (0x00000200U)                     /*!< PC[6] pin */
5282 #define SYSCFG_EXTICR2_EXTI6_PD              (0x00000300U)                     /*!< PD[6] pin */
5283 #define SYSCFG_EXTICR2_EXTI6_PE              (0x00000400U)                     /*!< PE[6] pin */
5284 #define SYSCFG_EXTICR2_EXTI6_PF              (0x00000500U)                     /*!< PF[6] pin */
5285 
5286 /**
5287   * @brief  EXTI7 configuration
5288   */
5289 #define SYSCFG_EXTICR2_EXTI7_PA              (0x00000000U)                     /*!< PA[7] pin */
5290 #define SYSCFG_EXTICR2_EXTI7_PB              (0x00001000U)                     /*!< PB[7] pin */
5291 #define SYSCFG_EXTICR2_EXTI7_PC              (0x00002000U)                     /*!< PC[7] pin */
5292 #define SYSCFG_EXTICR2_EXTI7_PD              (0x00003000U)                     /*!< PD[7] pin */
5293 #define SYSCFG_EXTICR2_EXTI7_PE              (0x00004000U)                     /*!< PE[7] pin */
5294 #define SYSCFG_EXTICR2_EXTI7_PF              (0x00005000U)                     /*!< PF[7] pin */
5295 
5296 /*****************  Bit definition for SYSCFG_EXTICR3 register  **************/
5297 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
5298 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
5299 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!< EXTI 8 configuration */
5300 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
5301 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
5302 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!< EXTI 9 configuration */
5303 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
5304 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
5305 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!< EXTI 10 configuration */
5306 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
5307 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
5308 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!< EXTI 11 configuration */
5309 
5310 /**
5311   * @brief  EXTI8 configuration
5312   */
5313 #define SYSCFG_EXTICR3_EXTI8_PA              (0x00000000U)                     /*!< PA[8] pin */
5314 #define SYSCFG_EXTICR3_EXTI8_PB              (0x00000001U)                     /*!< PB[8] pin */
5315 #define SYSCFG_EXTICR3_EXTI8_PC              (0x00000002U)                     /*!< PC[8] pin */
5316 #define SYSCFG_EXTICR3_EXTI8_PD              (0x00000003U)                     /*!< PD[8] pin */
5317 #define SYSCFG_EXTICR3_EXTI8_PE              (0x00000004U)                     /*!< PE[8] pin */
5318 
5319 
5320 /**
5321   * @brief  EXTI9 configuration
5322   */
5323 #define SYSCFG_EXTICR3_EXTI9_PA              (0x00000000U)                     /*!< PA[9] pin */
5324 #define SYSCFG_EXTICR3_EXTI9_PB              (0x00000010U)                     /*!< PB[9] pin */
5325 #define SYSCFG_EXTICR3_EXTI9_PC              (0x00000020U)                     /*!< PC[9] pin */
5326 #define SYSCFG_EXTICR3_EXTI9_PD              (0x00000030U)                     /*!< PD[9] pin */
5327 #define SYSCFG_EXTICR3_EXTI9_PE              (0x00000040U)                     /*!< PE[9] pin */
5328 #define SYSCFG_EXTICR3_EXTI9_PF              (0x00000050U)                     /*!< PF[9] pin */
5329 
5330 /**
5331   * @brief  EXTI10 configuration
5332   */
5333 #define SYSCFG_EXTICR3_EXTI10_PA             (0x00000000U)                     /*!< PA[10] pin */
5334 #define SYSCFG_EXTICR3_EXTI10_PB             (0x00000100U)                     /*!< PB[10] pin */
5335 #define SYSCFG_EXTICR3_EXTI10_PC             (0x00000200U)                     /*!< PC[10] pin */
5336 #define SYSCFG_EXTICR3_EXTI10_PD             (0x00000300U)                     /*!< PD[10] pin */
5337 #define SYSCFG_EXTICR3_EXTI10_PE             (0x00000400U)                     /*!< PE[10] pin */
5338 #define SYSCFG_EXTICR3_EXTI10_PF             (0x00000500U)                     /*!< PF[10] pin */
5339 
5340 /**
5341   * @brief  EXTI11 configuration
5342   */
5343 #define SYSCFG_EXTICR3_EXTI11_PA             (0x00000000U)                     /*!< PA[11] pin */
5344 #define SYSCFG_EXTICR3_EXTI11_PB             (0x00001000U)                     /*!< PB[11] pin */
5345 #define SYSCFG_EXTICR3_EXTI11_PC             (0x00002000U)                     /*!< PC[11] pin */
5346 #define SYSCFG_EXTICR3_EXTI11_PD             (0x00003000U)                     /*!< PD[11] pin */
5347 #define SYSCFG_EXTICR3_EXTI11_PE             (0x00004000U)                     /*!< PE[11] pin */
5348 
5349 /*****************  Bit definition for SYSCFG_EXTICR4 register  **************/
5350 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
5351 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
5352 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!< EXTI 12 configuration */
5353 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
5354 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
5355 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!< EXTI 13 configuration */
5356 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
5357 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
5358 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!< EXTI 14 configuration */
5359 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
5360 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
5361 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!< EXTI 15 configuration */
5362 
5363 /**
5364   * @brief  EXTI12 configuration
5365   */
5366 #define SYSCFG_EXTICR4_EXTI12_PA             (0x00000000U)                     /*!< PA[12] pin */
5367 #define SYSCFG_EXTICR4_EXTI12_PB             (0x00000001U)                     /*!< PB[12] pin */
5368 #define SYSCFG_EXTICR4_EXTI12_PC             (0x00000002U)                     /*!< PC[12] pin */
5369 #define SYSCFG_EXTICR4_EXTI12_PD             (0x00000003U)                     /*!< PD[12] pin */
5370 #define SYSCFG_EXTICR4_EXTI12_PE             (0x00000004U)                     /*!< PE[12] pin */
5371 
5372 /**
5373   * @brief  EXTI13 configuration
5374   */
5375 #define SYSCFG_EXTICR4_EXTI13_PA             (0x00000000U)                     /*!< PA[13] pin */
5376 #define SYSCFG_EXTICR4_EXTI13_PB             (0x00000010U)                     /*!< PB[13] pin */
5377 #define SYSCFG_EXTICR4_EXTI13_PC             (0x00000020U)                     /*!< PC[13] pin */
5378 #define SYSCFG_EXTICR4_EXTI13_PD             (0x00000030U)                     /*!< PD[13] pin */
5379 #define SYSCFG_EXTICR4_EXTI13_PE             (0x00000040U)                     /*!< PE[13] pin */
5380 
5381 /**
5382   * @brief  EXTI14 configuration
5383   */
5384 #define SYSCFG_EXTICR4_EXTI14_PA             (0x00000000U)                     /*!< PA[14] pin */
5385 #define SYSCFG_EXTICR4_EXTI14_PB             (0x00000100U)                     /*!< PB[14] pin */
5386 #define SYSCFG_EXTICR4_EXTI14_PC             (0x00000200U)                     /*!< PC[14] pin */
5387 #define SYSCFG_EXTICR4_EXTI14_PD             (0x00000300U)                     /*!< PD[14] pin */
5388 #define SYSCFG_EXTICR4_EXTI14_PE             (0x00000400U)                     /*!< PE[14] pin */
5389 
5390 /**
5391   * @brief  EXTI15 configuration
5392   */
5393 #define SYSCFG_EXTICR4_EXTI15_PA             (0x00000000U)                     /*!< PA[15] pin */
5394 #define SYSCFG_EXTICR4_EXTI15_PB             (0x00001000U)                     /*!< PB[15] pin */
5395 #define SYSCFG_EXTICR4_EXTI15_PC             (0x00002000U)                     /*!< PC[15] pin */
5396 #define SYSCFG_EXTICR4_EXTI15_PD             (0x00003000U)                     /*!< PD[15] pin */
5397 #define SYSCFG_EXTICR4_EXTI15_PE             (0x00004000U)                     /*!< PE[15] pin */
5398 
5399 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
5400 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)
5401 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
5402 #define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
5403 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos    (1U)
5404 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk    (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
5405 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK        SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
5406 #define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)
5407 #define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
5408 #define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
5409 #define SYSCFG_CFGR2_SRAM_PEF_Pos            (8U)
5410 #define SYSCFG_CFGR2_SRAM_PEF_Msk            (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
5411 #define SYSCFG_CFGR2_SRAM_PEF                SYSCFG_CFGR2_SRAM_PEF_Msk         /*!< SRAM Parity error flag */
5412 #define SYSCFG_CFGR2_SRAM_PE                 SYSCFG_CFGR2_SRAM_PEF  /*!< SRAM Parity error flag (define maintained for legacy purpose) */
5413 
5414 /*****************************************************************************/
5415 /*                                                                           */
5416 /*                               Timers (TIM)                                */
5417 /*                                                                           */
5418 /*****************************************************************************/
5419 /*******************  Bit definition for TIM_CR1 register  *******************/
5420 #define TIM_CR1_CEN_Pos           (0U)
5421 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
5422 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
5423 #define TIM_CR1_UDIS_Pos          (1U)
5424 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
5425 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
5426 #define TIM_CR1_URS_Pos           (2U)
5427 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
5428 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
5429 #define TIM_CR1_OPM_Pos           (3U)
5430 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
5431 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
5432 #define TIM_CR1_DIR_Pos           (4U)
5433 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
5434 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
5435 
5436 #define TIM_CR1_CMS_Pos           (5U)
5437 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
5438 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
5439 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
5440 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
5441 
5442 #define TIM_CR1_ARPE_Pos          (7U)
5443 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
5444 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
5445 
5446 #define TIM_CR1_CKD_Pos           (8U)
5447 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
5448 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
5449 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
5450 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
5451 
5452 /*******************  Bit definition for TIM_CR2 register  *******************/
5453 #define TIM_CR2_CCPC_Pos          (0U)
5454 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
5455 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
5456 #define TIM_CR2_CCUS_Pos          (2U)
5457 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
5458 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
5459 #define TIM_CR2_CCDS_Pos          (3U)
5460 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
5461 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
5462 
5463 #define TIM_CR2_MMS_Pos           (4U)
5464 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
5465 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
5466 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
5467 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
5468 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
5469 
5470 #define TIM_CR2_TI1S_Pos          (7U)
5471 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
5472 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
5473 #define TIM_CR2_OIS1_Pos          (8U)
5474 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
5475 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
5476 #define TIM_CR2_OIS1N_Pos         (9U)
5477 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
5478 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
5479 #define TIM_CR2_OIS2_Pos          (10U)
5480 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
5481 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
5482 #define TIM_CR2_OIS2N_Pos         (11U)
5483 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
5484 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
5485 #define TIM_CR2_OIS3_Pos          (12U)
5486 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
5487 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
5488 #define TIM_CR2_OIS3N_Pos         (13U)
5489 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
5490 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
5491 #define TIM_CR2_OIS4_Pos          (14U)
5492 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
5493 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
5494 
5495 /*******************  Bit definition for TIM_SMCR register  ******************/
5496 #define TIM_SMCR_SMS_Pos          (0U)
5497 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
5498 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
5499 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
5500 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
5501 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
5502 
5503 #define TIM_SMCR_OCCS_Pos         (3U)
5504 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
5505 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
5506 
5507 #define TIM_SMCR_TS_Pos           (4U)
5508 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
5509 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
5510 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
5511 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
5512 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
5513 
5514 #define TIM_SMCR_MSM_Pos          (7U)
5515 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
5516 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
5517 
5518 #define TIM_SMCR_ETF_Pos          (8U)
5519 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
5520 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
5521 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
5522 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
5523 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
5524 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
5525 
5526 #define TIM_SMCR_ETPS_Pos         (12U)
5527 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
5528 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
5529 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
5530 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
5531 
5532 #define TIM_SMCR_ECE_Pos          (14U)
5533 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
5534 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
5535 #define TIM_SMCR_ETP_Pos          (15U)
5536 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
5537 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
5538 
5539 /*******************  Bit definition for TIM_DIER register  ******************/
5540 #define TIM_DIER_UIE_Pos          (0U)
5541 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
5542 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
5543 #define TIM_DIER_CC1IE_Pos        (1U)
5544 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
5545 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
5546 #define TIM_DIER_CC2IE_Pos        (2U)
5547 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
5548 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
5549 #define TIM_DIER_CC3IE_Pos        (3U)
5550 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
5551 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
5552 #define TIM_DIER_CC4IE_Pos        (4U)
5553 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
5554 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
5555 #define TIM_DIER_COMIE_Pos        (5U)
5556 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
5557 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
5558 #define TIM_DIER_TIE_Pos          (6U)
5559 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
5560 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
5561 #define TIM_DIER_BIE_Pos          (7U)
5562 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
5563 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
5564 #define TIM_DIER_UDE_Pos          (8U)
5565 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
5566 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
5567 #define TIM_DIER_CC1DE_Pos        (9U)
5568 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
5569 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
5570 #define TIM_DIER_CC2DE_Pos        (10U)
5571 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
5572 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
5573 #define TIM_DIER_CC3DE_Pos        (11U)
5574 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
5575 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
5576 #define TIM_DIER_CC4DE_Pos        (12U)
5577 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
5578 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
5579 #define TIM_DIER_COMDE_Pos        (13U)
5580 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
5581 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
5582 #define TIM_DIER_TDE_Pos          (14U)
5583 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
5584 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
5585 
5586 /********************  Bit definition for TIM_SR register  *******************/
5587 #define TIM_SR_UIF_Pos            (0U)
5588 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
5589 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
5590 #define TIM_SR_CC1IF_Pos          (1U)
5591 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
5592 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
5593 #define TIM_SR_CC2IF_Pos          (2U)
5594 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
5595 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
5596 #define TIM_SR_CC3IF_Pos          (3U)
5597 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
5598 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
5599 #define TIM_SR_CC4IF_Pos          (4U)
5600 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
5601 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
5602 #define TIM_SR_COMIF_Pos          (5U)
5603 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
5604 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
5605 #define TIM_SR_TIF_Pos            (6U)
5606 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
5607 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
5608 #define TIM_SR_BIF_Pos            (7U)
5609 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
5610 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
5611 #define TIM_SR_CC1OF_Pos          (9U)
5612 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
5613 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
5614 #define TIM_SR_CC2OF_Pos          (10U)
5615 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
5616 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
5617 #define TIM_SR_CC3OF_Pos          (11U)
5618 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
5619 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
5620 #define TIM_SR_CC4OF_Pos          (12U)
5621 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
5622 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
5623 
5624 /*******************  Bit definition for TIM_EGR register  *******************/
5625 #define TIM_EGR_UG_Pos            (0U)
5626 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
5627 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
5628 #define TIM_EGR_CC1G_Pos          (1U)
5629 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
5630 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
5631 #define TIM_EGR_CC2G_Pos          (2U)
5632 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
5633 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
5634 #define TIM_EGR_CC3G_Pos          (3U)
5635 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
5636 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
5637 #define TIM_EGR_CC4G_Pos          (4U)
5638 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
5639 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
5640 #define TIM_EGR_COMG_Pos          (5U)
5641 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
5642 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
5643 #define TIM_EGR_TG_Pos            (6U)
5644 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
5645 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
5646 #define TIM_EGR_BG_Pos            (7U)
5647 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
5648 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
5649 
5650 /******************  Bit definition for TIM_CCMR1 register  ******************/
5651 #define TIM_CCMR1_CC1S_Pos        (0U)
5652 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
5653 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5654 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
5655 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
5656 
5657 #define TIM_CCMR1_OC1FE_Pos       (2U)
5658 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
5659 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
5660 #define TIM_CCMR1_OC1PE_Pos       (3U)
5661 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
5662 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
5663 
5664 #define TIM_CCMR1_OC1M_Pos        (4U)
5665 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
5666 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5667 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
5668 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
5669 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
5670 
5671 #define TIM_CCMR1_OC1CE_Pos       (7U)
5672 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
5673 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
5674 
5675 #define TIM_CCMR1_CC2S_Pos        (8U)
5676 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
5677 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5678 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
5679 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
5680 
5681 #define TIM_CCMR1_OC2FE_Pos       (10U)
5682 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
5683 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
5684 #define TIM_CCMR1_OC2PE_Pos       (11U)
5685 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
5686 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
5687 
5688 #define TIM_CCMR1_OC2M_Pos        (12U)
5689 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
5690 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5691 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
5692 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
5693 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
5694 
5695 #define TIM_CCMR1_OC2CE_Pos       (15U)
5696 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
5697 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
5698 
5699 /*---------------------------------------------------------------------------*/
5700 
5701 #define TIM_CCMR1_IC1PSC_Pos      (2U)
5702 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
5703 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
5704 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
5705 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
5706 
5707 #define TIM_CCMR1_IC1F_Pos        (4U)
5708 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
5709 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5710 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
5711 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
5712 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
5713 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
5714 
5715 #define TIM_CCMR1_IC2PSC_Pos      (10U)
5716 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
5717 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5718 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
5719 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
5720 
5721 #define TIM_CCMR1_IC2F_Pos        (12U)
5722 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
5723 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5724 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
5725 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
5726 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
5727 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
5728 
5729 /******************  Bit definition for TIM_CCMR2 register  ******************/
5730 #define TIM_CCMR2_CC3S_Pos        (0U)
5731 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
5732 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5733 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
5734 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
5735 
5736 #define TIM_CCMR2_OC3FE_Pos       (2U)
5737 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
5738 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
5739 #define TIM_CCMR2_OC3PE_Pos       (3U)
5740 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
5741 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
5742 
5743 #define TIM_CCMR2_OC3M_Pos        (4U)
5744 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
5745 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5746 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
5747 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
5748 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
5749 
5750 #define TIM_CCMR2_OC3CE_Pos       (7U)
5751 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
5752 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
5753 
5754 #define TIM_CCMR2_CC4S_Pos        (8U)
5755 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
5756 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5757 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
5758 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
5759 
5760 #define TIM_CCMR2_OC4FE_Pos       (10U)
5761 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
5762 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
5763 #define TIM_CCMR2_OC4PE_Pos       (11U)
5764 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
5765 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
5766 
5767 #define TIM_CCMR2_OC4M_Pos        (12U)
5768 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
5769 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5770 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
5771 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
5772 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
5773 
5774 #define TIM_CCMR2_OC4CE_Pos       (15U)
5775 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
5776 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
5777 
5778 /*---------------------------------------------------------------------------*/
5779 
5780 #define TIM_CCMR2_IC3PSC_Pos      (2U)
5781 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
5782 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5783 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
5784 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
5785 
5786 #define TIM_CCMR2_IC3F_Pos        (4U)
5787 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
5788 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5789 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
5790 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
5791 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
5792 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
5793 
5794 #define TIM_CCMR2_IC4PSC_Pos      (10U)
5795 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
5796 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
5797 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
5798 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
5799 
5800 #define TIM_CCMR2_IC4F_Pos        (12U)
5801 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
5802 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
5803 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
5804 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
5805 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
5806 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
5807 
5808 /*******************  Bit definition for TIM_CCER register  ******************/
5809 #define TIM_CCER_CC1E_Pos         (0U)
5810 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
5811 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
5812 #define TIM_CCER_CC1P_Pos         (1U)
5813 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
5814 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
5815 #define TIM_CCER_CC1NE_Pos        (2U)
5816 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
5817 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
5818 #define TIM_CCER_CC1NP_Pos        (3U)
5819 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
5820 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
5821 #define TIM_CCER_CC2E_Pos         (4U)
5822 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
5823 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
5824 #define TIM_CCER_CC2P_Pos         (5U)
5825 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
5826 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
5827 #define TIM_CCER_CC2NE_Pos        (6U)
5828 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
5829 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
5830 #define TIM_CCER_CC2NP_Pos        (7U)
5831 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
5832 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
5833 #define TIM_CCER_CC3E_Pos         (8U)
5834 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
5835 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
5836 #define TIM_CCER_CC3P_Pos         (9U)
5837 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
5838 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
5839 #define TIM_CCER_CC3NE_Pos        (10U)
5840 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
5841 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
5842 #define TIM_CCER_CC3NP_Pos        (11U)
5843 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
5844 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
5845 #define TIM_CCER_CC4E_Pos         (12U)
5846 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
5847 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
5848 #define TIM_CCER_CC4P_Pos         (13U)
5849 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
5850 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
5851 #define TIM_CCER_CC4NP_Pos        (15U)
5852 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
5853 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
5854 
5855 /*******************  Bit definition for TIM_CNT register  *******************/
5856 #define TIM_CNT_CNT_Pos           (0U)
5857 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
5858 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
5859 
5860 /*******************  Bit definition for TIM_PSC register  *******************/
5861 #define TIM_PSC_PSC_Pos           (0U)
5862 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
5863 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
5864 
5865 /*******************  Bit definition for TIM_ARR register  *******************/
5866 #define TIM_ARR_ARR_Pos           (0U)
5867 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
5868 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
5869 
5870 /*******************  Bit definition for TIM_RCR register  *******************/
5871 #define TIM_RCR_REP_Pos           (0U)
5872 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
5873 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
5874 
5875 /*******************  Bit definition for TIM_CCR1 register  ******************/
5876 #define TIM_CCR1_CCR1_Pos         (0U)
5877 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
5878 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
5879 
5880 /*******************  Bit definition for TIM_CCR2 register  ******************/
5881 #define TIM_CCR2_CCR2_Pos         (0U)
5882 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
5883 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
5884 
5885 /*******************  Bit definition for TIM_CCR3 register  ******************/
5886 #define TIM_CCR3_CCR3_Pos         (0U)
5887 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
5888 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
5889 
5890 /*******************  Bit definition for TIM_CCR4 register  ******************/
5891 #define TIM_CCR4_CCR4_Pos         (0U)
5892 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
5893 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
5894 
5895 /*******************  Bit definition for TIM_BDTR register  ******************/
5896 #define TIM_BDTR_DTG_Pos          (0U)
5897 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
5898 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
5899 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
5900 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
5901 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
5902 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
5903 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
5904 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
5905 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
5906 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
5907 
5908 #define TIM_BDTR_LOCK_Pos         (8U)
5909 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
5910 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
5911 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
5912 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
5913 
5914 #define TIM_BDTR_OSSI_Pos         (10U)
5915 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
5916 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
5917 #define TIM_BDTR_OSSR_Pos         (11U)
5918 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
5919 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
5920 #define TIM_BDTR_BKE_Pos          (12U)
5921 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
5922 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable */
5923 #define TIM_BDTR_BKP_Pos          (13U)
5924 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
5925 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity */
5926 #define TIM_BDTR_AOE_Pos          (14U)
5927 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
5928 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
5929 #define TIM_BDTR_MOE_Pos          (15U)
5930 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
5931 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
5932 
5933 /*******************  Bit definition for TIM_DCR register  *******************/
5934 #define TIM_DCR_DBA_Pos           (0U)
5935 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
5936 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
5937 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
5938 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
5939 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
5940 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
5941 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
5942 
5943 #define TIM_DCR_DBL_Pos           (8U)
5944 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
5945 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
5946 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
5947 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
5948 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
5949 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
5950 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
5951 
5952 /*******************  Bit definition for TIM_DMAR register  ******************/
5953 #define TIM_DMAR_DMAB_Pos         (0U)
5954 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
5955 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
5956 
5957 /*******************  Bit definition for TIM14_OR register  ********************/
5958 #define TIM14_OR_TI1_RMP_Pos      (0U)
5959 #define TIM14_OR_TI1_RMP_Msk      (0x3UL << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
5960 #define TIM14_OR_TI1_RMP          TIM14_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
5961 #define TIM14_OR_TI1_RMP_0        (0x1UL << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
5962 #define TIM14_OR_TI1_RMP_1        (0x2UL << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
5963 
5964 /******************************************************************************/
5965 /*                                                                            */
5966 /*                          Touch Sensing Controller (TSC)                    */
5967 /*                                                                            */
5968 /******************************************************************************/
5969 /*******************  Bit definition for TSC_CR register  *********************/
5970 #define TSC_CR_TSCE_Pos          (0U)
5971 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
5972 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
5973 #define TSC_CR_START_Pos         (1U)
5974 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
5975 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
5976 #define TSC_CR_AM_Pos            (2U)
5977 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
5978 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
5979 #define TSC_CR_SYNCPOL_Pos       (3U)
5980 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
5981 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
5982 #define TSC_CR_IODEF_Pos         (4U)
5983 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
5984 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
5985 
5986 #define TSC_CR_MCV_Pos           (5U)
5987 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
5988 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
5989 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
5990 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
5991 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
5992 
5993 #define TSC_CR_PGPSC_Pos         (12U)
5994 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
5995 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
5996 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
5997 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
5998 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
5999 
6000 #define TSC_CR_SSPSC_Pos         (15U)
6001 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
6002 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
6003 #define TSC_CR_SSE_Pos           (16U)
6004 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
6005 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
6006 
6007 #define TSC_CR_SSD_Pos           (17U)
6008 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
6009 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
6010 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
6011 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
6012 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
6013 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
6014 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
6015 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
6016 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
6017 
6018 #define TSC_CR_CTPL_Pos          (24U)
6019 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
6020 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
6021 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
6022 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
6023 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
6024 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
6025 
6026 #define TSC_CR_CTPH_Pos          (28U)
6027 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
6028 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
6029 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
6030 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
6031 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
6032 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
6033 
6034 /*******************  Bit definition for TSC_IER register  ********************/
6035 #define TSC_IER_EOAIE_Pos        (0U)
6036 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
6037 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
6038 #define TSC_IER_MCEIE_Pos        (1U)
6039 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
6040 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
6041 
6042 /*******************  Bit definition for TSC_ICR register  ********************/
6043 #define TSC_ICR_EOAIC_Pos        (0U)
6044 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
6045 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
6046 #define TSC_ICR_MCEIC_Pos        (1U)
6047 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
6048 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
6049 
6050 /*******************  Bit definition for TSC_ISR register  ********************/
6051 #define TSC_ISR_EOAF_Pos         (0U)
6052 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
6053 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
6054 #define TSC_ISR_MCEF_Pos         (1U)
6055 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
6056 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
6057 
6058 /*******************  Bit definition for TSC_IOHCR register  ******************/
6059 #define TSC_IOHCR_G1_IO1_Pos     (0U)
6060 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
6061 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
6062 #define TSC_IOHCR_G1_IO2_Pos     (1U)
6063 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
6064 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
6065 #define TSC_IOHCR_G1_IO3_Pos     (2U)
6066 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
6067 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
6068 #define TSC_IOHCR_G1_IO4_Pos     (3U)
6069 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
6070 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
6071 #define TSC_IOHCR_G2_IO1_Pos     (4U)
6072 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
6073 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
6074 #define TSC_IOHCR_G2_IO2_Pos     (5U)
6075 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
6076 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
6077 #define TSC_IOHCR_G2_IO3_Pos     (6U)
6078 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
6079 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
6080 #define TSC_IOHCR_G2_IO4_Pos     (7U)
6081 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
6082 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
6083 #define TSC_IOHCR_G3_IO1_Pos     (8U)
6084 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
6085 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
6086 #define TSC_IOHCR_G3_IO2_Pos     (9U)
6087 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
6088 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
6089 #define TSC_IOHCR_G3_IO3_Pos     (10U)
6090 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
6091 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
6092 #define TSC_IOHCR_G3_IO4_Pos     (11U)
6093 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
6094 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
6095 #define TSC_IOHCR_G4_IO1_Pos     (12U)
6096 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
6097 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
6098 #define TSC_IOHCR_G4_IO2_Pos     (13U)
6099 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
6100 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
6101 #define TSC_IOHCR_G4_IO3_Pos     (14U)
6102 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
6103 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
6104 #define TSC_IOHCR_G4_IO4_Pos     (15U)
6105 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
6106 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
6107 #define TSC_IOHCR_G5_IO1_Pos     (16U)
6108 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
6109 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
6110 #define TSC_IOHCR_G5_IO2_Pos     (17U)
6111 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
6112 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
6113 #define TSC_IOHCR_G5_IO3_Pos     (18U)
6114 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
6115 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
6116 #define TSC_IOHCR_G5_IO4_Pos     (19U)
6117 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
6118 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
6119 #define TSC_IOHCR_G6_IO1_Pos     (20U)
6120 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
6121 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
6122 #define TSC_IOHCR_G6_IO2_Pos     (21U)
6123 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
6124 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
6125 #define TSC_IOHCR_G6_IO3_Pos     (22U)
6126 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
6127 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
6128 #define TSC_IOHCR_G6_IO4_Pos     (23U)
6129 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
6130 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
6131 #define TSC_IOHCR_G7_IO1_Pos     (24U)
6132 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
6133 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
6134 #define TSC_IOHCR_G7_IO2_Pos     (25U)
6135 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
6136 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
6137 #define TSC_IOHCR_G7_IO3_Pos     (26U)
6138 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
6139 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
6140 #define TSC_IOHCR_G7_IO4_Pos     (27U)
6141 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
6142 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
6143 #define TSC_IOHCR_G8_IO1_Pos     (28U)
6144 #define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
6145 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
6146 #define TSC_IOHCR_G8_IO2_Pos     (29U)
6147 #define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
6148 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
6149 #define TSC_IOHCR_G8_IO3_Pos     (30U)
6150 #define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
6151 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
6152 #define TSC_IOHCR_G8_IO4_Pos     (31U)
6153 #define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
6154 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
6155 
6156 /*******************  Bit definition for TSC_IOASCR register  *****************/
6157 #define TSC_IOASCR_G1_IO1_Pos    (0U)
6158 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
6159 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
6160 #define TSC_IOASCR_G1_IO2_Pos    (1U)
6161 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
6162 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
6163 #define TSC_IOASCR_G1_IO3_Pos    (2U)
6164 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
6165 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
6166 #define TSC_IOASCR_G1_IO4_Pos    (3U)
6167 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
6168 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
6169 #define TSC_IOASCR_G2_IO1_Pos    (4U)
6170 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
6171 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
6172 #define TSC_IOASCR_G2_IO2_Pos    (5U)
6173 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
6174 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
6175 #define TSC_IOASCR_G2_IO3_Pos    (6U)
6176 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
6177 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
6178 #define TSC_IOASCR_G2_IO4_Pos    (7U)
6179 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
6180 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
6181 #define TSC_IOASCR_G3_IO1_Pos    (8U)
6182 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
6183 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
6184 #define TSC_IOASCR_G3_IO2_Pos    (9U)
6185 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
6186 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
6187 #define TSC_IOASCR_G3_IO3_Pos    (10U)
6188 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
6189 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
6190 #define TSC_IOASCR_G3_IO4_Pos    (11U)
6191 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
6192 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
6193 #define TSC_IOASCR_G4_IO1_Pos    (12U)
6194 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
6195 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
6196 #define TSC_IOASCR_G4_IO2_Pos    (13U)
6197 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
6198 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
6199 #define TSC_IOASCR_G4_IO3_Pos    (14U)
6200 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
6201 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
6202 #define TSC_IOASCR_G4_IO4_Pos    (15U)
6203 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
6204 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
6205 #define TSC_IOASCR_G5_IO1_Pos    (16U)
6206 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
6207 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
6208 #define TSC_IOASCR_G5_IO2_Pos    (17U)
6209 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
6210 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
6211 #define TSC_IOASCR_G5_IO3_Pos    (18U)
6212 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
6213 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
6214 #define TSC_IOASCR_G5_IO4_Pos    (19U)
6215 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
6216 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
6217 #define TSC_IOASCR_G6_IO1_Pos    (20U)
6218 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
6219 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
6220 #define TSC_IOASCR_G6_IO2_Pos    (21U)
6221 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
6222 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
6223 #define TSC_IOASCR_G6_IO3_Pos    (22U)
6224 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
6225 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
6226 #define TSC_IOASCR_G6_IO4_Pos    (23U)
6227 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
6228 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
6229 #define TSC_IOASCR_G7_IO1_Pos    (24U)
6230 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
6231 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
6232 #define TSC_IOASCR_G7_IO2_Pos    (25U)
6233 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
6234 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
6235 #define TSC_IOASCR_G7_IO3_Pos    (26U)
6236 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
6237 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
6238 #define TSC_IOASCR_G7_IO4_Pos    (27U)
6239 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
6240 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
6241 #define TSC_IOASCR_G8_IO1_Pos    (28U)
6242 #define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
6243 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
6244 #define TSC_IOASCR_G8_IO2_Pos    (29U)
6245 #define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
6246 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
6247 #define TSC_IOASCR_G8_IO3_Pos    (30U)
6248 #define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
6249 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
6250 #define TSC_IOASCR_G8_IO4_Pos    (31U)
6251 #define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
6252 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
6253 
6254 /*******************  Bit definition for TSC_IOSCR register  ******************/
6255 #define TSC_IOSCR_G1_IO1_Pos     (0U)
6256 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
6257 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
6258 #define TSC_IOSCR_G1_IO2_Pos     (1U)
6259 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
6260 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
6261 #define TSC_IOSCR_G1_IO3_Pos     (2U)
6262 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
6263 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
6264 #define TSC_IOSCR_G1_IO4_Pos     (3U)
6265 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
6266 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
6267 #define TSC_IOSCR_G2_IO1_Pos     (4U)
6268 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
6269 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
6270 #define TSC_IOSCR_G2_IO2_Pos     (5U)
6271 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
6272 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
6273 #define TSC_IOSCR_G2_IO3_Pos     (6U)
6274 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
6275 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
6276 #define TSC_IOSCR_G2_IO4_Pos     (7U)
6277 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
6278 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
6279 #define TSC_IOSCR_G3_IO1_Pos     (8U)
6280 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
6281 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
6282 #define TSC_IOSCR_G3_IO2_Pos     (9U)
6283 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
6284 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
6285 #define TSC_IOSCR_G3_IO3_Pos     (10U)
6286 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
6287 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
6288 #define TSC_IOSCR_G3_IO4_Pos     (11U)
6289 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
6290 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
6291 #define TSC_IOSCR_G4_IO1_Pos     (12U)
6292 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
6293 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
6294 #define TSC_IOSCR_G4_IO2_Pos     (13U)
6295 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
6296 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
6297 #define TSC_IOSCR_G4_IO3_Pos     (14U)
6298 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
6299 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
6300 #define TSC_IOSCR_G4_IO4_Pos     (15U)
6301 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
6302 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
6303 #define TSC_IOSCR_G5_IO1_Pos     (16U)
6304 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
6305 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
6306 #define TSC_IOSCR_G5_IO2_Pos     (17U)
6307 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
6308 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
6309 #define TSC_IOSCR_G5_IO3_Pos     (18U)
6310 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
6311 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
6312 #define TSC_IOSCR_G5_IO4_Pos     (19U)
6313 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
6314 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
6315 #define TSC_IOSCR_G6_IO1_Pos     (20U)
6316 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
6317 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
6318 #define TSC_IOSCR_G6_IO2_Pos     (21U)
6319 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
6320 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
6321 #define TSC_IOSCR_G6_IO3_Pos     (22U)
6322 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
6323 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
6324 #define TSC_IOSCR_G6_IO4_Pos     (23U)
6325 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
6326 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
6327 #define TSC_IOSCR_G7_IO1_Pos     (24U)
6328 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
6329 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
6330 #define TSC_IOSCR_G7_IO2_Pos     (25U)
6331 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
6332 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
6333 #define TSC_IOSCR_G7_IO3_Pos     (26U)
6334 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
6335 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
6336 #define TSC_IOSCR_G7_IO4_Pos     (27U)
6337 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
6338 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
6339 #define TSC_IOSCR_G8_IO1_Pos     (28U)
6340 #define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
6341 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
6342 #define TSC_IOSCR_G8_IO2_Pos     (29U)
6343 #define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
6344 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
6345 #define TSC_IOSCR_G8_IO3_Pos     (30U)
6346 #define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
6347 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
6348 #define TSC_IOSCR_G8_IO4_Pos     (31U)
6349 #define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
6350 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
6351 
6352 /*******************  Bit definition for TSC_IOCCR register  ******************/
6353 #define TSC_IOCCR_G1_IO1_Pos     (0U)
6354 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
6355 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
6356 #define TSC_IOCCR_G1_IO2_Pos     (1U)
6357 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
6358 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
6359 #define TSC_IOCCR_G1_IO3_Pos     (2U)
6360 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
6361 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
6362 #define TSC_IOCCR_G1_IO4_Pos     (3U)
6363 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
6364 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
6365 #define TSC_IOCCR_G2_IO1_Pos     (4U)
6366 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
6367 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
6368 #define TSC_IOCCR_G2_IO2_Pos     (5U)
6369 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
6370 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
6371 #define TSC_IOCCR_G2_IO3_Pos     (6U)
6372 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
6373 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
6374 #define TSC_IOCCR_G2_IO4_Pos     (7U)
6375 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
6376 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
6377 #define TSC_IOCCR_G3_IO1_Pos     (8U)
6378 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
6379 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
6380 #define TSC_IOCCR_G3_IO2_Pos     (9U)
6381 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
6382 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
6383 #define TSC_IOCCR_G3_IO3_Pos     (10U)
6384 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
6385 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
6386 #define TSC_IOCCR_G3_IO4_Pos     (11U)
6387 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
6388 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
6389 #define TSC_IOCCR_G4_IO1_Pos     (12U)
6390 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
6391 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
6392 #define TSC_IOCCR_G4_IO2_Pos     (13U)
6393 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
6394 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
6395 #define TSC_IOCCR_G4_IO3_Pos     (14U)
6396 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
6397 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
6398 #define TSC_IOCCR_G4_IO4_Pos     (15U)
6399 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
6400 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
6401 #define TSC_IOCCR_G5_IO1_Pos     (16U)
6402 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
6403 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
6404 #define TSC_IOCCR_G5_IO2_Pos     (17U)
6405 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
6406 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
6407 #define TSC_IOCCR_G5_IO3_Pos     (18U)
6408 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
6409 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
6410 #define TSC_IOCCR_G5_IO4_Pos     (19U)
6411 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
6412 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
6413 #define TSC_IOCCR_G6_IO1_Pos     (20U)
6414 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
6415 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
6416 #define TSC_IOCCR_G6_IO2_Pos     (21U)
6417 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
6418 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
6419 #define TSC_IOCCR_G6_IO3_Pos     (22U)
6420 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
6421 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
6422 #define TSC_IOCCR_G6_IO4_Pos     (23U)
6423 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
6424 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
6425 #define TSC_IOCCR_G7_IO1_Pos     (24U)
6426 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
6427 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
6428 #define TSC_IOCCR_G7_IO2_Pos     (25U)
6429 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
6430 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
6431 #define TSC_IOCCR_G7_IO3_Pos     (26U)
6432 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
6433 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
6434 #define TSC_IOCCR_G7_IO4_Pos     (27U)
6435 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
6436 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
6437 #define TSC_IOCCR_G8_IO1_Pos     (28U)
6438 #define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
6439 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
6440 #define TSC_IOCCR_G8_IO2_Pos     (29U)
6441 #define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
6442 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
6443 #define TSC_IOCCR_G8_IO3_Pos     (30U)
6444 #define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
6445 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
6446 #define TSC_IOCCR_G8_IO4_Pos     (31U)
6447 #define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
6448 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
6449 
6450 /*******************  Bit definition for TSC_IOGCSR register  *****************/
6451 #define TSC_IOGCSR_G1E_Pos       (0U)
6452 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
6453 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
6454 #define TSC_IOGCSR_G2E_Pos       (1U)
6455 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
6456 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
6457 #define TSC_IOGCSR_G3E_Pos       (2U)
6458 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
6459 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
6460 #define TSC_IOGCSR_G4E_Pos       (3U)
6461 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
6462 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
6463 #define TSC_IOGCSR_G5E_Pos       (4U)
6464 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
6465 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
6466 #define TSC_IOGCSR_G6E_Pos       (5U)
6467 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
6468 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
6469 #define TSC_IOGCSR_G7E_Pos       (6U)
6470 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
6471 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
6472 #define TSC_IOGCSR_G8E_Pos       (7U)
6473 #define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
6474 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
6475 #define TSC_IOGCSR_G1S_Pos       (16U)
6476 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
6477 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
6478 #define TSC_IOGCSR_G2S_Pos       (17U)
6479 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
6480 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
6481 #define TSC_IOGCSR_G3S_Pos       (18U)
6482 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
6483 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
6484 #define TSC_IOGCSR_G4S_Pos       (19U)
6485 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
6486 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
6487 #define TSC_IOGCSR_G5S_Pos       (20U)
6488 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
6489 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
6490 #define TSC_IOGCSR_G6S_Pos       (21U)
6491 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
6492 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
6493 #define TSC_IOGCSR_G7S_Pos       (22U)
6494 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
6495 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
6496 #define TSC_IOGCSR_G8S_Pos       (23U)
6497 #define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
6498 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
6499 
6500 /*******************  Bit definition for TSC_IOGXCR register  *****************/
6501 #define TSC_IOGXCR_CNT_Pos       (0U)
6502 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
6503 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
6504 
6505 /******************************************************************************/
6506 /*                                                                            */
6507 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
6508 /*                                                                            */
6509 /******************************************************************************/
6510 
6511 /*
6512 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
6513 */
6514 
6515 /* Support of 7 bits data length feature */
6516 #define USART_7BITS_SUPPORT
6517 
6518 /* Support of LIN feature */
6519 #define USART_LIN_SUPPORT
6520 
6521 /* Support of Smartcard feature */
6522 #define USART_SMARTCARD_SUPPORT
6523 
6524 /* Support of Irda feature */
6525 #define USART_IRDA_SUPPORT
6526 
6527 /* Support of Wake Up from Stop Mode feature */
6528 #define USART_WUSM_SUPPORT
6529 
6530 /* Support of Full Auto Baud rate feature (4 modes) activation */
6531 #define USART_FABR_SUPPORT
6532 
6533 /******************  Bit definition for USART_CR1 register  *******************/
6534 #define USART_CR1_UE_Pos              (0U)
6535 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
6536 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
6537 #define USART_CR1_UESM_Pos            (1U)
6538 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
6539 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
6540 #define USART_CR1_RE_Pos              (2U)
6541 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
6542 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
6543 #define USART_CR1_TE_Pos              (3U)
6544 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
6545 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
6546 #define USART_CR1_IDLEIE_Pos          (4U)
6547 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
6548 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
6549 #define USART_CR1_RXNEIE_Pos          (5U)
6550 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
6551 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
6552 #define USART_CR1_TCIE_Pos            (6U)
6553 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
6554 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
6555 #define USART_CR1_TXEIE_Pos           (7U)
6556 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
6557 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
6558 #define USART_CR1_PEIE_Pos            (8U)
6559 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
6560 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
6561 #define USART_CR1_PS_Pos              (9U)
6562 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
6563 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
6564 #define USART_CR1_PCE_Pos             (10U)
6565 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
6566 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
6567 #define USART_CR1_WAKE_Pos            (11U)
6568 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
6569 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
6570 #define USART_CR1_M0_Pos              (12U)
6571 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
6572 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length bit 0 */
6573 #define USART_CR1_MME_Pos             (13U)
6574 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
6575 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
6576 #define USART_CR1_CMIE_Pos            (14U)
6577 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
6578 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
6579 #define USART_CR1_OVER8_Pos           (15U)
6580 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
6581 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
6582 #define USART_CR1_DEDT_Pos            (16U)
6583 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
6584 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
6585 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
6586 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
6587 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
6588 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
6589 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
6590 #define USART_CR1_DEAT_Pos            (21U)
6591 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
6592 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
6593 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
6594 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
6595 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
6596 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
6597 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
6598 #define USART_CR1_RTOIE_Pos           (26U)
6599 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
6600 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
6601 #define USART_CR1_EOBIE_Pos           (27U)
6602 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
6603 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
6604 #define USART_CR1_M1_Pos              (28U)
6605 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
6606 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length bit 1 */
6607 #define USART_CR1_M_Pos               (12U)
6608 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
6609 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< [M1:M0] Word length */
6610 
6611 /******************  Bit definition for USART_CR2 register  *******************/
6612 #define USART_CR2_ADDM7_Pos           (4U)
6613 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
6614 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
6615 #define USART_CR2_LBDL_Pos            (5U)
6616 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
6617 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
6618 #define USART_CR2_LBDIE_Pos           (6U)
6619 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
6620 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
6621 #define USART_CR2_LBCL_Pos            (8U)
6622 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
6623 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
6624 #define USART_CR2_CPHA_Pos            (9U)
6625 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
6626 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
6627 #define USART_CR2_CPOL_Pos            (10U)
6628 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
6629 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
6630 #define USART_CR2_CLKEN_Pos           (11U)
6631 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
6632 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
6633 #define USART_CR2_STOP_Pos            (12U)
6634 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
6635 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
6636 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
6637 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
6638 #define USART_CR2_LINEN_Pos           (14U)
6639 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
6640 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
6641 #define USART_CR2_SWAP_Pos            (15U)
6642 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
6643 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
6644 #define USART_CR2_RXINV_Pos           (16U)
6645 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
6646 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
6647 #define USART_CR2_TXINV_Pos           (17U)
6648 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
6649 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
6650 #define USART_CR2_DATAINV_Pos         (18U)
6651 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
6652 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
6653 #define USART_CR2_MSBFIRST_Pos        (19U)
6654 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
6655 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
6656 #define USART_CR2_ABREN_Pos           (20U)
6657 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
6658 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
6659 #define USART_CR2_ABRMODE_Pos         (21U)
6660 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
6661 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
6662 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
6663 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
6664 #define USART_CR2_RTOEN_Pos           (23U)
6665 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
6666 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
6667 #define USART_CR2_ADD_Pos             (24U)
6668 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
6669 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
6670 
6671 /******************  Bit definition for USART_CR3 register  *******************/
6672 #define USART_CR3_EIE_Pos             (0U)
6673 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
6674 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
6675 #define USART_CR3_IREN_Pos            (1U)
6676 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
6677 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
6678 #define USART_CR3_IRLP_Pos            (2U)
6679 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
6680 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
6681 #define USART_CR3_HDSEL_Pos           (3U)
6682 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
6683 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
6684 #define USART_CR3_NACK_Pos            (4U)
6685 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
6686 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
6687 #define USART_CR3_SCEN_Pos            (5U)
6688 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
6689 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
6690 #define USART_CR3_DMAR_Pos            (6U)
6691 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
6692 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
6693 #define USART_CR3_DMAT_Pos            (7U)
6694 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
6695 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
6696 #define USART_CR3_RTSE_Pos            (8U)
6697 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
6698 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
6699 #define USART_CR3_CTSE_Pos            (9U)
6700 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
6701 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
6702 #define USART_CR3_CTSIE_Pos           (10U)
6703 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
6704 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
6705 #define USART_CR3_ONEBIT_Pos          (11U)
6706 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
6707 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
6708 #define USART_CR3_OVRDIS_Pos          (12U)
6709 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
6710 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
6711 #define USART_CR3_DDRE_Pos            (13U)
6712 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
6713 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
6714 #define USART_CR3_DEM_Pos             (14U)
6715 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
6716 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
6717 #define USART_CR3_DEP_Pos             (15U)
6718 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
6719 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
6720 #define USART_CR3_SCARCNT_Pos         (17U)
6721 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
6722 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
6723 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
6724 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
6725 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
6726 #define USART_CR3_WUS_Pos             (20U)
6727 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
6728 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
6729 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
6730 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
6731 #define USART_CR3_WUFIE_Pos           (22U)
6732 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
6733 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
6734 
6735 /******************  Bit definition for USART_BRR register  *******************/
6736 #define USART_BRR_DIV_FRACTION_Pos    (0U)
6737 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
6738 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
6739 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
6740 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
6741 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
6742 
6743 /******************  Bit definition for USART_GTPR register  ******************/
6744 #define USART_GTPR_PSC_Pos            (0U)
6745 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
6746 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
6747 #define USART_GTPR_GT_Pos             (8U)
6748 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
6749 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
6750 
6751 
6752 /*******************  Bit definition for USART_RTOR register  *****************/
6753 #define USART_RTOR_RTO_Pos            (0U)
6754 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
6755 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
6756 #define USART_RTOR_BLEN_Pos           (24U)
6757 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
6758 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
6759 
6760 /*******************  Bit definition for USART_RQR register  ******************/
6761 #define USART_RQR_ABRRQ_Pos           (0U)
6762 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
6763 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
6764 #define USART_RQR_SBKRQ_Pos           (1U)
6765 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
6766 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
6767 #define USART_RQR_MMRQ_Pos            (2U)
6768 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
6769 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
6770 #define USART_RQR_RXFRQ_Pos           (3U)
6771 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
6772 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
6773 #define USART_RQR_TXFRQ_Pos           (4U)
6774 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
6775 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
6776 
6777 /*******************  Bit definition for USART_ISR register  ******************/
6778 #define USART_ISR_PE_Pos              (0U)
6779 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
6780 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
6781 #define USART_ISR_FE_Pos              (1U)
6782 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
6783 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
6784 #define USART_ISR_NE_Pos              (2U)
6785 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
6786 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
6787 #define USART_ISR_ORE_Pos             (3U)
6788 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
6789 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
6790 #define USART_ISR_IDLE_Pos            (4U)
6791 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
6792 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
6793 #define USART_ISR_RXNE_Pos            (5U)
6794 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
6795 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
6796 #define USART_ISR_TC_Pos              (6U)
6797 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
6798 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
6799 #define USART_ISR_TXE_Pos             (7U)
6800 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
6801 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
6802 #define USART_ISR_LBDF_Pos            (8U)
6803 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
6804 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
6805 #define USART_ISR_CTSIF_Pos           (9U)
6806 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
6807 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
6808 #define USART_ISR_CTS_Pos             (10U)
6809 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
6810 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
6811 #define USART_ISR_RTOF_Pos            (11U)
6812 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
6813 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
6814 #define USART_ISR_EOBF_Pos            (12U)
6815 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
6816 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
6817 #define USART_ISR_ABRE_Pos            (14U)
6818 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
6819 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
6820 #define USART_ISR_ABRF_Pos            (15U)
6821 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
6822 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
6823 #define USART_ISR_BUSY_Pos            (16U)
6824 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
6825 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
6826 #define USART_ISR_CMF_Pos             (17U)
6827 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
6828 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
6829 #define USART_ISR_SBKF_Pos            (18U)
6830 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
6831 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
6832 #define USART_ISR_RWU_Pos             (19U)
6833 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
6834 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
6835 #define USART_ISR_WUF_Pos             (20U)
6836 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
6837 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
6838 #define USART_ISR_TEACK_Pos           (21U)
6839 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
6840 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
6841 #define USART_ISR_REACK_Pos           (22U)
6842 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
6843 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
6844 
6845 /*******************  Bit definition for USART_ICR register  ******************/
6846 #define USART_ICR_PECF_Pos            (0U)
6847 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
6848 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
6849 #define USART_ICR_FECF_Pos            (1U)
6850 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
6851 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
6852 #define USART_ICR_NCF_Pos             (2U)
6853 #define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
6854 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
6855 #define USART_ICR_ORECF_Pos           (3U)
6856 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
6857 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
6858 #define USART_ICR_IDLECF_Pos          (4U)
6859 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
6860 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
6861 #define USART_ICR_TCCF_Pos            (6U)
6862 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
6863 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
6864 #define USART_ICR_LBDCF_Pos           (8U)
6865 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
6866 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
6867 #define USART_ICR_CTSCF_Pos           (9U)
6868 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
6869 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
6870 #define USART_ICR_RTOCF_Pos           (11U)
6871 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
6872 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
6873 #define USART_ICR_EOBCF_Pos           (12U)
6874 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
6875 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
6876 #define USART_ICR_CMCF_Pos            (17U)
6877 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
6878 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
6879 #define USART_ICR_WUCF_Pos            (20U)
6880 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
6881 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
6882 
6883 /*******************  Bit definition for USART_RDR register  ******************/
6884 #define USART_RDR_RDR                 ((uint16_t)0x01FFU)                      /*!< RDR[8:0] bits (Receive Data value) */
6885 
6886 /*******************  Bit definition for USART_TDR register  ******************/
6887 #define USART_TDR_TDR                 ((uint16_t)0x01FFU)                      /*!< TDR[8:0] bits (Transmit Data value) */
6888 
6889 /******************************************************************************/
6890 /*                                                                            */
6891 /*                         Window WATCHDOG (WWDG)                             */
6892 /*                                                                            */
6893 /******************************************************************************/
6894 
6895 /*******************  Bit definition for WWDG_CR register  ********************/
6896 #define WWDG_CR_T_Pos           (0U)
6897 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
6898 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
6899 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
6900 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
6901 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
6902 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
6903 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
6904 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
6905 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
6906 
6907 /* Legacy defines */
6908 #define  WWDG_CR_T0 WWDG_CR_T_0
6909 #define  WWDG_CR_T1 WWDG_CR_T_1
6910 #define  WWDG_CR_T2 WWDG_CR_T_2
6911 #define  WWDG_CR_T3 WWDG_CR_T_3
6912 #define  WWDG_CR_T4 WWDG_CR_T_4
6913 #define  WWDG_CR_T5 WWDG_CR_T_5
6914 #define  WWDG_CR_T6 WWDG_CR_T_6
6915 
6916 #define WWDG_CR_WDGA_Pos        (7U)
6917 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
6918 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
6919 
6920 /*******************  Bit definition for WWDG_CFR register  *******************/
6921 #define WWDG_CFR_W_Pos          (0U)
6922 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
6923 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
6924 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
6925 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
6926 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
6927 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
6928 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
6929 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
6930 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
6931 
6932 /* Legacy defines */
6933 #define  WWDG_CFR_W0 WWDG_CFR_W_0
6934 #define  WWDG_CFR_W1 WWDG_CFR_W_1
6935 #define  WWDG_CFR_W2 WWDG_CFR_W_2
6936 #define  WWDG_CFR_W3 WWDG_CFR_W_3
6937 #define  WWDG_CFR_W4 WWDG_CFR_W_4
6938 #define  WWDG_CFR_W5 WWDG_CFR_W_5
6939 #define  WWDG_CFR_W6 WWDG_CFR_W_6
6940 
6941 #define WWDG_CFR_WDGTB_Pos      (7U)
6942 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
6943 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
6944 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
6945 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
6946 
6947 /* Legacy defines */
6948 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6949 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6950 
6951 #define WWDG_CFR_EWI_Pos        (9U)
6952 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
6953 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
6954 
6955 /*******************  Bit definition for WWDG_SR register  ********************/
6956 #define WWDG_SR_EWIF_Pos        (0U)
6957 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
6958 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
6959 
6960 /**
6961   * @}
6962   */
6963 
6964  /**
6965   * @}
6966   */
6967 
6968 
6969 /** @addtogroup Exported_macro
6970   * @{
6971   */
6972 
6973 /****************************** ADC Instances *********************************/
6974 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
6975 
6976 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
6977 
6978 /****************************** COMP Instances *********************************/
6979 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
6980                                         ((INSTANCE) == COMP2))
6981 
6982 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
6983 
6984 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
6985 
6986 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
6987 
6988 /****************************** CEC Instances *********************************/
6989 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
6990 
6991 /****************************** CRC Instances *********************************/
6992 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
6993 
6994 /******************************* DAC Instances ********************************/
6995 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
6996 
6997 /******************************* DMA Instances ********************************/
6998 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
6999                                        ((INSTANCE) == DMA1_Channel2) || \
7000                                        ((INSTANCE) == DMA1_Channel3) || \
7001                                        ((INSTANCE) == DMA1_Channel4) || \
7002                                        ((INSTANCE) == DMA1_Channel5) || \
7003                                        ((INSTANCE) == DMA1_Channel6) || \
7004                                        ((INSTANCE) == DMA1_Channel7))
7005 
7006 /****************************** GPIO Instances ********************************/
7007 #define IS_GPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
7008                                          ((INSTANCE) == GPIOB) || \
7009                                          ((INSTANCE) == GPIOC) || \
7010                                          ((INSTANCE) == GPIOD) || \
7011                                          ((INSTANCE) == GPIOE) || \
7012                                          ((INSTANCE) == GPIOF))
7013 
7014 /**************************** GPIO Alternate Function Instances ***************/
7015 #define IS_GPIO_AF_INSTANCE(INSTANCE)   (((INSTANCE) == GPIOA) || \
7016                                          ((INSTANCE) == GPIOB) || \
7017                                          ((INSTANCE) == GPIOC) || \
7018                                          ((INSTANCE) == GPIOD) || \
7019                                          ((INSTANCE) == GPIOE))
7020 
7021 /****************************** GPIO Lock Instances ***************************/
7022 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7023                                          ((INSTANCE) == GPIOB))
7024 
7025 /****************************** I2C Instances *********************************/
7026 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7027                                        ((INSTANCE) == I2C2))
7028 
7029 /****************** I2C Instances : wakeup capability from stop modes *********/
7030 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
7031 
7032 /****************************** I2S Instances *********************************/
7033 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7034                                        ((INSTANCE) == SPI2))
7035 
7036 /****************************** IWDG Instances ********************************/
7037 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
7038 
7039 /****************************** RTC Instances *********************************/
7040 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
7041 
7042 /****************************** SMBUS Instances *********************************/
7043 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
7044 
7045 /****************************** SPI Instances *********************************/
7046 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7047                                        ((INSTANCE) == SPI2))
7048 
7049 /****************************** TIM Instances *********************************/
7050 #define IS_TIM_INSTANCE(INSTANCE)\
7051   (((INSTANCE) == TIM1)    || \
7052    ((INSTANCE) == TIM2)    || \
7053    ((INSTANCE) == TIM3)    || \
7054    ((INSTANCE) == TIM6)    || \
7055    ((INSTANCE) == TIM7)    || \
7056    ((INSTANCE) == TIM14)   || \
7057    ((INSTANCE) == TIM15)   || \
7058    ((INSTANCE) == TIM16)   || \
7059    ((INSTANCE) == TIM17))
7060 
7061 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
7062   (((INSTANCE) == TIM1)    || \
7063    ((INSTANCE) == TIM2)    || \
7064    ((INSTANCE) == TIM3)    || \
7065    ((INSTANCE) == TIM14)   || \
7066    ((INSTANCE) == TIM15)   || \
7067    ((INSTANCE) == TIM16)   || \
7068    ((INSTANCE) == TIM17))
7069 
7070 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
7071   (((INSTANCE) == TIM1)    || \
7072    ((INSTANCE) == TIM2)    || \
7073    ((INSTANCE) == TIM3)    || \
7074    ((INSTANCE) == TIM15))
7075 
7076 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
7077   (((INSTANCE) == TIM1)    || \
7078    ((INSTANCE) == TIM2)    || \
7079    ((INSTANCE) == TIM3))
7080 
7081 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
7082   (((INSTANCE) == TIM1)    || \
7083    ((INSTANCE) == TIM2)    || \
7084    ((INSTANCE) == TIM3))
7085 
7086 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
7087   (((INSTANCE) == TIM1)    || \
7088    ((INSTANCE) == TIM2)    || \
7089    ((INSTANCE) == TIM3))
7090 
7091 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
7092   (((INSTANCE) == TIM1)    || \
7093    ((INSTANCE) == TIM2)    || \
7094    ((INSTANCE) == TIM3))
7095 
7096 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
7097   (((INSTANCE) == TIM1)    || \
7098    ((INSTANCE) == TIM2)    || \
7099    ((INSTANCE) == TIM3)    || \
7100    ((INSTANCE) == TIM15))
7101 
7102 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
7103   (((INSTANCE) == TIM1)    || \
7104    ((INSTANCE) == TIM2)    || \
7105    ((INSTANCE) == TIM3)    || \
7106    ((INSTANCE) == TIM15))
7107 
7108 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
7109   (((INSTANCE) == TIM1)    || \
7110    ((INSTANCE) == TIM2)    || \
7111    ((INSTANCE) == TIM3))
7112 
7113 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
7114   (((INSTANCE) == TIM1)    || \
7115    ((INSTANCE) == TIM2)    || \
7116    ((INSTANCE) == TIM3))
7117 
7118 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
7119   (((INSTANCE) == TIM1))
7120 
7121 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
7122   (((INSTANCE) == TIM1))
7123 
7124 #define IS_TIM_ETR_INSTANCE(INSTANCE)\
7125   (((INSTANCE) == TIM1)    || \
7126    ((INSTANCE) == TIM2)    || \
7127    ((INSTANCE) == TIM3))
7128 
7129 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
7130   (((INSTANCE) == TIM1)    || \
7131    ((INSTANCE) == TIM2)    || \
7132    ((INSTANCE) == TIM3))
7133 
7134 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
7135   (((INSTANCE) == TIM1)    || \
7136    ((INSTANCE) == TIM2)    || \
7137    ((INSTANCE) == TIM3)    || \
7138    ((INSTANCE) == TIM6)    || \
7139    ((INSTANCE) == TIM7)    || \
7140    ((INSTANCE) == TIM15))
7141 
7142 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
7143   (((INSTANCE) == TIM1)    || \
7144    ((INSTANCE) == TIM2)    || \
7145    ((INSTANCE) == TIM3)    || \
7146    ((INSTANCE) == TIM15))
7147 
7148 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
7149     ((INSTANCE) == TIM2)
7150 
7151 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
7152     (((INSTANCE) == TIM1)    || \
7153      ((INSTANCE) == TIM2)    || \
7154      ((INSTANCE) == TIM3)    || \
7155      ((INSTANCE) == TIM15)   || \
7156      ((INSTANCE) == TIM16)   || \
7157      ((INSTANCE) == TIM17))
7158 
7159 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
7160       (((INSTANCE) == TIM1)    || \
7161        ((INSTANCE) == TIM15)   || \
7162        ((INSTANCE) == TIM16)   || \
7163        ((INSTANCE) == TIM17))
7164 
7165 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7166     ((((INSTANCE) == TIM1) &&                   \
7167      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7168       ((CHANNEL) == TIM_CHANNEL_2) ||          \
7169       ((CHANNEL) == TIM_CHANNEL_3) ||          \
7170       ((CHANNEL) == TIM_CHANNEL_4)))           \
7171     ||                                         \
7172     (((INSTANCE) == TIM2) &&                   \
7173      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7174       ((CHANNEL) == TIM_CHANNEL_2) ||          \
7175       ((CHANNEL) == TIM_CHANNEL_3) ||          \
7176       ((CHANNEL) == TIM_CHANNEL_4)))           \
7177     ||                                         \
7178     (((INSTANCE) == TIM3) &&                   \
7179      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7180       ((CHANNEL) == TIM_CHANNEL_2) ||          \
7181       ((CHANNEL) == TIM_CHANNEL_3) ||          \
7182       ((CHANNEL) == TIM_CHANNEL_4)))           \
7183     ||                                         \
7184     (((INSTANCE) == TIM14) &&                  \
7185      (((CHANNEL) == TIM_CHANNEL_1)))           \
7186     ||                                         \
7187     (((INSTANCE) == TIM15) &&                  \
7188      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7189       ((CHANNEL) == TIM_CHANNEL_2)))           \
7190     ||                                         \
7191     (((INSTANCE) == TIM16) &&                  \
7192      (((CHANNEL) == TIM_CHANNEL_1)))           \
7193     ||                                         \
7194     (((INSTANCE) == TIM17) &&                  \
7195      (((CHANNEL) == TIM_CHANNEL_1))))
7196 
7197 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7198    ((((INSTANCE) == TIM1) &&                    \
7199      (((CHANNEL) == TIM_CHANNEL_1) ||           \
7200       ((CHANNEL) == TIM_CHANNEL_2) ||           \
7201       ((CHANNEL) == TIM_CHANNEL_3)))            \
7202     ||                                          \
7203     (((INSTANCE) == TIM15) &&                   \
7204       ((CHANNEL) == TIM_CHANNEL_1))             \
7205     ||                                          \
7206     (((INSTANCE) == TIM16) &&                   \
7207      ((CHANNEL) == TIM_CHANNEL_1))              \
7208     ||                                          \
7209     (((INSTANCE) == TIM17) &&                   \
7210      ((CHANNEL) == TIM_CHANNEL_1)))
7211 
7212 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
7213   (((INSTANCE) == TIM1)    || \
7214    ((INSTANCE) == TIM2)    || \
7215    ((INSTANCE) == TIM3))
7216 
7217 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
7218   (((INSTANCE) == TIM1)    || \
7219    ((INSTANCE) == TIM15)   || \
7220    ((INSTANCE) == TIM16)   || \
7221    ((INSTANCE) == TIM17))
7222 
7223 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
7224   (((INSTANCE) == TIM1)    || \
7225    ((INSTANCE) == TIM2)    || \
7226    ((INSTANCE) == TIM3)    || \
7227    ((INSTANCE) == TIM14)   || \
7228    ((INSTANCE) == TIM15)   || \
7229    ((INSTANCE) == TIM16)   || \
7230    ((INSTANCE) == TIM17))
7231 
7232 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
7233   (((INSTANCE) == TIM1)    || \
7234    ((INSTANCE) == TIM2)    || \
7235    ((INSTANCE) == TIM3)    || \
7236    ((INSTANCE) == TIM6)    || \
7237    ((INSTANCE) == TIM7)    || \
7238    ((INSTANCE) == TIM15)   || \
7239    ((INSTANCE) == TIM16)   || \
7240    ((INSTANCE) == TIM17))
7241 
7242 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
7243   (((INSTANCE) == TIM1)    || \
7244    ((INSTANCE) == TIM2)    || \
7245    ((INSTANCE) == TIM3)    || \
7246    ((INSTANCE) == TIM15)   || \
7247    ((INSTANCE) == TIM16)   || \
7248    ((INSTANCE) == TIM17))
7249 
7250 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
7251   (((INSTANCE) == TIM1)    || \
7252    ((INSTANCE) == TIM15)   || \
7253    ((INSTANCE) == TIM16)   || \
7254    ((INSTANCE) == TIM17))
7255 
7256 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
7257   ((INSTANCE) == TIM14)
7258 
7259 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
7260   ((INSTANCE) == TIM1)
7261 
7262 /****************************** TSC Instances *********************************/
7263 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
7264 
7265 /*********************** UART Instances : IRDA mode ***************************/
7266 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7267                                     ((INSTANCE) == USART2))
7268 
7269 /********************* UART Instances : Smard card mode ***********************/
7270 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7271                                          ((INSTANCE) == USART2))
7272 
7273 /******************** USART Instances : Synchronous mode **********************/
7274 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7275                                      ((INSTANCE) == USART2) || \
7276                                      ((INSTANCE) == USART3) || \
7277                                      ((INSTANCE) == USART4))
7278 
7279 /******************** USART Instances : auto Baud rate detection **************/
7280 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7281                                                             ((INSTANCE) == USART2))
7282 
7283 /******************** UART Instances : Asynchronous mode **********************/
7284 #define IS_UART_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
7285                                       ((INSTANCE) == USART2) || \
7286                                       ((INSTANCE) == USART3) || \
7287                                       ((INSTANCE) == USART4))
7288 
7289 /******************** UART Instances : Half-Duplex mode **********************/
7290 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
7291                                                  ((INSTANCE) == USART2) || \
7292                                                  ((INSTANCE) == USART3) || \
7293                                                  ((INSTANCE) == USART4))
7294 
7295 /****************** UART Instances : Hardware Flow control ********************/
7296 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7297                                            ((INSTANCE) == USART2) || \
7298                                            ((INSTANCE) == USART3) || \
7299                                            ((INSTANCE) == USART4))
7300 
7301 /****************** UART Instances : LIN mode ********************/
7302 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7303                                         ((INSTANCE) == USART2))
7304 
7305 /****************** UART Instances : wakeup from stop mode ********************/
7306 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7307                                                     ((INSTANCE) == USART2))
7308 /* Old macro definition maintained for legacy purpose */
7309 #define IS_UART_WAKEUP_INSTANCE         IS_UART_WAKEUP_FROMSTOP_INSTANCE
7310 
7311 /****************** UART Instances : Driver enable detection ********************/
7312 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7313                                                   ((INSTANCE) == USART2) || \
7314                                                   ((INSTANCE) == USART3) || \
7315                                                   ((INSTANCE) == USART4))
7316 
7317 /****************************** WWDG Instances ********************************/
7318 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
7319 
7320 /**
7321   * @}
7322   */
7323 
7324 
7325 /******************************************************************************/
7326 /*  For a painless codes migration between the STM32F0xx device product       */
7327 /*  lines, the aliases defined below are put in place to overcome the         */
7328 /*  differences in the interrupt handlers and IRQn definitions.               */
7329 /*  No need to update developed interrupt code when moving across             */
7330 /*  product lines within the same STM32F0 Family                              */
7331 /******************************************************************************/
7332 
7333 /* Aliases for __IRQn */
7334 #define ADC1_IRQn                  ADC1_COMP_IRQn
7335 #define DMA1_Ch1_IRQn              DMA1_Channel1_IRQn
7336 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
7337 #define DMA1_Channel4_5_IRQn       DMA1_Channel4_5_6_7_IRQn
7338 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_6_7_IRQn
7339 #define VDDIO2_IRQn                PVD_VDDIO2_IRQn
7340 #define PVD_IRQn                   PVD_VDDIO2_IRQn
7341 #define RCC_IRQn                   RCC_CRS_IRQn
7342 #define TIM6_IRQn                  TIM6_DAC_IRQn
7343 #define USART3_6_IRQn              USART3_4_IRQn
7344 #define USART3_8_IRQn              USART3_4_IRQn
7345 
7346 #define SVC_IRQn                   SVCall_IRQn
7347 
7348 /* Aliases for __IRQHandler */
7349 #define ADC1_IRQHandler                  ADC1_COMP_IRQHandler
7350 #define DMA1_Ch1_IRQHandler              DMA1_Channel1_IRQHandler
7351 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
7352 #define DMA1_Channel4_5_IRQHandler       DMA1_Channel4_5_6_7_IRQHandler
7353 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
7354 #define VDDIO2_IRQHandler                PVD_VDDIO2_IRQHandler
7355 #define PVD_IRQHandler                   PVD_VDDIO2_IRQHandler
7356 #define RCC_IRQHandler                   RCC_CRS_IRQHandler
7357 #define TIM6_IRQHandler                  TIM6_DAC_IRQHandler
7358 #define USART3_6_IRQHandler              USART3_4_IRQHandler
7359 #define USART3_8_IRQHandler              USART3_4_IRQHandler
7360 
7361 #ifdef __cplusplus
7362 }
7363 #endif /* __cplusplus */
7364 
7365 #endif /* __STM32F071xB_H */
7366 
7367 /**
7368   * @}
7369   */
7370 
7371 /**
7372   * @}
7373   */
7374 
7375