1 /**
2   ******************************************************************************
3   * @file    stm32u031xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32U031xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32u031xx
30   * @{
31   */
32 
33 #ifndef STM32U031xx_H
34 #define STM32U031xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
46    */
47 #define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
48 #define __MPU_PRESENT             1 /*!< STM32U0xx  provides an MPU                    */
49 #define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
50 #define __NVIC_PRIO_BITS          2 /*!< STM32U0xx uses 2 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32U0XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
68   Reset_IRQn                  = -15,    /*!< -15 Reset Vector, invoked on Power up and warm reset              */
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70   HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
71   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
72   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
73   SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
74 /******  STM32 specific Interrupt Numbers **********************************************************************/
75   WWDG_IWDG_IRQn              = 0,      /*!< Window watchdog interrupt + Independent watchdog interrupt        */
76   PVD_PVM_IRQn                = 1,      /*!< PVD through EXTI Line detection Interrupt(EXTI lines 16/19/20/21) */
77   RTC_TAMP_IRQn               = 2,      /*!< RTC and TAMP interrupts (combined EXTI lines 20 & 21)             */
78   FLASH_ECC_IRQn              = 3,      /*!< FLASH global Interrupt + FLASH ECC interrupt                      */
79   RCC_CRS_IRQn                = 4,      /*!< RCC global Interrupt + CRS global interrupt                       */
80   EXTI0_1_IRQn                = 5,      /*!< EXTI Line0 & Line1 Interrupt                                      */
81   EXTI2_3_IRQn                = 6,      /*!< EXTI Line2 & Line3 Interrupt                                      */
82   EXTI4_15_IRQn               = 7,      /*!< EXTI Line4 to Line15 Interrupt                                    */
83   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                          */
84   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                           */
85   DMA1_Ch4_7_DMAMUX_OVR_IRQn  = 11,     /*!< DMAMUX_OVR_IT + GPDMA1 channel 4 to 7                             */
86   ADC_COMP1_IRQn              = 12,     /*!< ADC and COMP1 interrupts (ADC combined with EXTI 17 & 18)         */
87   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 break, update, trigger, commutation, error, direction change and index interrupts        */
88   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare interrupt                                    */
89   TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                             */
90   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                             */
91   TIM6_DAC_LPTIM1_IRQn        = 17,     /*!< TIM6 + LPTIM1 + DAC global interrupt (combined with EXTI 31)      */
92   TIM7_LPTIM2_IRQn            = 18,     /*!< TIM7 + LPTIM2 global interrupt (combined with EXTI 32)            */
93   TIM15_IRQn                  = 19,     /*!< TIM15 global interrupt (combined with EXTI 33)                    */
94   TIM16_IRQn                  = 20,     /*!< TIM16 global interrupt                                            */
95   TSC_IRQn                    = 21,     /*!< TSC global interrupt                                              */
96   I2C1_IRQn                   = 23,     /*!< I2C1 global interrupt (combined with EXTI 23)                     */
97   I2C2_3_IRQn                 = 24,     /*!< I2C2 + I2C3 global interrupt (combined with EXTI 22)                                */
98   SPI1_IRQn                   = 25,     /*!< SPI1/I2S1 global interrupt                                        */
99   SPI2_IRQn                   = 26,     /*!< SPI2 global interrupt                                             */
100   USART1_IRQn                 = 27,     /*!< USART1 global interrupt (combined with EXTI 25)                   */
101   USART2_LPUART2_IRQn         = 28,     /*!< USART2 global interrupt (combined with EXTI 26) + LPUART2 global interrupt (combined with EXTI lines 35)      */
102   USART3_LPUART1_IRQn         = 29,     /*!< USART3  (combined with EXTI 24) + LPUART1 global interrupt (combined with EXTI lines 28)                      */
103   USART4_IRQn                 = 30,     /*!< USART4  global interrupt (combined with EXTI 20)                  */
104   RNG_IRQn                    = 31,     /*!< RNG global interrupt                                              */
105 } IRQn_Type;
106 
107 /**
108   * @}
109   */
110 
111 #include "core_cm0plus.h"               /* Cortex-M0+ processor and core peripherals */
112 #include "system_stm32u0xx.h"
113 #include <stdint.h>
114 
115 /** @addtogroup Peripheral_registers_structures
116   * @{
117   */
118 
119 /**
120   * @brief Analog to Digital Converter
121   */
122 
123 typedef struct
124 {
125   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
126   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
127   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
128   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
129   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
130   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
131        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
132        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
133   __IO uint32_t AWD1TR;       /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
134   __IO uint32_t AWD2TR;       /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
135   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
136   __IO uint32_t AWD3TR;       /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
137        uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
138   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
139        uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
140   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
141   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
142        uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
143   __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
144 } ADC_TypeDef;
145 
146 typedef struct
147 {
148   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
149 } ADC_Common_TypeDef;
150 
151 /**
152   * @brief Comparator
153   */
154 typedef struct
155 {
156   __IO uint32_t CSR;         /*!< COMP control and status register,                                                 Address offset: 0x00 */
157 } COMP_TypeDef;
158 
159 typedef struct
160 {
161   __IO uint32_t CSR_ODD;        /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
162   __IO uint32_t CSR_EVEN;       /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
163 } COMP_Common_TypeDef;
164 
165 /**
166   * @brief CRC calculation unit
167   */
168 typedef struct
169 {
170   __IO uint32_t DR;             /*!< CRC Data register,                           Address offset: 0x00 */
171   __IO uint32_t IDR;            /*!< CRC Independent data register,               Address offset: 0x04 */
172   __IO uint32_t CR;             /*!< CRC Control register,                        Address offset: 0x08 */
173        uint32_t RESERVED2;      /*!< Reserved,                                                    0x0C */
174   __IO uint32_t INIT;           /*!< Initial CRC value register,                  Address offset: 0x10 */
175   __IO uint32_t POL;            /*!< CRC polynomial register,                     Address offset: 0x14 */
176        uint32_t RESERVED3[246]; /*!< Reserved,                                                         */
177   __IO uint32_t HWCFGR;         /*!< CRC IP HWCFGR register,                     Address offset: 0x3F0 */
178   __IO uint32_t VERR;           /*!< CRC IP version register,                    Address offset: 0x3F4 */
179   __IO uint32_t PIDR;           /*!< CRC IP type identification register,        Address offset: 0x3F8 */
180   __IO uint32_t SIDR;           /*!< CRC IP map Size ID register,                Address offset: 0x3FC */
181 } CRC_TypeDef;
182 
183 
184 /**
185   * @brief Digital to Analog Converter
186   */
187 typedef struct
188 {
189   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
190   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
191   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
192   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
193   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
194   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
195   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
196   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
197   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
198   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
199   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
200   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
201   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
202   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
203   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
204   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
205   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
206   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
207   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
208   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
209 } DAC_TypeDef;
210 
211 /**
212   * @brief Debug MCU
213   */
214 
215 typedef struct
216 {
217   __IO uint32_t IDCODE;           /*!< MCU device ID code,                        Address offset: 0x00      */
218   __IO uint32_t CR;               /*!< Debug configuration register,              Address offset: 0x04      */
219   __IO uint32_t APBFZ1;           /*!< Debug APB freeze register 1,               Address offset: 0x08      */
220   __IO uint32_t APBFZ2;           /*!< Debug APB freeze register 2,               Address offset: 0x0C      */
221 } DBGMCU_TypeDef;
222 
223 /**
224   * @brief DMA Controller
225   */
226 typedef struct
227 {
228   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
229   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
230   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
231   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
232 } DMA_Channel_TypeDef;
233 
234 typedef struct
235 {
236   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
237   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
238 } DMA_TypeDef;
239 
240 /**
241   * @brief DMA Multiplexer
242   */
243 typedef struct
244 {
245   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
246 }DMAMUX_Channel_TypeDef;
247 
248 typedef struct
249 {
250   __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
251   __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
252 }DMAMUX_ChannelStatus_TypeDef;
253 
254 typedef struct
255 {
256   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
257 }DMAMUX_RequestGen_TypeDef;
258 
259 typedef struct
260 {
261   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
262   __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
263 }DMAMUX_RequestGenStatus_TypeDef;
264 
265 /**
266   * @brief Asynch Interrupt/Event Controller (EXTI)
267   */
268 typedef struct
269 {
270   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
271   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
272   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
273   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
274   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
275        uint32_t RESERVED1[19];  /*!< Reserved 1,                                                0x14 -- 0x5C */
276   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
277        uint32_t RESERVED3[4];   /*!< Reserved 3,                                                0x70 -- 0x7C */
278   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
279   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
280        uint32_t RESERVED4[2];   /*!< Reserved 4,                                                0x88 -- 0x8C */
281   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
282   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
283 } EXTI_TypeDef;
284 
285 /**
286   * @brief FLASH Registers
287   */
288 typedef struct
289 {
290   __IO uint32_t ACR;           /*!< FLASH Access Control register,                     Address offset: 0x00 */
291        uint32_t RESERVED1;     /*!< Reserved1,                                         Address offset: 0x04 */
292   __IO uint32_t KEYR;          /*!< FLASH Key register,                                Address offset: 0x08 */
293   __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                         Address offset: 0x0C */
294   __IO uint32_t SR;            /*!< FLASH Status register,                             Address offset: 0x10 */
295   __IO uint32_t CR;            /*!< FLASH Control register,                            Address offset: 0x14 */
296   __IO uint32_t ECCR;          /*!< FLASH ECC register,                                Address offset: 0x18 */
297        uint32_t RESERVED2;     /*!< Reserved2,                                         Address offset: 0x1C */
298   __IO uint32_t OPTR;          /*!< FLASH Option register,                             Address offset: 0x20 */
299        uint32_t RESERVED3[2];  /*!< Reserved3,                                                 0x24 -- 0x28 */
300   __IO uint32_t WRP1AR;        /*!< FLASH Bank WRP area A address register,            Address offset: 0x2C */
301   __IO uint32_t WRP1BR;        /*!< FLASH Bank WRP area B address register,            Address offset: 0x30 */
302        uint32_t RESERVED4[19]; /*!< Reserved4,                                                0x34 -- 0x7C */
303   __IO uint32_t SECR;          /*!< FLASH Security option register,                    Address offset: 0x80 */
304        uint32_t RESERVED5;     /*!< Reserved5,                                         Address offset: 0x84 */
305   __IO uint32_t OEM1KEYW0R;    /*!< FLASH OEM1 key register 1,                         Address offset: 0x88 */
306   __IO uint32_t OEM1KEYW1R;    /*!< FLASH OEM1 key register 2,                         Address offset: 0x8C */
307   __IO uint32_t OEM1KEYW2R;    /*!< FLASH OEM1 key register 3,                         Address offset: 0x90 */
308   __IO uint32_t OEM1KEYW3R;    /*!< FLASH OEM1 key register 4,                         Address offset: 0x94 */
309   __IO uint32_t OEM2KEYW0R;    /*!< FLASH OEM2 key register 5,                         Address offset: 0x98 */
310   __IO uint32_t OEM2KEYW1R;    /*!< FLASH OEM2 key register 6,                         Address offset: 0x9C */
311   __IO uint32_t OEM2KEYW2R;    /*!< FLASH OEM2 key register 7,                         Address offset: 0xA0 */
312   __IO uint32_t OEM2KEYW3R;    /*!< FLASH OEM2 key register 8,                         Address offset: 0xA4 */
313   __IO uint32_t OEMKEYSR;      /*!< FLASH OEM key status register,                     Address offset: 0xA8 */
314   __IO uint32_t HDPCR;         /*!< FLASH HDP control register,                        Address offset: 0xAC */
315   __IO uint32_t HDPEXTR;       /*!< FLASH HDP extension register,                      Address offset: 0xB0 */
316 } FLASH_TypeDef;
317 
318 /**
319   * @brief General Purpose I/O
320   */
321 typedef struct
322 {
323   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
324   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
325   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
326   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
327   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
328   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
329   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
330   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
331   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
332   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
333 } GPIO_TypeDef;
334 
335 /**
336   * @brief Instruction Cache
337   */
338 
339 typedef struct
340 {
341   __IO uint32_t CR;             /*!< ICACHE control register,               Address offset: 0x00 */
342   __IO uint32_t SR;             /*!< ICACHE status register,                Address offset: 0x04 */
343   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,      Address offset: 0x08 */
344   __IO uint32_t FCR;            /*!< ICACHE Flag clear register,            Address offset: 0x0C */
345   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,           Address offset: 0x10 */
346   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,          Address offset: 0x14 */
347        uint32_t RESERVED1[2];   /*!< Reserved,                              Address offset: 0x018-0x01C */
348   __IO uint32_t CCR0;           /*!< ICACHE region 0 control register,      Address offset: 0x20 */
349   __IO uint32_t CCR1;           /*!< ICACHE region 1 control register,      Address offset: 0x24 */
350   __IO uint32_t CCR2;           /*!< ICACHE region 2 control register,      Address offset: 0x28 */
351   __IO uint32_t CCR3;           /*!< ICACHE region 3 control register,      Address offset: 0x2C */
352        uint32_t RESERVED2[240]; /*!< Reserved,                              Address offset: 0x30-0x3EC */
353   __IO uint32_t HWCFGR;         /*!< ICACHE HW configuration register,      Address offset: 0x3F0 */
354   __IO uint32_t VERR;           /*!< ICACHE version register,               Address offset: 0x3F4 */
355   __IO uint32_t IPIDR;          /*!< ICACHE IP identification register,     Address offset: 0x3F8 */
356   __IO uint32_t SIDR;           /*!< ICACHE size identification register,   Address offset: 0x3FC */
357 } ICACHE_TypeDef;
358 
359 /**
360   * @brief Inter-integrated Circuit Interface
361   */
362 typedef struct
363 {
364   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
365   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
366   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
367   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
368   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
369   __IO uint32_t RESERVED;    /*!< Reserved,                          Address offset: 0x14 */
370   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
371   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
372   __IO uint32_t RESERVED0;   /*!< Reserved,                          Address offset: 0x20 */
373   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
374   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
375 } I2C_TypeDef;
376 
377 /**
378   * @brief Independent WATCHDOG
379   */
380 typedef struct
381 {
382   __IO uint32_t KR;          /*!< IWDG Key register,                Address offset: 0x00 */
383   __IO uint32_t PR;          /*!< IWDG Prescaler register,          Address offset: 0x04 */
384   __IO uint32_t RLR;         /*!< IWDG Reload register,             Address offset: 0x08 */
385   __IO uint32_t SR;          /*!< IWDG Status register,             Address offset: 0x0C */
386   __IO uint32_t WINR;        /*!< IWDG Window register,             Address offset: 0x10 */
387   __IO uint32_t EWCR;        /*!< IWDG wake-up interrupt register,  Address offset: 0x14 */
388 } IWDG_TypeDef;
389 
390 
391 /**
392   * @brief LPTIMER
393   */
394 typedef struct
395 {
396   __IO uint32_t ISR;          /*!< LPTIM Interrupt and Status register,              Address offset: 0x00 */
397   __IO uint32_t ICR;          /*!< LPTIM Interrupt Clear register,                   Address offset: 0x04 */
398   __IO uint32_t DIER;         /*!< LPTIM Interrupt Enable register,                  Address offset: 0x08 */
399   __IO uint32_t CFGR;         /*!< LPTIM Configuration register,                     Address offset: 0x0C */
400   __IO uint32_t CR;           /*!< LPTIM Control register,                           Address offset: 0x10 */
401   __IO uint32_t CCR1;         /*!< LPTIM Capture/Compare register 1,                 Address offset: 0x14 */
402   __IO uint32_t ARR;          /*!< LPTIM Autoreload register,                        Address offset: 0x18 */
403   __IO uint32_t CNT;          /*!< LPTIM Counter register,                           Address offset: 0x1C */
404   __IO uint32_t RESERVED0;    /*!< Reserved,                                         Address offset: 0x20 */
405   __IO uint32_t CFGR2;        /*!< LPTIM Configuration register 2,                   Address offset: 0x24 */
406   __IO uint32_t RCR;          /*!< LPTIM Repetition register,                        Address offset: 0x28 */
407   __IO uint32_t CCMR1;        /*!< LPTIM Capture/Compare mode register 1,            Address offset: 0x2C */
408   __IO uint32_t CCMR2;        /*!< LPTIM Capture/Compare mode register 2,            Address offset: 0x30 */
409   __IO uint32_t CCR2;         /*!< LPTIM Capture/Compare register 2,                 Address offset: 0x34 */
410   __IO uint32_t CCR3;         /*!< LPTIM Capture/Compare register 3,                 Address offset: 0x38 */
411   __IO uint32_t CCR4;         /*!< LPTIM Capture/Compare register 4,                 Address offset: 0x3C */
412 } LPTIM_TypeDef;
413 
414 /**
415   * @brief Operational Amplifier (OPAMP)
416   */
417 typedef struct
418 {
419   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
420   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
421   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
422 } OPAMP_TypeDef;
423 
424 typedef struct
425 {
426   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to
427                                   several OPAMP instances, Address offset: 0x00         */
428 } OPAMP_Common_TypeDef;
429 
430 
431 /**
432   * @brief Power Control
433   */
434 typedef struct
435 {
436   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
437   __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
438   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
439   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
440   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
441   __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
442   __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
443        uint32_t RESERVED0;    /*!< Reserved,                                         Address offset: 0x1C */
444   __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
445   __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
446   __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
447   __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
448   __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
449   __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
450   __IO uint32_t PUCRD;        /*!< PWR Pull-Up Control Register of port D,           Address offset: 0x38 */
451   __IO uint32_t PDCRD;        /*!< PWR Pull-Down Control Register of port D,         Address offset: 0x3C */
452     uint32_t RESERVED1[2];    /*!< Reserved,                                         Address offset: 0x40 -- 0x44 */
453   __IO uint32_t PUCRF;        /*!< PWR Pull-Up Control Register of port F,           Address offset: 0x48 */
454   __IO uint32_t PDCRF;        /*!< PWR Pull-Down Control Register of port F,         Address offset: 0x4C */
455 } PWR_TypeDef;
456 
457 /**
458   * @brief Reset and Clock Control
459   */
460 
461 typedef struct
462 {
463   __IO uint32_t CR;             /*!< RCC Clock Sources Control Register,                                     Address offset: 0x00 */
464   __IO uint32_t ICSCR;          /*!< RCC Internal Clock Sources Calibration Register,                        Address offset: 0x04 */
465   __IO uint32_t CFGR;           /*!< RCC Regulated Domain Clocks Configuration Register,                     Address offset: 0x08 */
466   __IO uint32_t PLLCFGR;        /*!< RCC system PLL configuration register,                                  Address offset: 0x0C */
467        uint32_t RESERVED0[2];   /*!< Reserved,                                                               Address offset: 0x10 -- 0x14 */
468   __IO uint32_t CIER;           /*!< RCC Clock Interrupt Enable Register,                                    Address offset: 0x18 */
469   __IO uint32_t CIFR;           /*!< RCC Clock Interrupt Flag Register,                                      Address offset: 0x1C */
470   __IO uint32_t CICR;           /*!< RCC Clock Interrupt Clear Register,                                     Address offset: 0x20 */
471        uint32_t RESERVED1;      /*!< Reserved,                                                               Address offset: 0x24 */
472   __IO uint32_t AHBRSTR;        /*!< RCC AHB peripheral reset register,                                      Address offset: 0x28 */
473   __IO uint32_t IOPRSTR;        /*!< RCC AHB2 peripheral reset register,                                     Address offset: 0x2C */
474        uint32_t RESERVED2[2];   /*!< Reserved,                                                               Address offset: 0x30 -- 0x34 */
475   __IO uint32_t APBRSTR1;       /*!< RCC APB1 peripheral reset register,                                     Address offset: 0x38 */
476        uint32_t RESERVED3;      /*!< Reserved,                                                               Address offset: 0x3C */
477   __IO uint32_t APBRSTR2;       /*!< RCC APB2 peripheral reset register,                                     Address offset: 0x40 */
478        uint32_t RESERVED4;      /*!< Reserved,                                                               Address offset: 0x44 */
479   __IO uint32_t AHBENR;         /*!< RCC AHB peripheral clocks enable register,                              Address offset: 0x48 */
480   __IO uint32_t IOPENR;         /*!< RCC IO port enable register,                                            Address offset: 0x4C */
481   __IO uint32_t DBGCFGR;        /*!< RCC DBGCFGR control register,                                           Address offset: 0x50 */
482        uint32_t RESERVED5;      /*!< Reserved,                                                               Address offset: 0x54 */
483   __IO uint32_t APBENR1;        /*!< RCC APB1 peripherals clock enable register,                             Address offset: 0x58 */
484        uint32_t RESERVED6;      /*!< Reserved,                                                               Address offset: 0x5C */
485   __IO uint32_t APBENR2;        /*!< RCC APB2 peripherals clock enable register,                             Address offset: 0x60 */
486        uint32_t RESERVED7;      /*!< Reserved,                                                               Address offset: 0x64 */
487   __IO uint32_t AHBSMENR;       /*!< RCC AHB peripheral clocks enable in sleep mode register,                Address offset: 0x68 */
488   __IO uint32_t IOPSMENR;       /*!< RCC IO port peripheral clocks enable in sleep mode register,            Address offset: 0x6C */
489        uint32_t RESERVED8[2];   /*!< Reserved,                                                               Address offset: 0x70 -- 0x74 */
490   __IO uint32_t APBSMENR1;      /*!< RCC APB1 peripheral clocks enable in sleep mode register,               Address offset: 0x78 */
491        uint32_t RESERVED9;      /*!< Reserved,                                                               Address offset: 0x7C */
492   __IO uint32_t APBSMENR2;      /*!< RCC APB2 peripheral clocks enable in sleep mode register,               Address offset: 0x80 */
493        uint32_t RESERVED10;     /*!< Reserved,                                                               Address offset: 0x84 */
494   __IO uint32_t CCIPR;          /*!< RCC Peripherals Independent Clocks Configuration Register,              Address offset: 0x88 */
495        uint32_t RESERVED11;     /*!< Reserved,                                                               Address offset: 0x8C */
496   __IO uint32_t BDCR;           /*!< RCC backup domain control register,                                     Address offset: 0x90 */
497   __IO uint32_t CSR;            /*!< RCC clock control & status register,                                    Address offset: 0x94 */
498 } RCC_TypeDef;
499 
500 /**
501   * @brief RNG
502   */
503 
504 typedef struct
505 {
506   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
507   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
508   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
509   uint32_t RESERVED;
510   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
511 } RNG_TypeDef;
512 
513 /**
514   * @brief Real-Time Clock
515   */
516 typedef struct
517 {
518  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
519  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
520  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
521  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
522  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
523  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
524  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
525       uint32_t RESERVED0[2];/*!< Reserved,                                       Address offset: 0x20 */
526  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
527  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
528  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
529  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
530  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
531  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
532       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
533  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
534  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
535  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
536  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
537  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
538  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
539       uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
540  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
541       uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
542  __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
543  __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
544 } RTC_TypeDef;
545 
546 /**
547   * @brief Tamper and backup registers
548   */
549 typedef struct
550 {
551   __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */
552   __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */
553   __IO uint32_t CR3;            /*!< TAMP configuration register 3,            Address offset: 0x08 */
554   __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */
555        uint32_t RESERVED1[7];   /*!< Reserved,                                 Address offset: 0x28 */
556   __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */
557   __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */
558   __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
559        uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */
560   __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */
561        uint32_t RESERVED4[48];  /*!< Reserved,                                 Address offset: 0x40 -- 0xFC */
562   __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */
563   __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */
564   __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */
565   __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */
566   __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */
567   __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */
568   __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */
569   __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */
570   __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */
571 } TAMP_TypeDef;
572 
573 /**
574   * @brief System configuration controller
575   */
576 
577 typedef struct
578 {
579   __IO uint32_t CFGR1;          /*!< SYSCFG Control register,                      Address offset: 0x00 */
580        uint32_t RESERVED0[5];   /*!< Reserved                                               0x04 --0x14 */
581        uint32_t CFGR2;          /*!< SYSCFG Class B register,                      Address offset: 0x18 */
582   __IO uint32_t SCSR;           /*!< SYSCFG Backup Sram Erase Register,            Address offset: 0x1C */
583   __IO uint32_t SKR;            /*!< SYSCFG Backup Sram Key Register,              Address offset: 0x20 */
584   __IO uint32_t TSCCR;          /*!< SYSCFG TSC Comp Register,                     Address offset: 0x24 */
585        uint32_t RESERVED1[22];  /*!< Reserved                                               0x28 --0x2C */
586   __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,        Address offset: 0x80 */
587 } SYSCFG_TypeDef;
588 
589 /**
590   * @brief Serial Peripheral Interface
591   */
592 
593 typedef struct
594 {
595   __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
596   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
597   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
598   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
599   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
600   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
601   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
602   __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
603   __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
604 } SPI_TypeDef;
605 
606 /**
607   * @brief TIM
608   */
609 
610 typedef struct
611 {
612   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
613   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
614   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
615   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
616   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
617   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
618   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
619   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
620   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
621   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
622   __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
623   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
624   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
625   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
626   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
627   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
628   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
629   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
630   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
631   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
632   __IO uint32_t OR1;         /*!< TIM option register,                      Address offset: 0x50 */
633   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
634   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
635   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
636   __IO uint32_t AF1;         /*!< TIM alternate function register 1,        Address offset: 0x60 */
637   __IO uint32_t AF2;         /*!< TIM alternate function register 2,        Address offset: 0x64 */
638   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
639 } TIM_TypeDef;
640 
641 /**
642   * @brief Touch Sensing Controller (TSC)
643   */
644 
645 typedef struct
646 {
647   __IO uint32_t CR;          /*!< TSC control register,                                     Address offset: 0x00 */
648   __IO uint32_t IER;         /*!< TSC interrupt enable register,                            Address offset: 0x04 */
649   __IO uint32_t ICR;         /*!< TSC interrupt clear register,                             Address offset: 0x08 */
650   __IO uint32_t ISR;         /*!< TSC interrupt status register,                            Address offset: 0x0C */
651   __IO uint32_t IOHCR;       /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
652   uint32_t      RESERVED1;   /*!< Reserved,                                                 Address offset: 0x14 */
653   __IO uint32_t IOASCR;      /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
654   uint32_t      RESERVED2;   /*!< Reserved,                                                 Address offset: 0x1C */
655   __IO uint32_t IOSCR;       /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
656   uint32_t      RESERVED3;   /*!< Reserved,                                                 Address offset: 0x24 */
657   __IO uint32_t IOCCR;       /*!< TSC I/O channel control register,                         Address offset: 0x28 */
658   uint32_t      RESERVED4;   /*!< Reserved,                                                 Address offset: 0x2C */
659   __IO uint32_t IOGCSR;      /*!< TSC I/O group control status register,                    Address offset: 0x30 */
660   __IO uint32_t IOGXCR[7];   /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
661 } TSC_TypeDef;
662 
663 /**
664   * @brief Universal Synchronous Asynchronous Receiver Transmitter
665   */
666 
667 typedef struct
668 {
669   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
670   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
671   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
672   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
673   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
674   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
675   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
676   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
677   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
678   __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
679   __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
680   __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
681 } USART_TypeDef;
682 
683 
684 /**
685   * @brief Window WATCHDOG
686   */
687 
688 typedef struct
689 {
690   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
691   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
692   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
693 } WWDG_TypeDef;
694 
695 
696 /**
697   * @}
698   */
699 
700 /* =========================================================================================================================== */
701 /* ================                          Device Specific Peripheral Address Map                           ================ */
702 /* =========================================================================================================================== */
703 
704 /*!< Device Electronic Signature */
705 #define PACKAGE_BASE          (0x1FFF3D00UL)        /*!< Package data register base address     */
706 #define UID_BASE              (0x1FFF3E50UL)        /*!< Unique device ID register base address */
707 #define FLASHSIZE_BASE        (0x1FFF3EA0UL)        /*!< Flash size data register base address  */
708 
709 /*!< Bootloader Firmware */
710 /************ Bootloader Exit Secure Memory Firmware *************/
711 #define BL_EXIT_SEC_MEM_BASE    (0x1FFF3500UL)
712 
713 /**
714   * @}
715   */
716 
717 /** @addtogroup STM32U0xx_Peripheral_memory_map
718   * @{
719   */
720 
721 #define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address */
722 #define SRAM1_BASE            (0x20000000UL)              /*!< SRAM1 base address */
723 #define SRAM1_SIZE_MAX        (0x00002000UL)              /*!< maximum SRAM1 size (up to 8 KBytes) */
724 #define BKPSRAM2_BASE         (SRAM1_BASE + 0x00002000UL) /*!< SRAM2 BKP(up to 4 KB) base address */
725 #define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address */
726 #define IOPORT_BASE           (0x50000000UL)              /*!< IOPORT base address */
727 
728 #define FLASH_SIZE_DEFAULT    0x10000U                    /*!< Flash memory default size */
729 
730 #define FLASH_SIZE            ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
731                                ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
732                                 (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
733 
734 /* Internal Flash OTP Area */
735 #define FLASH_OTP_BASE          (0x1FFF6800UL)            /*!< FLASH OTP (one-time programmable) base address */
736 #define FLASH_OTP_SIZE          (0x400U)                  /*!< 1024 bytes OTP (one-time programmable)         */
737 
738 /* Flash system Area */
739 #define FLASH_SYSTEM_BASE_NS    (0x1FFF0000UL)            /*!< FLASH System non-secure base address  */
740 #define FLASH_SYSTEM_SIZE       (0x6800U)                 /*!< 26 Kbytes system Flash */
741 
742 /* Peripheral memory map */
743 #define APBPERIPH_BASE        PERIPH_BASE
744 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
745 
746 /*!< APB peripherals */
747 #define TIM2_BASE             (APBPERIPH_BASE + 0x0000UL)
748 #define TIM3_BASE             (APBPERIPH_BASE + 0x0400UL)
749 #define TIM6_BASE             (APBPERIPH_BASE + 0x1000UL)
750 #define TIM7_BASE             (APBPERIPH_BASE + 0x1400UL)
751 #define RTC_BASE              (APBPERIPH_BASE + 0x2800UL)
752 #define WWDG_BASE             (APBPERIPH_BASE + 0x2C00UL)
753 #define IWDG_BASE             (APBPERIPH_BASE + 0x3000UL)
754 #define SPI2_BASE             (APBPERIPH_BASE + 0x3800UL)
755 #define USART2_BASE           (APBPERIPH_BASE + 0x4400UL)
756 #define USART3_BASE           (APBPERIPH_BASE + 0x4800UL)
757 #define USART4_BASE           (APBPERIPH_BASE + 0x4C00UL)
758 #define I2C1_BASE             (APBPERIPH_BASE + 0x5400UL)
759 #define I2C2_BASE             (APBPERIPH_BASE + 0x5800UL)
760 #define PWR_BASE              (APBPERIPH_BASE + 0x7000UL)
761 #define DAC1_BASE             (APBPERIPH_BASE + 0x7400UL)
762 #define OPAMP1_BASE           (APBPERIPH_BASE + 0x7800UL)
763 #define LPTIM1_BASE           (APBPERIPH_BASE + 0x7C00UL)
764 #define LPUART1_BASE          (APBPERIPH_BASE + 0x8000UL)
765 #define LPUART2_BASE          (APBPERIPH_BASE + 0x8400UL)
766 #define I2C3_BASE             (APBPERIPH_BASE + 0x8800UL)
767 #define LPTIM2_BASE           (APBPERIPH_BASE + 0x9400UL)
768 #define TAMP_BASE             (APBPERIPH_BASE + 0xB000UL)   /*TAMPER (+ BKP Regs)*/
769 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x10000UL)  /*SYSCFG IF + COMP*/
770 #define COMP1_BASE            (SYSCFG_BASE + 0x0200UL)
771 #define ADC1_BASE             (APBPERIPH_BASE + 0x12400UL)
772 #define ADC1_COMMON_BASE      (APBPERIPH_BASE + 0x12708UL)
773 #define TIM1_BASE             (APBPERIPH_BASE + 0x12C00UL)
774 #define SPI1_BASE             (APBPERIPH_BASE + 0x13000UL)
775 #define USART1_BASE           (APBPERIPH_BASE + 0x13800UL)
776 #define TIM15_BASE            (APBPERIPH_BASE + 0x14000UL)
777 #define TIM16_BASE            (APBPERIPH_BASE + 0x14400UL)
778 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x15800UL)
779 
780 /*!< AHB peripherals */
781 #define DMA1_BASE             (AHBPERIPH_BASE + 0x0000UL)
782 
783 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
784 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
785 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
786 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
787 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
788 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
789 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
790 
791 #define DMAMUX1_BASE           (AHBPERIPH_BASE + 0x0800UL)
792 
793 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
794 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
795 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
796 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
797 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
798 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
799 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
800 
801 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
802 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
803 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
804 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
805 
806 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
807 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
808 #define DMAMUX1_IdRegisters_BASE        (DMAMUX1_BASE + 0x000003EC)
809 
810 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000UL)
811 #define EXTI_BASE             (AHBPERIPH_BASE + 0x1800UL) /* AIEC */
812 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000UL)
813 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000UL)
814 #define TSC_BASE              (AHBPERIPH_BASE + 0x4000UL)
815 #define RNG_BASE              (AHBPERIPH_BASE + 0x5000UL)
816 
817 /*!< IOPORT (GPIO) memory map */
818 #define GPIOA_BASE            (IOPORT_BASE + 0x0000UL)
819 #define GPIOB_BASE            (IOPORT_BASE + 0x0400UL)
820 #define GPIOC_BASE            (IOPORT_BASE + 0x0800UL)
821 #define GPIOD_BASE            (IOPORT_BASE + 0x0C00UL)
822 #define GPIOF_BASE            (IOPORT_BASE + 0x1400UL)
823 
824 /**
825   * @}
826   */
827 
828 /** @addtogroup Peripheral_declaration
829   * @{
830   */
831 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
832 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
833 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
834 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
835 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
836 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
837 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
838 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
839 
840 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
841 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
842 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
843 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
844 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
845 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
846 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
847 
848 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
849 
850 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
851 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
852 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
853 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
854 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
855 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
856 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
857 
858 
859 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
860 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
861 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
862 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
863 
864 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
865 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
866 
867 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
868 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
869 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
870 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
871 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
872 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
873 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
874 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
875 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
876 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
877 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
878 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
879 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
880 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
881 #define LPUART2             ((USART_TypeDef *) LPUART2_BASE)
882 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
883 #define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
884 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
885 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
886 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
887 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
888 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
889 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
890 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
891 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
892 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
893 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
894 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
895 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
896 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
897 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
898 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
899 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
900 #define USART1              ((USART_TypeDef *) USART1_BASE)
901 #define USART2              ((USART_TypeDef *) USART2_BASE)
902 #define USART3              ((USART_TypeDef *) USART3_BASE)
903 #define USART4              ((USART_TypeDef *) USART4_BASE)
904 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
905 
906 /**
907   * @}
908   */
909 
910 /** @addtogroup Exported_constants
911   * @{
912   */
913 
914   /** @addtogroup Hardware_Constant_Definition
915     * @{
916     */
917 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
918 
919   /**
920     * @}
921     */
922 
923   /** @addtogroup Peripheral_Registers_Bits_Definition
924   * @{
925   */
926 
927 /******************************************************************************/
928 /*                         Peripheral Registers_Bits_Definition               */
929 /******************************************************************************/
930 
931 /******************************************************************************/
932 /*                                                                            */
933 /*                      Analog to Digital Converter (ADC)                     */
934 /*                                                                            */
935 /******************************************************************************/
936 /********************  Bit definition for ADC_ISR register  *******************/
937 #define ADC_ISR_ADRDY_Pos              (0U)
938 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
939 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
940 #define ADC_ISR_EOSMP_Pos              (1U)
941 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
942 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
943 #define ADC_ISR_EOC_Pos                (2U)
944 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
945 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
946 #define ADC_ISR_EOS_Pos                (3U)
947 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
948 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
949 #define ADC_ISR_OVR_Pos                (4U)
950 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
951 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
952 #define ADC_ISR_AWD1_Pos               (7U)
953 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
954 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
955 #define ADC_ISR_AWD2_Pos               (8U)
956 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
957 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
958 #define ADC_ISR_AWD3_Pos               (9U)
959 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
960 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
961 #define ADC_ISR_EOCAL_Pos              (11U)
962 #define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
963 #define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
964 #define ADC_ISR_CCRDY_Pos              (13U)
965 #define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
966 #define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
967 
968 /* Legacy defines */
969 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
970 
971 /********************  Bit definition for ADC_IER register  *******************/
972 #define ADC_IER_ADRDYIE_Pos            (0U)
973 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
974 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
975 #define ADC_IER_EOSMPIE_Pos            (1U)
976 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
977 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
978 #define ADC_IER_EOCIE_Pos              (2U)
979 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
980 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
981 #define ADC_IER_EOSIE_Pos              (3U)
982 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
983 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
984 #define ADC_IER_OVRIE_Pos              (4U)
985 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
986 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
987 #define ADC_IER_AWD1IE_Pos             (7U)
988 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
989 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
990 #define ADC_IER_AWD2IE_Pos             (8U)
991 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
992 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
993 #define ADC_IER_AWD3IE_Pos             (9U)
994 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
995 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
996 #define ADC_IER_EOCALIE_Pos            (11U)
997 #define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
998 #define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
999 #define ADC_IER_CCRDYIE_Pos            (13U)
1000 #define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
1001 #define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
1002 
1003 /* Legacy defines */
1004 #define ADC_IER_EOSEQIE           (ADC_IER_EOSIE)
1005 
1006 /********************  Bit definition for ADC_CR register  ********************/
1007 #define ADC_CR_ADEN_Pos                (0U)
1008 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1009 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1010 #define ADC_CR_ADDIS_Pos               (1U)
1011 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1012 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1013 #define ADC_CR_ADSTART_Pos             (2U)
1014 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1015 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1016 #define ADC_CR_ADSTP_Pos               (4U)
1017 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1018 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1019 #define ADC_CR_ADVREGEN_Pos            (28U)
1020 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1021 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1022 #define ADC_CR_ADCAL_Pos               (31U)
1023 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1024 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1025 
1026 /********************  Bit definition for ADC_CFGR1 register  *****************/
1027 #define ADC_CFGR1_DMAEN_Pos            (0U)
1028 #define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
1029 #define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
1030 #define ADC_CFGR1_DMACFG_Pos           (1U)
1031 #define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
1032 #define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
1033 
1034 #define ADC_CFGR1_SCANDIR_Pos          (2U)
1035 #define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
1036 #define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
1037 
1038 #define ADC_CFGR1_RES_Pos              (3U)
1039 #define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
1040 #define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
1041 #define ADC_CFGR1_RES_0                (0x1U << ADC_CFGR1_RES_Pos)             /*!< 0x00000008 */
1042 #define ADC_CFGR1_RES_1                (0x2U << ADC_CFGR1_RES_Pos)             /*!< 0x00000010 */
1043 
1044 #define ADC_CFGR1_ALIGN_Pos            (5U)
1045 #define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
1046 #define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignment */
1047 
1048 #define ADC_CFGR1_EXTSEL_Pos           (6U)
1049 #define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
1050 #define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
1051 #define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
1052 #define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
1053 #define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
1054 
1055 #define ADC_CFGR1_EXTEN_Pos            (10U)
1056 #define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
1057 #define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
1058 #define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
1059 #define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
1060 
1061 #define ADC_CFGR1_OVRMOD_Pos           (12U)
1062 #define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
1063 #define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
1064 #define ADC_CFGR1_CONT_Pos             (13U)
1065 #define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
1066 #define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
1067 #define ADC_CFGR1_WAIT_Pos             (14U)
1068 #define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
1069 #define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
1070 #define ADC_CFGR1_AUTOFF_Pos           (15U)
1071 #define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
1072 #define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
1073 #define ADC_CFGR1_DISCEN_Pos           (16U)
1074 #define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
1075 #define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
1076 #define ADC_CFGR1_CHSELRMOD_Pos        (21U)
1077 #define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
1078 #define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
1079 
1080 #define ADC_CFGR1_AWD1SGL_Pos          (22U)
1081 #define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
1082 #define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1083 #define ADC_CFGR1_AWD1EN_Pos           (23U)
1084 #define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
1085 #define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1086 
1087 #define ADC_CFGR1_AWD1CH_Pos           (26U)
1088 #define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
1089 #define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
1090 #define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
1091 #define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
1092 #define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
1093 #define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
1094 #define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
1095 
1096 /* Legacy defines */
1097 #define ADC_CFGR1_AUTDLY          (ADC_CFGR1_WAIT)
1098 
1099 /********************  Bit definition for ADC_CFGR2 register  *****************/
1100 #define ADC_CFGR2_OVSE_Pos             (0U)
1101 #define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
1102 #define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
1103 
1104 #define ADC_CFGR2_OVSR_Pos             (2U)
1105 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1106 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1107 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1108 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1109 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1110 
1111 #define ADC_CFGR2_OVSS_Pos             (5U)
1112 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1113 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1114 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1115 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1116 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1117 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1118 
1119 #define ADC_CFGR2_TOVS_Pos             (9U)
1120 #define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
1121 #define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1122 
1123 #define ADC_CFGR2_LFTRIG_Pos           (29U)
1124 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
1125 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
1126 
1127 #define ADC_CFGR2_CKMODE_Pos           (30U)
1128 #define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
1129 #define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
1130 #define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
1131 #define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
1132 
1133 /********************  Bit definition for ADC_SMPR register  ******************/
1134 #define ADC_SMPR_SMP1_Pos              (0U)
1135 #define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
1136 #define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
1137 #define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
1138 #define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
1139 #define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
1140 
1141 #define ADC_SMPR_SMP2_Pos              (4U)
1142 #define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
1143 #define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
1144 #define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
1145 #define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
1146 #define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
1147 
1148 #define ADC_SMPR_SMPSEL_Pos            (8U)
1149 #define ADC_SMPR_SMPSEL_Msk            (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x07FFFF00 */
1150 #define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
1151 #define ADC_SMPR_SMPSEL0_Pos           (8U)
1152 #define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
1153 #define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
1154 #define ADC_SMPR_SMPSEL1_Pos           (9U)
1155 #define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
1156 #define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
1157 #define ADC_SMPR_SMPSEL2_Pos           (10U)
1158 #define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
1159 #define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
1160 #define ADC_SMPR_SMPSEL3_Pos           (11U)
1161 #define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
1162 #define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
1163 #define ADC_SMPR_SMPSEL4_Pos           (12U)
1164 #define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
1165 #define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
1166 #define ADC_SMPR_SMPSEL5_Pos           (13U)
1167 #define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
1168 #define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
1169 #define ADC_SMPR_SMPSEL6_Pos           (14U)
1170 #define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
1171 #define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
1172 #define ADC_SMPR_SMPSEL7_Pos           (15U)
1173 #define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
1174 #define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
1175 #define ADC_SMPR_SMPSEL8_Pos           (16U)
1176 #define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
1177 #define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
1178 #define ADC_SMPR_SMPSEL9_Pos           (17U)
1179 #define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
1180 #define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
1181 #define ADC_SMPR_SMPSEL10_Pos          (18U)
1182 #define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
1183 #define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
1184 #define ADC_SMPR_SMPSEL11_Pos          (19U)
1185 #define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
1186 #define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
1187 #define ADC_SMPR_SMPSEL12_Pos          (20U)
1188 #define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
1189 #define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
1190 #define ADC_SMPR_SMPSEL13_Pos          (21U)
1191 #define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
1192 #define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
1193 #define ADC_SMPR_SMPSEL14_Pos          (22U)
1194 #define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
1195 #define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
1196 #define ADC_SMPR_SMPSEL15_Pos          (23U)
1197 #define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
1198 #define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
1199 #define ADC_SMPR_SMPSEL16_Pos          (24U)
1200 #define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
1201 #define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
1202 #define ADC_SMPR_SMPSEL17_Pos          (25U)
1203 #define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
1204 #define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
1205 #define ADC_SMPR_SMPSEL18_Pos          (26U)
1206 #define ADC_SMPR_SMPSEL18_Msk          (0x1UL << ADC_SMPR_SMPSEL18_Pos)        /*!< 0x04000000 */
1207 #define ADC_SMPR_SMPSEL18              ADC_SMPR_SMPSEL18_Msk                   /*!< ADC channel 18 sampling time selection */
1208 #define ADC_SMPR_SMPSEL19_Pos          (27U)
1209 #define ADC_SMPR_SMPSEL19_Msk          (0x1UL << ADC_SMPR_SMPSEL19_Pos)        /*!< 0x08000000 */
1210 #define ADC_SMPR_SMPSEL19              ADC_SMPR_SMPSEL19_Msk                   /*!< ADC channel 19 sampling time selection */
1211 
1212 /********************  Bit definition for ADC_AWD1TR register  *******************/
1213 #define ADC_AWD1TR_LT1_Pos             (0U)
1214 #define ADC_AWD1TR_LT1_Msk             (0xFFFUL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000FFF */
1215 #define ADC_AWD1TR_LT1                 ADC_AWD1TR_LT1_Msk                      /*!< ADC analog watchdog 1 threshold low */
1216 #define ADC_AWD1TR_LT1_0               (0x001UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000001 */
1217 #define ADC_AWD1TR_LT1_1               (0x002UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000002 */
1218 #define ADC_AWD1TR_LT1_2               (0x004UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000004 */
1219 #define ADC_AWD1TR_LT1_3               (0x008UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000008 */
1220 #define ADC_AWD1TR_LT1_4               (0x010UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000010 */
1221 #define ADC_AWD1TR_LT1_5               (0x020UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000020 */
1222 #define ADC_AWD1TR_LT1_6               (0x040UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000040 */
1223 #define ADC_AWD1TR_LT1_7               (0x080UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000080 */
1224 #define ADC_AWD1TR_LT1_8               (0x100UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000100 */
1225 #define ADC_AWD1TR_LT1_9               (0x200UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000200 */
1226 #define ADC_AWD1TR_LT1_10              (0x400UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000400 */
1227 #define ADC_AWD1TR_LT1_11              (0x800UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000800 */
1228 
1229 #define ADC_AWD1TR_HT1_Pos             (16U)
1230 #define ADC_AWD1TR_HT1_Msk             (0xFFFUL << ADC_AWD1TR_HT1_Pos)         /*!< 0x0FFF0000 */
1231 #define ADC_AWD1TR_HT1                 ADC_AWD1TR_HT1_Msk                      /*!< ADC Analog watchdog 1 threshold high */
1232 #define ADC_AWD1TR_HT1_0               (0x001UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00010000 */
1233 #define ADC_AWD1TR_HT1_1               (0x002UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00020000 */
1234 #define ADC_AWD1TR_HT1_2               (0x004UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00040000 */
1235 #define ADC_AWD1TR_HT1_3               (0x008UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00080000 */
1236 #define ADC_AWD1TR_HT1_4               (0x010UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00100000 */
1237 #define ADC_AWD1TR_HT1_5               (0x020UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00200000 */
1238 #define ADC_AWD1TR_HT1_6               (0x040UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00400000 */
1239 #define ADC_AWD1TR_HT1_7               (0x080UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00800000 */
1240 #define ADC_AWD1TR_HT1_8               (0x100UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x01000000 */
1241 #define ADC_AWD1TR_HT1_9               (0x200UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x02000000 */
1242 #define ADC_AWD1TR_HT1_10              (0x400UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x04000000 */
1243 #define ADC_AWD1TR_HT1_11              (0x800UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x08000000 */
1244 
1245 /********************  Bit definition for ADC_AWD2TR register  *******************/
1246 #define ADC_AWD2TR_LT2_Pos             (0U)
1247 #define ADC_AWD2TR_LT2_Msk             (0xFFFUL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000FFF */
1248 #define ADC_AWD2TR_LT2                 ADC_AWD2TR_LT2_Msk                      /*!< ADC analog watchdog 2 threshold low */
1249 #define ADC_AWD2TR_LT2_0               (0x001UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000001 */
1250 #define ADC_AWD2TR_LT2_1               (0x002UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000002 */
1251 #define ADC_AWD2TR_LT2_2               (0x004UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000004 */
1252 #define ADC_AWD2TR_LT2_3               (0x008UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000008 */
1253 #define ADC_AWD2TR_LT2_4               (0x010UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000010 */
1254 #define ADC_AWD2TR_LT2_5               (0x020UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000020 */
1255 #define ADC_AWD2TR_LT2_6               (0x040UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000040 */
1256 #define ADC_AWD2TR_LT2_7               (0x080UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000080 */
1257 #define ADC_AWD2TR_LT2_8               (0x100UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000100 */
1258 #define ADC_AWD2TR_LT2_9               (0x200UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000200 */
1259 #define ADC_AWD2TR_LT2_10              (0x400UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000400 */
1260 #define ADC_AWD2TR_LT2_11              (0x800UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000800 */
1261 
1262 #define ADC_AWD2TR_HT2_Pos             (16U)
1263 #define ADC_AWD2TR_HT2_Msk             (0xFFFUL << ADC_AWD2TR_HT2_Pos)         /*!< 0x0FFF0000 */
1264 #define ADC_AWD2TR_HT2                 ADC_AWD2TR_HT2_Msk                      /*!< ADC analog watchdog 2 threshold high */
1265 #define ADC_AWD2TR_HT2_0               (0x001UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00010000 */
1266 #define ADC_AWD2TR_HT2_1               (0x002UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00020000 */
1267 #define ADC_AWD2TR_HT2_2               (0x004UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00040000 */
1268 #define ADC_AWD2TR_HT2_3               (0x008UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00080000 */
1269 #define ADC_AWD2TR_HT2_4               (0x010UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00100000 */
1270 #define ADC_AWD2TR_HT2_5               (0x020UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00200000 */
1271 #define ADC_AWD2TR_HT2_6               (0x040UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00400000 */
1272 #define ADC_AWD2TR_HT2_7               (0x080UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00800000 */
1273 #define ADC_AWD2TR_HT2_8               (0x100UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x01000000 */
1274 #define ADC_AWD2TR_HT2_9               (0x200UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x02000000 */
1275 #define ADC_AWD2TR_HT2_10              (0x400UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x04000000 */
1276 #define ADC_AWD2TR_HT2_11              (0x800UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x08000000 */
1277 
1278 /********************  Bit definition for ADC_CHSELR register  ****************/
1279 #define ADC_CHSELR_CHSEL_Pos           (0U)
1280 #define ADC_CHSELR_CHSEL_Msk           (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos)    /*!< 0x0007FFFFF */
1281 #define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1282 #define ADC_CHSELR_CHSEL22_Pos         (22U)
1283 #define ADC_CHSELR_CHSEL22_Msk         (0x1UL << ADC_CHSELR_CHSEL22_Pos)       /*!< 0x00400000 */
1284 #define ADC_CHSELR_CHSEL22             ADC_CHSELR_CHSEL22_Msk                  /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */
1285 #define ADC_CHSELR_CHSEL21_Pos         (21U)
1286 #define ADC_CHSELR_CHSEL21_Msk         (0x1UL << ADC_CHSELR_CHSEL21_Pos)       /*!< 0x00200000 */
1287 #define ADC_CHSELR_CHSEL21             ADC_CHSELR_CHSEL21_Msk                  /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */
1288 #define ADC_CHSELR_CHSEL20_Pos         (20U)
1289 #define ADC_CHSELR_CHSEL20_Msk         (0x1UL << ADC_CHSELR_CHSEL20_Pos)       /*!< 0x00100000 */
1290 #define ADC_CHSELR_CHSEL20             ADC_CHSELR_CHSEL20_Msk                  /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */
1291 #define ADC_CHSELR_CHSEL19_Pos         (19U)
1292 #define ADC_CHSELR_CHSEL19_Msk         (0x1UL << ADC_CHSELR_CHSEL19_Pos)       /*!< 0x00080000 */
1293 #define ADC_CHSELR_CHSEL19             ADC_CHSELR_CHSEL19_Msk                  /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */
1294 #define ADC_CHSELR_CHSEL18_Pos         (18U)
1295 #define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */
1296 #define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1297 #define ADC_CHSELR_CHSEL17_Pos         (17U)
1298 #define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
1299 #define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1300 #define ADC_CHSELR_CHSEL16_Pos         (16U)
1301 #define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
1302 #define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1303 #define ADC_CHSELR_CHSEL15_Pos         (15U)
1304 #define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
1305 #define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1306 #define ADC_CHSELR_CHSEL14_Pos         (14U)
1307 #define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
1308 #define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1309 #define ADC_CHSELR_CHSEL13_Pos         (13U)
1310 #define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
1311 #define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1312 #define ADC_CHSELR_CHSEL12_Pos         (12U)
1313 #define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
1314 #define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1315 #define ADC_CHSELR_CHSEL11_Pos         (11U)
1316 #define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
1317 #define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1318 #define ADC_CHSELR_CHSEL10_Pos         (10U)
1319 #define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
1320 #define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1321 #define ADC_CHSELR_CHSEL9_Pos          (9U)
1322 #define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
1323 #define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1324 #define ADC_CHSELR_CHSEL8_Pos          (8U)
1325 #define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
1326 #define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1327 #define ADC_CHSELR_CHSEL7_Pos          (7U)
1328 #define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
1329 #define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1330 #define ADC_CHSELR_CHSEL6_Pos          (6U)
1331 #define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
1332 #define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1333 #define ADC_CHSELR_CHSEL5_Pos          (5U)
1334 #define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
1335 #define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1336 #define ADC_CHSELR_CHSEL4_Pos          (4U)
1337 #define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
1338 #define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1339 #define ADC_CHSELR_CHSEL3_Pos          (3U)
1340 #define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
1341 #define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1342 #define ADC_CHSELR_CHSEL2_Pos          (2U)
1343 #define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
1344 #define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1345 #define ADC_CHSELR_CHSEL1_Pos          (1U)
1346 #define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
1347 #define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1348 #define ADC_CHSELR_CHSEL0_Pos          (0U)
1349 #define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
1350 #define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1351 
1352 #define ADC_CHSELR_SQ_ALL_Pos          (0U)
1353 #define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1354 #define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1355 
1356 #define ADC_CHSELR_SQ8_Pos             (28U)
1357 #define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
1358 #define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1359 #define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
1360 #define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
1361 #define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
1362 #define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
1363 
1364 #define ADC_CHSELR_SQ7_Pos             (24U)
1365 #define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
1366 #define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1367 #define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
1368 #define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
1369 #define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
1370 #define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
1371 
1372 #define ADC_CHSELR_SQ6_Pos             (20U)
1373 #define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
1374 #define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1375 #define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
1376 #define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
1377 #define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
1378 #define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
1379 
1380 #define ADC_CHSELR_SQ5_Pos             (16U)
1381 #define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
1382 #define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1383 #define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
1384 #define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
1385 #define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
1386 #define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
1387 
1388 #define ADC_CHSELR_SQ4_Pos             (12U)
1389 #define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
1390 #define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1391 #define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
1392 #define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
1393 #define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
1394 #define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
1395 
1396 #define ADC_CHSELR_SQ3_Pos             (8U)
1397 #define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
1398 #define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1399 #define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
1400 #define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
1401 #define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
1402 #define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
1403 
1404 #define ADC_CHSELR_SQ2_Pos             (4U)
1405 #define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
1406 #define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1407 #define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
1408 #define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
1409 #define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
1410 #define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
1411 
1412 #define ADC_CHSELR_SQ1_Pos             (0U)
1413 #define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
1414 #define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1415 #define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
1416 #define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
1417 #define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
1418 #define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
1419 
1420 /********************  Bit definition for ADC_AWD3TR register  *******************/
1421 #define ADC_AWD3TR_LT3_Pos             (0U)
1422 #define ADC_AWD3TR_LT3_Msk             (0xFFFUL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000FFF */
1423 #define ADC_AWD3TR_LT3                 ADC_AWD3TR_LT3_Msk                      /*!< ADC analog watchdog 3 threshold low */
1424 #define ADC_AWD3TR_LT3_0               (0x001UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000001 */
1425 #define ADC_AWD3TR_LT3_1               (0x002UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000002 */
1426 #define ADC_AWD3TR_LT3_2               (0x004UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000004 */
1427 #define ADC_AWD3TR_LT3_3               (0x008UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000008 */
1428 #define ADC_AWD3TR_LT3_4               (0x010UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000010 */
1429 #define ADC_AWD3TR_LT3_5               (0x020UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000020 */
1430 #define ADC_AWD3TR_LT3_6               (0x040UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000040 */
1431 #define ADC_AWD3TR_LT3_7               (0x080UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000080 */
1432 #define ADC_AWD3TR_LT3_8               (0x100UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000100 */
1433 #define ADC_AWD3TR_LT3_9               (0x200UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000200 */
1434 #define ADC_AWD3TR_LT3_10              (0x400UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000400 */
1435 #define ADC_AWD3TR_LT3_11              (0x800UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000800 */
1436 
1437 #define ADC_AWD3TR_HT3_Pos             (16U)
1438 #define ADC_AWD3TR_HT3_Msk             (0xFFFUL << ADC_AWD3TR_HT3_Pos)         /*!< 0x0FFF0000 */
1439 #define ADC_AWD3TR_HT3                 ADC_AWD3TR_HT3_Msk                      /*!< ADC analog watchdog 3 threshold high */
1440 #define ADC_AWD3TR_HT3_0               (0x001UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00010000 */
1441 #define ADC_AWD3TR_HT3_1               (0x002UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00020000 */
1442 #define ADC_AWD3TR_HT3_2               (0x004UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00040000 */
1443 #define ADC_AWD3TR_HT3_3               (0x008UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00080000 */
1444 #define ADC_AWD3TR_HT3_4               (0x010UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00100000 */
1445 #define ADC_AWD3TR_HT3_5               (0x020UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00200000 */
1446 #define ADC_AWD3TR_HT3_6               (0x040UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00400000 */
1447 #define ADC_AWD3TR_HT3_7               (0x080UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00800000 */
1448 #define ADC_AWD3TR_HT3_8               (0x100UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x01000000 */
1449 #define ADC_AWD3TR_HT3_9               (0x200UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x02000000 */
1450 #define ADC_AWD3TR_HT3_10              (0x400UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x04000000 */
1451 #define ADC_AWD3TR_HT3_11              (0x800UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x08000000 */
1452 
1453 /********************  Bit definition for ADC_DR register  ********************/
1454 #define ADC_DR_DATA_Pos                (0U)
1455 #define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
1456 #define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
1457 #define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
1458 #define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
1459 #define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
1460 #define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
1461 #define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
1462 #define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
1463 #define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
1464 #define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
1465 #define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
1466 #define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
1467 #define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
1468 #define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
1469 #define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
1470 #define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
1471 #define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
1472 #define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
1473 
1474 /********************  Bit definition for ADC_AWD2CR register  ****************/
1475 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1476 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1477 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1478 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1479 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1480 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1481 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1482 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1483 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1484 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1485 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1486 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1487 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1488 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1489 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1490 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1491 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1492 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1493 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1494 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1495 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1496 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1497 
1498 /********************  Bit definition for ADC_AWD3CR register  ****************/
1499 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1500 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1501 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1502 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1503 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1504 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1505 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1506 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1507 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
1508 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
1509 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
1510 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
1511 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
1512 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
1513 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
1514 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
1515 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
1516 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
1517 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
1518 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
1519 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
1520 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
1521 
1522 /********************  Bit definition for ADC_CALFACT register  ***************/
1523 #define ADC_CALFACT_CALFACT_Pos        (0U)
1524 #define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
1525 #define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
1526 #define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
1527 #define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
1528 #define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
1529 #define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
1530 #define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
1531 #define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
1532 #define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
1533 
1534 /*************************  ADC Common registers  *****************************/
1535 /********************  Bit definition for ADC_CCR register  *******************/
1536 #define ADC_CCR_PRESC_Pos              (18U)
1537 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
1538 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
1539 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
1540 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
1541 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
1542 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
1543 
1544 #define ADC_CCR_VREFEN_Pos             (22U)
1545 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
1546 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
1547 #define ADC_CCR_TSEN_Pos               (23U)
1548 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
1549 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
1550 #define ADC_CCR_VBATEN_Pos             (24U)
1551 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
1552 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to VBATEN sensor enable */
1553 
1554 
1555 /******************************************************************************/
1556 /*                                                                            */
1557 /*                          CRC calculation unit                              */
1558 /*                                                                            */
1559 /******************************************************************************/
1560 /*******************  Bit definition for CRC_DR register  *********************/
1561 #define CRC_DR_DR_Pos            (0U)
1562 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
1563 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
1564 
1565 /*******************  Bit definition for CRC_IDR register  ********************/
1566 #define CRC_IDR_IDR_Pos          (0U)
1567 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
1568 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
1569 
1570 /********************  Bit definition for CRC_CR register  ********************/
1571 #define CRC_CR_RESET_Pos         (0U)
1572 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
1573 #define CRC_CR_RESET             CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
1574 #define CRC_CR_POLYSIZE_Pos      (3U)
1575 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
1576 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
1577 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
1578 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
1579 #define CRC_CR_REV_IN_Pos        (5U)
1580 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
1581 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
1582 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
1583 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
1584 #define CRC_CR_REV_OUT_Pos       (7U)
1585 #define CRC_CR_REV_OUT_Msk       (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
1586 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
1587 #define CRC_CR_REV_OUT_0         (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
1588 #define CRC_CR_REV_OUT_1         (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
1589 #define CRC_CR_RTYPE_IN_Pos      (9U)
1590 #define CRC_CR_RTYPE_IN_Msk      (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
1591 #define CRC_CR_RTYPE_IN          CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
1592 #define CRC_CR_RTYPE_OUT_Pos     (10U)
1593 #define CRC_CR_RTYPE_OUT_Msk     (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
1594 #define CRC_CR_RTYPE_OUT         CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
1595 
1596 
1597 /*******************  Bit definition for CRC_INIT register  *******************/
1598 #define CRC_INIT_INIT_Pos        (0U)
1599 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
1600 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
1601 
1602 /*******************  Bit definition for CRC_POL register  ********************/
1603 #define CRC_POL_POL_Pos          (0U)
1604 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
1605 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
1606 /******************************************************************************/
1607 /*                                                                            */
1608 /*                      Digital to Analog Converter                           */
1609 /*                                                                            */
1610 /******************************************************************************/
1611 /********************  Bit definition for DAC_CR register  ********************/
1612 #define DAC_CR_EN1_Pos              (0U)
1613 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
1614 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
1615 #define DAC_CR_TEN1_Pos             (1U)
1616 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
1617 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
1618 
1619 #define DAC_CR_TSEL1_Pos            (2U)
1620 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
1621 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
1622 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
1623 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
1624 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
1625 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
1626 
1627 
1628 #define DAC_CR_WAVE1_Pos            (6U)
1629 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
1630 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1631 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
1632 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
1633 
1634 #define DAC_CR_MAMP1_Pos            (8U)
1635 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
1636 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1637 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
1638 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
1639 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
1640 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
1641 
1642 #define DAC_CR_DMAEN1_Pos           (12U)
1643 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
1644 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
1645 #define DAC_CR_DMAUDRIE1_Pos        (13U)
1646 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
1647 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
1648 #define DAC_CR_CEN1_Pos             (14U)
1649 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
1650 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
1651 
1652 #define DAC_CR_EN2_Pos              (16U)
1653 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
1654 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
1655 #define DAC_CR_TEN2_Pos             (17U)
1656 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
1657 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
1658 
1659 #define DAC_CR_TSEL2_Pos            (18U)
1660 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
1661 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1662 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
1663 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
1664 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
1665 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
1666 
1667 
1668 #define DAC_CR_WAVE2_Pos            (22U)
1669 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
1670 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1671 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
1672 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
1673 
1674 #define DAC_CR_MAMP2_Pos            (24U)
1675 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
1676 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1677 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
1678 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
1679 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
1680 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
1681 
1682 #define DAC_CR_DMAEN2_Pos           (28U)
1683 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
1684 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
1685 #define DAC_CR_DMAUDRIE2_Pos        (29U)
1686 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
1687 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
1688 #define DAC_CR_CEN2_Pos             (30U)
1689 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
1690 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
1691 
1692 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
1693 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
1694 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
1695 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
1696 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
1697 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
1698 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
1699 
1700 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
1701 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
1702 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
1703 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
1704 
1705 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
1706 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
1707 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
1708 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
1709 
1710 /******************  Bit definition for DAC_DHR8R1 register  ******************/
1711 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
1712 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
1713 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
1714 
1715 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
1716 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
1717 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
1718 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
1719 
1720 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
1721 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
1722 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
1723 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
1724 
1725 /******************  Bit definition for DAC_DHR8R2 register  ******************/
1726 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
1727 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
1728 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
1729 
1730 /*****************  Bit definition for DAC_DHR12RD register  ******************/
1731 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
1732 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
1733 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
1734 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
1735 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
1736 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
1737 
1738 /*****************  Bit definition for DAC_DHR12LD register  ******************/
1739 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
1740 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
1741 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
1742 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
1743 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
1744 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
1745 
1746 /******************  Bit definition for DAC_DHR8RD register  ******************/
1747 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
1748 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
1749 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
1750 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
1751 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
1752 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
1753 
1754 /*******************  Bit definition for DAC_DOR1 register  *******************/
1755 #define DAC_DOR1_DACC1DOR_Pos       (0U)
1756 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
1757 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
1758 
1759 /*******************  Bit definition for DAC_DOR2 register  *******************/
1760 #define DAC_DOR2_DACC2DOR_Pos       (0U)
1761 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
1762 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
1763 
1764 /********************  Bit definition for DAC_SR register  ********************/
1765 #define DAC_SR_DMAUDR1_Pos          (13U)
1766 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
1767 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
1768 #define DAC_SR_CAL_FLAG1_Pos        (14U)
1769 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
1770 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
1771 #define DAC_SR_BWST1_Pos            (15U)
1772 #define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
1773 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
1774 
1775 #define DAC_SR_DMAUDR2_Pos          (29U)
1776 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
1777 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
1778 #define DAC_SR_CAL_FLAG2_Pos        (30U)
1779 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
1780 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
1781 #define DAC_SR_BWST2_Pos            (31U)
1782 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
1783 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
1784 
1785 /*******************  Bit definition for DAC_CCR register  ********************/
1786 #define DAC_CCR_OTRIM1_Pos          (0U)
1787 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
1788 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
1789 #define DAC_CCR_OTRIM2_Pos          (16U)
1790 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
1791 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
1792 
1793 /*******************  Bit definition for DAC_MCR register  *******************/
1794 #define DAC_MCR_MODE1_Pos           (0U)
1795 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
1796 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
1797 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
1798 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
1799 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
1800 
1801 #define DAC_MCR_MODE2_Pos           (16U)
1802 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
1803 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
1804 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
1805 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
1806 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
1807 
1808 /******************  Bit definition for DAC_SHSR1 register  ******************/
1809 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
1810 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
1811 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
1812 
1813 /******************  Bit definition for DAC_SHSR2 register  ******************/
1814 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
1815 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
1816 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
1817 
1818 /******************  Bit definition for DAC_SHHR register  ******************/
1819 #define DAC_SHHR_THOLD1_Pos         (0U)
1820 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
1821 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
1822 #define DAC_SHHR_THOLD2_Pos         (16U)
1823 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
1824 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
1825 
1826 /******************  Bit definition for DAC_SHRR register  ******************/
1827 #define DAC_SHRR_TREFRESH1_Pos      (0U)
1828 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
1829 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
1830 #define DAC_SHRR_TREFRESH2_Pos      (16U)
1831 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
1832 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
1833 
1834 /******************************************************************************/
1835 /*                                                                            */
1836 /*                           DMA Controller (DMA)                             */
1837 /*                                                                            */
1838 /******************************************************************************/
1839 
1840 /*******************  Bit definition for DMA_ISR register  ********************/
1841 #define DMA_ISR_GIF1_Pos       (0U)
1842 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
1843 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
1844 #define DMA_ISR_TCIF1_Pos      (1U)
1845 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
1846 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
1847 #define DMA_ISR_HTIF1_Pos      (2U)
1848 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
1849 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
1850 #define DMA_ISR_TEIF1_Pos      (3U)
1851 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
1852 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
1853 #define DMA_ISR_GIF2_Pos       (4U)
1854 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
1855 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
1856 #define DMA_ISR_TCIF2_Pos      (5U)
1857 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
1858 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
1859 #define DMA_ISR_HTIF2_Pos      (6U)
1860 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
1861 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
1862 #define DMA_ISR_TEIF2_Pos      (7U)
1863 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
1864 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
1865 #define DMA_ISR_GIF3_Pos       (8U)
1866 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
1867 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
1868 #define DMA_ISR_TCIF3_Pos      (9U)
1869 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
1870 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
1871 #define DMA_ISR_HTIF3_Pos      (10U)
1872 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
1873 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
1874 #define DMA_ISR_TEIF3_Pos      (11U)
1875 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
1876 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 4 Transfer Error flag */
1877 #define DMA_ISR_GIF4_Pos       (12U)
1878 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
1879 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
1880 #define DMA_ISR_TCIF4_Pos      (13U)
1881 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
1882 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
1883 #define DMA_ISR_HTIF4_Pos      (14U)
1884 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
1885 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
1886 #define DMA_ISR_TEIF4_Pos      (15U)
1887 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
1888 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
1889 #define DMA_ISR_GIF5_Pos       (16U)
1890 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
1891 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
1892 #define DMA_ISR_TCIF5_Pos      (17U)
1893 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
1894 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
1895 #define DMA_ISR_HTIF5_Pos      (18U)
1896 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
1897 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
1898 #define DMA_ISR_TEIF5_Pos      (19U)
1899 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
1900 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
1901 #define DMA_ISR_GIF6_Pos       (20U)
1902 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
1903 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
1904 #define DMA_ISR_TCIF6_Pos      (21U)
1905 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
1906 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
1907 #define DMA_ISR_HTIF6_Pos      (22U)
1908 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
1909 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
1910 #define DMA_ISR_TEIF6_Pos      (23U)
1911 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
1912 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
1913 #define DMA_ISR_GIF7_Pos       (24U)
1914 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
1915 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
1916 #define DMA_ISR_TCIF7_Pos      (25U)
1917 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
1918 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
1919 #define DMA_ISR_HTIF7_Pos      (26U)
1920 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
1921 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
1922 #define DMA_ISR_TEIF7_Pos      (27U)
1923 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
1924 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
1925 
1926 /*******************  Bit definition for DMA_IFCR register  *******************/
1927 #define DMA_IFCR_CGIF1_Pos     (0U)
1928 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
1929 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
1930 #define DMA_IFCR_CTCIF1_Pos    (1U)
1931 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
1932 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
1933 #define DMA_IFCR_CHTIF1_Pos    (2U)
1934 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
1935 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
1936 #define DMA_IFCR_CTEIF1_Pos    (3U)
1937 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
1938 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
1939 #define DMA_IFCR_CGIF2_Pos     (4U)
1940 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
1941 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
1942 #define DMA_IFCR_CTCIF2_Pos    (5U)
1943 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
1944 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
1945 #define DMA_IFCR_CHTIF2_Pos    (6U)
1946 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
1947 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
1948 #define DMA_IFCR_CTEIF2_Pos    (7U)
1949 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
1950 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
1951 #define DMA_IFCR_CGIF3_Pos     (8U)
1952 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
1953 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
1954 #define DMA_IFCR_CTCIF3_Pos    (9U)
1955 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
1956 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
1957 #define DMA_IFCR_CHTIF3_Pos    (10U)
1958 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
1959 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
1960 #define DMA_IFCR_CTEIF3_Pos    (11U)
1961 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
1962 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
1963 #define DMA_IFCR_CGIF4_Pos     (12U)
1964 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
1965 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
1966 #define DMA_IFCR_CTCIF4_Pos    (13U)
1967 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
1968 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
1969 #define DMA_IFCR_CHTIF4_Pos    (14U)
1970 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
1971 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
1972 #define DMA_IFCR_CTEIF4_Pos    (15U)
1973 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
1974 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
1975 #define DMA_IFCR_CGIF5_Pos     (16U)
1976 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
1977 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
1978 #define DMA_IFCR_CTCIF5_Pos    (17U)
1979 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
1980 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
1981 #define DMA_IFCR_CHTIF5_Pos    (18U)
1982 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
1983 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
1984 #define DMA_IFCR_CTEIF5_Pos    (19U)
1985 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
1986 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
1987 #define DMA_IFCR_CGIF6_Pos     (20U)
1988 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
1989 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
1990 #define DMA_IFCR_CTCIF6_Pos    (21U)
1991 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
1992 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
1993 #define DMA_IFCR_CHTIF6_Pos    (22U)
1994 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
1995 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
1996 #define DMA_IFCR_CTEIF6_Pos    (23U)
1997 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
1998 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
1999 #define DMA_IFCR_CGIF7_Pos     (24U)
2000 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
2001 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
2002 #define DMA_IFCR_CTCIF7_Pos    (25U)
2003 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
2004 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
2005 #define DMA_IFCR_CHTIF7_Pos    (26U)
2006 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
2007 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
2008 #define DMA_IFCR_CTEIF7_Pos    (27U)
2009 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
2010 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
2011 
2012 /*******************  Bit definition for DMA_CCR register  ********************/
2013 #define DMA_CCR_EN_Pos         (0U)
2014 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2015 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2016 #define DMA_CCR_TCIE_Pos       (1U)
2017 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2018 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2019 #define DMA_CCR_HTIE_Pos       (2U)
2020 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2021 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2022 #define DMA_CCR_TEIE_Pos       (3U)
2023 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2024 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2025 #define DMA_CCR_DIR_Pos        (4U)
2026 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2027 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2028 #define DMA_CCR_CIRC_Pos       (5U)
2029 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2030 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2031 #define DMA_CCR_PINC_Pos       (6U)
2032 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2033 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2034 #define DMA_CCR_MINC_Pos       (7U)
2035 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2036 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2037 
2038 #define DMA_CCR_PSIZE_Pos      (8U)
2039 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2040 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2041 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
2042 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
2043 
2044 #define DMA_CCR_MSIZE_Pos      (10U)
2045 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2046 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2047 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
2048 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
2049 
2050 #define DMA_CCR_PL_Pos         (12U)
2051 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2052 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2053 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
2054 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
2055 
2056 #define DMA_CCR_MEM2MEM_Pos    (14U)
2057 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2058 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2059 
2060 /******************  Bit definition for DMA_CNDTR register  *******************/
2061 #define DMA_CNDTR_NDT_Pos      (0U)
2062 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2063 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2064 
2065 /******************  Bit definition for DMA_CPAR register  ********************/
2066 #define DMA_CPAR_PA_Pos        (0U)
2067 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2068 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2069 
2070 /******************  Bit definition for DMA_CMAR register  ********************/
2071 #define DMA_CMAR_MA_Pos        (0U)
2072 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2073 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2074 
2075 /******************************************************************************/
2076 /*                                                                            */
2077 /*                             DMAMUX Controller                              */
2078 /*                                                                            */
2079 /******************************************************************************/
2080 /********************  Bits definition for DMAMUX_CxCR register  **************/
2081 #define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
2082 #define DMAMUX_CxCR_DMAREQ_ID_Msk              (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
2083 #define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk             /*!< DMA Request ID   */
2084 #define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2085 #define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2086 #define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2087 #define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2088 #define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2089 #define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2090 #define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2091 #define DMAMUX_CxCR_DMAREQ_ID_7                (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
2092 #define DMAMUX_CxCR_SOIE_Pos                   (8U)
2093 #define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos)  /*!< 0x00000100 */
2094 #define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk             /*!< Synchro overrun interrupt enable     */
2095 #define DMAMUX_CxCR_EGE_Pos                    (9U)
2096 #define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)   /*!< 0x00000200 */
2097 #define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk              /*!< Event generation interrupt enable    */
2098 #define DMAMUX_CxCR_SE_Pos                     (16U)
2099 #define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)    /*!< 0x00010000 */
2100 #define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk               /*!< Synchronization enable               */
2101 #define DMAMUX_CxCR_SPOL_Pos                   (17U)
2102 #define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00060000 */
2103 #define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk             /*!< Synchronization polarity             */
2104 #define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00020000 */
2105 #define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00040000 */
2106 #define DMAMUX_CxCR_NBREQ_Pos                  (19U)
2107 #define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2108 #define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk             /*!< Number of request                    */
2109 #define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2110 #define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2111 #define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2112 #define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2113 #define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2114 #define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
2115 #define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2116 #define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk             /*!< Synchronization ID                   */
2117 #define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2118 #define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2119 #define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2120 #define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2121 #define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2122 
2123 /*******************  Bits definition for DMAMUX_CSR register  **************/
2124 #define DMAMUX_CSR_SOF0_Pos                          (0U)
2125 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
2126 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
2127 #define DMAMUX_CSR_SOF1_Pos                          (1U)
2128 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
2129 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
2130 #define DMAMUX_CSR_SOF2_Pos                          (2U)
2131 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
2132 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
2133 #define DMAMUX_CSR_SOF3_Pos                          (3U)
2134 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
2135 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
2136 #define DMAMUX_CSR_SOF4_Pos                          (4U)
2137 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
2138 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
2139 #define DMAMUX_CSR_SOF5_Pos                          (5U)
2140 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
2141 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
2142 #define DMAMUX_CSR_SOF6_Pos                          (6U)
2143 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
2144 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
2145 #define DMAMUX_CSR_SOF7_Pos                          (7U)
2146 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
2147 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
2148 #define DMAMUX_CSR_SOF8_Pos                          (8U)
2149 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
2150 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
2151 #define DMAMUX_CSR_SOF9_Pos                          (9U)
2152 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
2153 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
2154 #define DMAMUX_CSR_SOF10_Pos                         (10U)
2155 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
2156 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
2157 #define DMAMUX_CSR_SOF11_Pos                         (11U)
2158 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
2159 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
2160 
2161 /********************  Bits definition for DMAMUX_CFR register  **************/
2162 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
2163 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
2164 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
2165 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
2166 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
2167 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
2168 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
2169 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
2170 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
2171 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
2172 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
2173 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
2174 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
2175 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
2176 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
2177 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
2178 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
2179 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
2180 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
2181 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
2182 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
2183 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
2184 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
2185 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
2186 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
2187 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
2188 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
2189 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
2190 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
2191 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
2192 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
2193 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
2194 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
2195 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
2196 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
2197 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
2198 
2199 /********************  Bits definition for DMAMUX_RGxCR register  ************/
2200 #define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
2201 #define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2202 #define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk             /*!< Signal ID                         */
2203 #define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2204 #define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2205 #define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2206 #define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2207 #define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2208 #define DMAMUX_RGxCR_OIE_Pos                   (8U)
2209 #define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos)  /*!< 0x00000100 */
2210 #define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk             /*!< Overrun interrupt enable             */
2211 #define DMAMUX_RGxCR_GE_Pos                    (16U)
2212 #define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)   /*!< 0x00010000 */
2213 #define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk              /*!< Generation enable                    */
2214 #define DMAMUX_RGxCR_GPOL_Pos                  (17U)
2215 #define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2216 #define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk            /*!< Generation polarity                  */
2217 #define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2218 #define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2219 #define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
2220 #define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2221 #define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk             /*!< Number of request                 */
2222 #define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2223 #define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2224 #define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2225 #define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2226 #define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2227 
2228 /********************  Bits definition for DMAMUX_RGSR register  **************/
2229 #define DMAMUX_RGSR_OF0_Pos                    (0U)
2230 #define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)   /*!< 0x00000001 */
2231 #define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk              /*!< Overrun flag 0                       */
2232 #define DMAMUX_RGSR_OF1_Pos                    (1U)
2233 #define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)   /*!< 0x00000002 */
2234 #define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk              /*!< Overrun flag 1                       */
2235 #define DMAMUX_RGSR_OF2_Pos                    (2U)
2236 #define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)   /*!< 0x00000004 */
2237 #define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk              /*!< Overrun flag 2                       */
2238 #define DMAMUX_RGSR_OF3_Pos                    (3U)
2239 #define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)   /*!< 0x00000008 */
2240 #define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk              /*!< Overrun flag 3                       */
2241 
2242 /********************  Bits definition for DMAMUX_RGCFR register  **************/
2243 #define DMAMUX_RGCFR_COF0_Pos                  (0U)
2244 #define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2245 #define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk            /*!< Clear Overrun flag 0                 */
2246 #define DMAMUX_RGCFR_COF1_Pos                  (1U)
2247 #define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2248 #define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk            /*!< Clear Overrun flag 1                 */
2249 #define DMAMUX_RGCFR_COF2_Pos                  (2U)
2250 #define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2251 #define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk            /*!< Clear Overrun flag 2                 */
2252 #define DMAMUX_RGCFR_COF3_Pos                  (3U)
2253 #define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2254 #define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk            /*!< Clear Overrun flag 3                 */
2255 
2256 /*****************  Bits definition for DMAMUX_IPHW_CFGR2 register  ************/
2257 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos       (0U)
2258 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk       (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
2259 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ           DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources   */
2260 
2261 /*****************  Bits definition for DMAMUX_IPHW_CFGR1 register  ************/
2262 #define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos       (0U)
2263 #define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk       (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
2264 #define DMAMUX_IPHW_CFGR1_NB_STREAMS           DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams                */
2265 
2266 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos    (8U)
2267 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk    (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
2268 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ        DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests     */
2269 
2270 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos     (16U)
2271 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk     (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
2272 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG         DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
2273 
2274 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos       (24U)
2275 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk       (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
2276 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN           DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks  */
2277 
2278 /******************************************************************************/
2279 /*                                                                            */
2280 /*                    External Interrupt/Event Controller                     */
2281 /*                                                                            */
2282 /******************************************************************************/
2283 /******************  Bit definition for EXTI_RTSR1 register  *******************/
2284 #define EXTI_RTSR1_TR_Pos          (0U)
2285 #define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
2286 #define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
2287 #define EXTI_RTSR1_TR0_Pos         (0U)
2288 #define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
2289 #define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
2290 #define EXTI_RTSR1_TR1_Pos         (1U)
2291 #define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
2292 #define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
2293 #define EXTI_RTSR1_TR2_Pos         (2U)
2294 #define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
2295 #define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
2296 #define EXTI_RTSR1_TR3_Pos         (3U)
2297 #define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
2298 #define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
2299 #define EXTI_RTSR1_TR4_Pos         (4U)
2300 #define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
2301 #define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
2302 #define EXTI_RTSR1_TR5_Pos         (5U)
2303 #define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
2304 #define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
2305 #define EXTI_RTSR1_TR6_Pos         (6U)
2306 #define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
2307 #define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
2308 #define EXTI_RTSR1_TR7_Pos         (7U)
2309 #define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
2310 #define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
2311 #define EXTI_RTSR1_TR8_Pos         (8U)
2312 #define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
2313 #define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
2314 #define EXTI_RTSR1_TR9_Pos         (9U)
2315 #define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
2316 #define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
2317 #define EXTI_RTSR1_TR10_Pos        (10U)
2318 #define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
2319 #define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
2320 #define EXTI_RTSR1_TR11_Pos        (11U)
2321 #define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
2322 #define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
2323 #define EXTI_RTSR1_TR12_Pos        (12U)
2324 #define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
2325 #define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
2326 #define EXTI_RTSR1_TR13_Pos        (13U)
2327 #define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
2328 #define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
2329 #define EXTI_RTSR1_TR14_Pos        (14U)
2330 #define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
2331 #define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
2332 #define EXTI_RTSR1_TR15_Pos        (15U)
2333 #define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
2334 #define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
2335 #define EXTI_RTSR1_TR16_Pos        (16U)
2336 #define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
2337 #define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
2338 #define EXTI_RTSR1_TR17_Pos        (17U)
2339 #define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
2340 #define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
2341 #define EXTI_RTSR1_TR20_Pos        (20U)
2342 #define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
2343 #define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
2344 #define EXTI_RTSR1_TR21_Pos        (21U)
2345 #define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
2346 #define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
2347 
2348 /******************  Bit definition for EXTI_FTSR1 register  *******************/
2349 #define EXTI_FTSR1_TR_Pos          (0U)
2350 #define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
2351 #define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
2352 #define EXTI_FTSR1_TR0_Pos         (0U)
2353 #define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
2354 #define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
2355 #define EXTI_FTSR1_TR1_Pos         (1U)
2356 #define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
2357 #define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
2358 #define EXTI_FTSR1_TR2_Pos         (2U)
2359 #define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
2360 #define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
2361 #define EXTI_FTSR1_TR3_Pos         (3U)
2362 #define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
2363 #define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
2364 #define EXTI_FTSR1_TR4_Pos         (4U)
2365 #define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
2366 #define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
2367 #define EXTI_FTSR1_TR5_Pos         (5U)
2368 #define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
2369 #define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
2370 #define EXTI_FTSR1_TR6_Pos         (6U)
2371 #define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
2372 #define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
2373 #define EXTI_FTSR1_TR7_Pos         (7U)
2374 #define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
2375 #define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
2376 #define EXTI_FTSR1_TR8_Pos         (8U)
2377 #define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
2378 #define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
2379 #define EXTI_FTSR1_TR9_Pos         (9U)
2380 #define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
2381 #define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
2382 #define EXTI_FTSR1_TR10_Pos        (10U)
2383 #define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
2384 #define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
2385 #define EXTI_FTSR1_TR11_Pos        (11U)
2386 #define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
2387 #define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
2388 #define EXTI_FTSR1_TR12_Pos        (12U)
2389 #define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
2390 #define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
2391 #define EXTI_FTSR1_TR13_Pos        (13U)
2392 #define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
2393 #define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
2394 #define EXTI_FTSR1_TR14_Pos        (14U)
2395 #define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
2396 #define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
2397 #define EXTI_FTSR1_TR15_Pos        (15U)
2398 #define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
2399 #define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
2400 #define EXTI_FTSR1_TR16_Pos        (16U)
2401 #define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
2402 #define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
2403 #define EXTI_FTSR1_TR17_Pos        (17U)
2404 #define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
2405 #define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
2406 #define EXTI_FTSR1_TR20_Pos        (20U)
2407 #define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
2408 #define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
2409 #define EXTI_FTSR1_TR21_Pos        (21U)
2410 #define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
2411 #define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
2412 
2413 /******************  Bit definition for EXTI_SWIER1 register  ******************/
2414 #define EXTI_SWIER1_SWIER0_Pos     (0U)
2415 #define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
2416 #define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
2417 #define EXTI_SWIER1_SWIER1_Pos     (1U)
2418 #define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
2419 #define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
2420 #define EXTI_SWIER1_SWIER2_Pos     (2U)
2421 #define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
2422 #define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
2423 #define EXTI_SWIER1_SWIER3_Pos     (3U)
2424 #define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
2425 #define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
2426 #define EXTI_SWIER1_SWIER4_Pos     (4U)
2427 #define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
2428 #define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
2429 #define EXTI_SWIER1_SWIER5_Pos     (5U)
2430 #define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
2431 #define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
2432 #define EXTI_SWIER1_SWIER6_Pos     (6U)
2433 #define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
2434 #define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
2435 #define EXTI_SWIER1_SWIER7_Pos     (7U)
2436 #define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
2437 #define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
2438 #define EXTI_SWIER1_SWIER8_Pos     (8U)
2439 #define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
2440 #define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
2441 #define EXTI_SWIER1_SWIER9_Pos     (9U)
2442 #define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
2443 #define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
2444 #define EXTI_SWIER1_SWIER10_Pos    (10U)
2445 #define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
2446 #define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
2447 #define EXTI_SWIER1_SWIER11_Pos    (11U)
2448 #define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
2449 #define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
2450 #define EXTI_SWIER1_SWIER12_Pos    (12U)
2451 #define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
2452 #define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
2453 #define EXTI_SWIER1_SWIER13_Pos    (13U)
2454 #define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
2455 #define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
2456 #define EXTI_SWIER1_SWIER14_Pos    (14U)
2457 #define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
2458 #define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
2459 #define EXTI_SWIER1_SWIER15_Pos    (15U)
2460 #define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
2461 #define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
2462 #define EXTI_SWIER1_SWIER16_Pos    (16U)
2463 #define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
2464 #define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
2465 #define EXTI_SWIER1_SWIER17_Pos    (17U)
2466 #define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
2467 #define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
2468 #define EXTI_SWIER1_SWIER20_Pos    (20U)
2469 #define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
2470 #define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
2471 #define EXTI_SWIER1_SWIER21_Pos    (21U)
2472 #define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
2473 #define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
2474 
2475 /*******************  Bit definition for EXTI_RPR1 register  ******************/
2476 #define EXTI_RPR1_RPIF0_Pos          (0U)
2477 #define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
2478 #define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
2479 #define EXTI_RPR1_RPIF1_Pos          (1U)
2480 #define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
2481 #define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
2482 #define EXTI_RPR1_RPIF2_Pos          (2U)
2483 #define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
2484 #define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
2485 #define EXTI_RPR1_RPIF3_Pos          (3U)
2486 #define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
2487 #define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
2488 #define EXTI_RPR1_RPIF4_Pos          (4U)
2489 #define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
2490 #define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
2491 #define EXTI_RPR1_RPIF5_Pos          (5U)
2492 #define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
2493 #define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
2494 #define EXTI_RPR1_RPIF6_Pos          (6U)
2495 #define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
2496 #define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
2497 #define EXTI_RPR1_RPIF7_Pos          (7U)
2498 #define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
2499 #define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
2500 #define EXTI_RPR1_RPIF8_Pos          (8U)
2501 #define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
2502 #define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
2503 #define EXTI_RPR1_RPIF9_Pos          (9U)
2504 #define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
2505 #define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
2506 #define EXTI_RPR1_RPIF10_Pos         (10U)
2507 #define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
2508 #define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
2509 #define EXTI_RPR1_RPIF11_Pos         (11U)
2510 #define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
2511 #define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
2512 #define EXTI_RPR1_RPIF12_Pos         (12U)
2513 #define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
2514 #define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
2515 #define EXTI_RPR1_RPIF13_Pos         (13U)
2516 #define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
2517 #define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
2518 #define EXTI_RPR1_RPIF14_Pos         (14U)
2519 #define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
2520 #define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
2521 #define EXTI_RPR1_RPIF15_Pos         (15U)
2522 #define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
2523 #define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
2524 #define EXTI_RPR1_RPIF16_Pos         (16U)
2525 #define EXTI_RPR1_RPIF16_Msk         (0x1UL << EXTI_RPR1_RPIF16_Pos)           /*!< 0x00010000 */
2526 #define EXTI_RPR1_RPIF16             EXTI_RPR1_RPIF16_Msk                      /*!< Rising Pending Interrupt Flag on line 16 */
2527 #define EXTI_RPR1_RPIF17_Pos         (17U)
2528 #define EXTI_RPR1_RPIF17_Msk         (0x1UL << EXTI_RPR1_RPIF17_Pos)           /*!< 0x00020000 */
2529 #define EXTI_RPR1_RPIF17             EXTI_RPR1_RPIF17_Msk                      /*!< Rising Pending Interrupt Flag on line 17 */
2530 #define EXTI_RPR1_RPIF20_Pos         (20U)
2531 #define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00100000 */
2532 #define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
2533 #define EXTI_RPR1_RPIF21_Pos         (21U)
2534 #define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00200000 */
2535 #define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
2536 
2537 /*******************  Bit definition for EXTI_FPR1 register  ******************/
2538 #define EXTI_FPR1_FPIF0_Pos          (0U)
2539 #define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
2540 #define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
2541 #define EXTI_FPR1_FPIF1_Pos          (1U)
2542 #define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
2543 #define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
2544 #define EXTI_FPR1_FPIF2_Pos          (2U)
2545 #define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
2546 #define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
2547 #define EXTI_FPR1_FPIF3_Pos          (3U)
2548 #define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
2549 #define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
2550 #define EXTI_FPR1_FPIF4_Pos          (4U)
2551 #define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
2552 #define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
2553 #define EXTI_FPR1_FPIF5_Pos          (5U)
2554 #define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
2555 #define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
2556 #define EXTI_FPR1_FPIF6_Pos          (6U)
2557 #define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
2558 #define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
2559 #define EXTI_FPR1_FPIF7_Pos          (7U)
2560 #define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
2561 #define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
2562 #define EXTI_FPR1_FPIF8_Pos          (8U)
2563 #define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
2564 #define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
2565 #define EXTI_FPR1_FPIF9_Pos          (9U)
2566 #define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
2567 #define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
2568 #define EXTI_FPR1_FPIF10_Pos         (10U)
2569 #define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
2570 #define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
2571 #define EXTI_FPR1_FPIF11_Pos         (11U)
2572 #define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
2573 #define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
2574 #define EXTI_FPR1_FPIF12_Pos         (12U)
2575 #define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
2576 #define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
2577 #define EXTI_FPR1_FPIF13_Pos         (13U)
2578 #define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00020000 */
2579 #define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
2580 #define EXTI_FPR1_FPIF14_Pos         (14U)
2581 #define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00040000 */
2582 #define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
2583 #define EXTI_FPR1_FPIF15_Pos         (15U)
2584 #define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00080000 */
2585 #define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
2586 #define EXTI_FPR1_FPIF16_Pos         (16U)
2587 #define EXTI_FPR1_FPIF16_Msk         (0x1UL << EXTI_FPR1_FPIF16_Pos)           /*!< 0x00010000 */
2588 #define EXTI_FPR1_FPIF16             EXTI_FPR1_FPIF16_Msk                      /*!< Falling Pending Interrupt Flag on line 16 */
2589 #define EXTI_FPR1_FPIF17_Pos         (17U)
2590 #define EXTI_FPR1_FPIF17_Msk         (0x1UL << EXTI_FPR1_FPIF17_Pos)           /*!< 0x00020000 */
2591 #define EXTI_FPR1_FPIF17             EXTI_FPR1_FPIF17_Msk                      /*!< Falling Pending Interrupt Flag on line 17 */
2592 #define EXTI_FPR1_FPIF20_Pos         (20U)
2593 #define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00100000 */
2594 #define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
2595 #define EXTI_FPR1_FPIF21_Pos         (21U)
2596 #define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00200000 */
2597 #define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
2598 
2599 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
2600 #define EXTI_EXTICR1_EXTI0_Pos       (0U)
2601 #define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
2602 #define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
2603 #define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
2604 #define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
2605 #define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
2606 #define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
2607 #define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
2608 #define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
2609 #define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
2610 #define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
2611 #define EXTI_EXTICR1_EXTI1_Pos       (8U)
2612 #define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
2613 #define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
2614 #define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
2615 #define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
2616 #define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
2617 #define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
2618 #define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
2619 #define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
2620 #define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
2621 #define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
2622 #define EXTI_EXTICR1_EXTI2_Pos       (16U)
2623 #define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
2624 #define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
2625 #define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
2626 #define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
2627 #define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
2628 #define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
2629 #define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
2630 #define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
2631 #define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
2632 #define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
2633 #define EXTI_EXTICR1_EXTI3_Pos       (24U)
2634 #define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
2635 #define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
2636 #define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
2637 #define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
2638 #define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
2639 #define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
2640 #define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
2641 #define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
2642 #define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
2643 #define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
2644 
2645 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
2646 #define EXTI_EXTICR2_EXTI4_Pos       (0U)
2647 #define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
2648 #define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
2649 #define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
2650 #define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
2651 #define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
2652 #define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
2653 #define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
2654 #define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
2655 #define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
2656 #define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
2657 #define EXTI_EXTICR2_EXTI5_Pos       (8U)
2658 #define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
2659 #define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
2660 #define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
2661 #define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
2662 #define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
2663 #define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
2664 #define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
2665 #define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
2666 #define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
2667 #define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
2668 #define EXTI_EXTICR2_EXTI6_Pos       (16U)
2669 #define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
2670 #define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
2671 #define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
2672 #define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
2673 #define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
2674 #define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
2675 #define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
2676 #define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
2677 #define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
2678 #define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
2679 #define EXTI_EXTICR2_EXTI7_Pos       (24U)
2680 #define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
2681 #define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
2682 #define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
2683 #define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
2684 #define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
2685 #define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
2686 #define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
2687 #define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
2688 #define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
2689 #define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
2690 
2691 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
2692 #define EXTI_EXTICR3_EXTI8_Pos       (0U)
2693 #define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
2694 #define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
2695 #define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
2696 #define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
2697 #define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
2698 #define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
2699 #define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
2700 #define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
2701 #define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
2702 #define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
2703 #define EXTI_EXTICR3_EXTI9_Pos       (8U)
2704 #define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
2705 #define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
2706 #define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
2707 #define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
2708 #define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
2709 #define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
2710 #define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
2711 #define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
2712 #define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
2713 #define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
2714 #define EXTI_EXTICR3_EXTI10_Pos      (16U)
2715 #define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
2716 #define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
2717 #define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
2718 #define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
2719 #define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
2720 #define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
2721 #define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
2722 #define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
2723 #define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
2724 #define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
2725 #define EXTI_EXTICR3_EXTI11_Pos      (24U)
2726 #define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
2727 #define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
2728 #define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
2729 #define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
2730 #define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
2731 #define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
2732 #define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
2733 #define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
2734 #define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
2735 #define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
2736 
2737 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
2738 #define EXTI_EXTICR4_EXTI12_Pos      (0U)
2739 #define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
2740 #define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
2741 #define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
2742 #define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
2743 #define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
2744 #define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
2745 #define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
2746 #define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
2747 #define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
2748 #define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
2749 #define EXTI_EXTICR4_EXTI13_Pos      (8U)
2750 #define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
2751 #define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
2752 #define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
2753 #define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
2754 #define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
2755 #define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
2756 #define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
2757 #define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
2758 #define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
2759 #define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
2760 #define EXTI_EXTICR4_EXTI14_Pos      (16U)
2761 #define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
2762 #define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
2763 #define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
2764 #define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
2765 #define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
2766 #define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
2767 #define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
2768 #define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
2769 #define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
2770 #define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
2771 #define EXTI_EXTICR4_EXTI15_Pos      (24U)
2772 #define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
2773 #define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
2774 #define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
2775 #define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
2776 #define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
2777 #define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
2778 #define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
2779 #define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
2780 #define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
2781 #define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
2782 
2783 /*******************  Bit definition for EXTI_IMR1 register  *******************/
2784 #define EXTI_IMR1_IM_Pos           (0U)
2785 #define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
2786 #define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
2787 #define EXTI_IMR1_IM0_Pos          (0U)
2788 #define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
2789 #define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
2790 #define EXTI_IMR1_IM1_Pos          (1U)
2791 #define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
2792 #define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
2793 #define EXTI_IMR1_IM2_Pos          (2U)
2794 #define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
2795 #define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
2796 #define EXTI_IMR1_IM3_Pos          (3U)
2797 #define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
2798 #define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
2799 #define EXTI_IMR1_IM4_Pos          (4U)
2800 #define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
2801 #define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
2802 #define EXTI_IMR1_IM5_Pos          (5U)
2803 #define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
2804 #define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
2805 #define EXTI_IMR1_IM6_Pos          (6U)
2806 #define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
2807 #define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
2808 #define EXTI_IMR1_IM7_Pos          (7U)
2809 #define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
2810 #define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
2811 #define EXTI_IMR1_IM8_Pos          (8U)
2812 #define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
2813 #define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
2814 #define EXTI_IMR1_IM9_Pos          (9U)
2815 #define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
2816 #define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
2817 #define EXTI_IMR1_IM10_Pos         (10U)
2818 #define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
2819 #define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
2820 #define EXTI_IMR1_IM11_Pos         (11U)
2821 #define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
2822 #define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
2823 #define EXTI_IMR1_IM12_Pos         (12U)
2824 #define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
2825 #define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
2826 #define EXTI_IMR1_IM13_Pos         (13U)
2827 #define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
2828 #define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
2829 #define EXTI_IMR1_IM14_Pos         (14U)
2830 #define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
2831 #define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
2832 #define EXTI_IMR1_IM15_Pos         (15U)
2833 #define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
2834 #define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
2835 #define EXTI_IMR1_IM16_Pos         (16U)
2836 #define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
2837 #define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
2838 #define EXTI_IMR1_IM17_Pos         (17U)
2839 #define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
2840 #define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
2841 #define EXTI_IMR1_IM20_Pos         (20U)
2842 #define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
2843 #define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
2844 #define EXTI_IMR1_IM21_Pos         (21U)
2845 #define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
2846 #define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
2847 #define EXTI_IMR1_IM23_Pos         (23U)
2848 #define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
2849 #define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
2850 #define EXTI_IMR1_IM24_Pos         (24U)
2851 #define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
2852 #define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
2853 #define EXTI_IMR1_IM25_Pos         (25U)
2854 #define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
2855 #define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
2856 #define EXTI_IMR1_IM27_Pos         (27U)
2857 #define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
2858 #define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
2859 #define EXTI_IMR1_IM28_Pos         (28U)
2860 #define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
2861 #define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
2862 #define EXTI_IMR1_IM29_Pos         (29U)
2863 #define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
2864 #define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
2865 #define EXTI_IMR1_IM30_Pos         (30U)
2866 #define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
2867 #define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
2868 #define EXTI_IMR1_IM31_Pos         (31U)
2869 #define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
2870 #define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
2871 
2872 /*******************  Bit definition for EXTI_EMR1 register  *******************/
2873 #define EXTI_EMR1_EM_Pos           (0U)
2874 #define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
2875 #define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
2876 #define EXTI_EMR1_EM0_Pos          (0U)
2877 #define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
2878 #define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
2879 #define EXTI_EMR1_EM1_Pos          (1U)
2880 #define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
2881 #define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
2882 #define EXTI_EMR1_EM2_Pos          (2U)
2883 #define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
2884 #define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
2885 #define EXTI_EMR1_EM3_Pos          (3U)
2886 #define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
2887 #define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
2888 #define EXTI_EMR1_EM4_Pos          (4U)
2889 #define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
2890 #define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
2891 #define EXTI_EMR1_EM5_Pos          (5U)
2892 #define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
2893 #define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
2894 #define EXTI_EMR1_EM6_Pos          (6U)
2895 #define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
2896 #define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
2897 #define EXTI_EMR1_EM7_Pos          (7U)
2898 #define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
2899 #define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
2900 #define EXTI_EMR1_EM8_Pos          (8U)
2901 #define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
2902 #define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
2903 #define EXTI_EMR1_EM9_Pos          (9U)
2904 #define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
2905 #define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
2906 #define EXTI_EMR1_EM10_Pos         (10U)
2907 #define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
2908 #define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
2909 #define EXTI_EMR1_EM11_Pos         (11U)
2910 #define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
2911 #define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
2912 #define EXTI_EMR1_EM12_Pos         (12U)
2913 #define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
2914 #define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
2915 #define EXTI_EMR1_EM13_Pos         (13U)
2916 #define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
2917 #define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
2918 #define EXTI_EMR1_EM14_Pos         (14U)
2919 #define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
2920 #define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
2921 #define EXTI_EMR1_EM15_Pos         (15U)
2922 #define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
2923 #define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
2924 #define EXTI_EMR1_EM16_Pos         (16U)
2925 #define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
2926 #define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
2927 #define EXTI_EMR1_EM17_Pos         (17U)
2928 #define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
2929 #define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
2930 #define EXTI_EMR1_EM20_Pos         (20U)
2931 #define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
2932 #define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
2933 #define EXTI_EMR1_EM21_Pos         (21U)
2934 #define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
2935 #define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
2936 #define EXTI_EMR1_EM23_Pos         (23U)
2937 #define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
2938 #define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
2939 #define EXTI_EMR1_EM24_Pos         (24U)
2940 #define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
2941 #define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
2942 #define EXTI_EMR1_EM25_Pos         (25U)
2943 #define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
2944 #define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
2945 #define EXTI_EMR1_EM27_Pos         (27U)
2946 #define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
2947 #define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
2948 #define EXTI_EMR1_EM28_Pos         (28U)
2949 #define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
2950 #define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
2951 #define EXTI_EMR1_EM29_Pos         (29U)
2952 #define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
2953 #define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
2954 #define EXTI_EMR1_EM30_Pos         (30U)
2955 #define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
2956 #define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
2957 #define EXTI_EMR1_EM31_Pos         (31U)
2958 #define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
2959 #define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
2960 
2961 /*******************  Bit definition for EXTI_IMR2 register  *******************/
2962 #define EXTI_IMR2_IM_Pos           (0U)
2963 #define EXTI_IMR2_IM_Msk           (0x0000003FUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */
2964 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */
2965 #define EXTI_IMR2_IM33_Pos         (1U)
2966 #define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
2967 #define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
2968 #define EXTI_IMR2_IM34_Pos         (2U)
2969 #define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
2970 #define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
2971 #define EXTI_IMR2_IM35_Pos         (3U)
2972 #define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
2973 #define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
2974 #define EXTI_IMR2_IM37_Pos         (5U)
2975 #define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
2976 #define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
2977 
2978 /*******************  Bit definition for EXTI_EMR2 register  *******************/
2979 #define EXTI_EMR2_EM_Pos           (0U)
2980 #define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */
2981 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */
2982 #define EXTI_EMR2_EM33_Pos         (1U)
2983 #define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
2984 #define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
2985 #define EXTI_EMR2_EM34_Pos         (2U)
2986 #define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
2987 #define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
2988 #define EXTI_EMR2_EM35_Pos         (3U)
2989 #define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
2990 #define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
2991 #define EXTI_EMR2_EM37_Pos         (5U)
2992 #define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
2993 #define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
2994 
2995 /******************************************************************************/
2996 /*                                                                            */
2997 /*                                    FLASH                                   */
2998 /*                                                                            */
2999 /******************************************************************************/
3000 
3001 /*******************  Bits definition for FLASH_ACR register  *****************/
3002 #define FLASH_ACR_LATENCY_Pos               (0U)
3003 #define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
3004 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk
3005 #define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
3006 #define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
3007 #define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
3008 #define FLASH_ACR_LATENCY_0WS               (0x00000000U)
3009 #define FLASH_ACR_LATENCY_1WS               (0x00000001U)
3010 #define FLASH_ACR_LATENCY_2WS               (0x00000002U)
3011 #define FLASH_ACR_LATENCY_3WS               (0x00000003U)
3012 #define FLASH_ACR_LATENCY_4WS               (0x00000004U)
3013 #define FLASH_ACR_LATENCY_5WS               (0x00000005U)
3014 #define FLASH_ACR_LATENCY_6WS               (0x00000006U)
3015 #define FLASH_ACR_LATENCY_7WS               (0x00000007U)
3016 #define FLASH_ACR_PRFTEN_Pos                (8U)
3017 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)     /*!< 0x00000100 */
3018 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk
3019 #define FLASH_ACR_ICEN_Pos                  (9U)
3020 #define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)       /*!< 0x00000200 */
3021 #define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk
3022 #define FLASH_ACR_ICRST_Pos                 (11U)
3023 #define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)      /*!< 0x00000800 */
3024 #define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk
3025 #define FLASH_ACR_EMPTY_Pos                 (16U)
3026 #define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)      /*!< 0x00010000 */
3027 #define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk
3028 #define FLASH_ACR_DBG_SWEN_Pos              (18U)
3029 #define FLASH_ACR_DBG_SWEN_Msk              (0x1UL << FLASH_ACR_DBG_SWEN_Pos)   /*!< 0x00040000 */
3030 #define FLASH_ACR_DBG_SWEN                  FLASH_ACR_DBG_SWEN_Msk
3031 
3032 /*******************  Bits definition for FLASH_SR register  ******************/
3033 #define FLASH_SR_EOP_Pos                    (0U)
3034 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)             /*!< 0x00000001 */
3035 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk
3036 #define FLASH_SR_OPERR_Pos                  (1U)
3037 #define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)           /*!< 0x00000002 */
3038 #define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk
3039 #define FLASH_SR_PROGERR_Pos                (3U)
3040 #define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)         /*!< 0x00000008 */
3041 #define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk
3042 #define FLASH_SR_WRPERR_Pos                 (4U)
3043 #define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)          /*!< 0x00000010 */
3044 #define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk
3045 #define FLASH_SR_PGAERR_Pos                 (5U)
3046 #define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)          /*!< 0x00000020 */
3047 #define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk
3048 #define FLASH_SR_SIZERR_Pos                 (6U)
3049 #define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)          /*!< 0x00000040 */
3050 #define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk
3051 #define FLASH_SR_PGSERR_Pos                 (7U)
3052 #define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)          /*!< 0x00000080 */
3053 #define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk
3054 #define FLASH_SR_MISERR_Pos                 (8U)
3055 #define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)          /*!< 0x00000100 */
3056 #define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk
3057 #define FLASH_SR_FASTERR_Pos                (9U)
3058 #define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)         /*!< 0x00000200 */
3059 #define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk
3060 #define FLASH_SR_HDPOPTWERR_Pos             (11U)
3061 #define FLASH_SR_HDPOPTWERRR_Msk            (0x1UL << FLASH_SR_HDPOPTWERR_Pos)      /*!< 0x00000800 */
3062 #define FLASH_SR_HDPOPTWERR                 FLASH_SR_HDPOPTWERR_Msk
3063 #define FLASH_SR_OEMOPTWERR_Pos             (12U)
3064 #define FLASH_SR_OEMOPTWERR_Msk             (0x1UL << FLASH_SR_OEMOPTWERR_Pos)      /*!< 0x00001000 */
3065 #define FLASH_SR_OEMOPTWERR                 FLASH_SR_OEMOPTWERR_Msk
3066 #define FLASH_SR_OPTVERR_Pos                (15U)
3067 #define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)         /*!< 0x00008000 */
3068 #define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk
3069 #define FLASH_SR_BSY1_Pos                   (16U)
3070 #define FLASH_SR_BSY1_Msk                   (0x1UL << FLASH_SR_BSY1_Pos)            /*!< 0x00010000 */
3071 #define FLASH_SR_BSY1                       FLASH_SR_BSY1_Msk
3072 #define FLASH_SR_CFGBSY_Pos                 (18U)
3073 #define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)          /*!< 0x00040000 */
3074 #define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk
3075 #define FLASH_SR_OEM1LOCK_POS               (20U)
3076 #define FLASH_SR_OEM1LOCK_Msk               (0x1UL << FLASH_SR_OEM1LOCK_POS)        /*!< 0x00100000 */
3077 #define FLASH_SR_OEM1LOCK                   FLASH_SR_OEM1LOCK_Msk
3078 #define FLASH_SR_OEM2LOCK_POS               (21U)
3079 #define FLASH_SR_OEM2LOCK_Msk               (0x1UL << FLASH_SR_OEM2LOCK_POS)        /*!< 0x00200000 */
3080 #define FLASH_SR_OEM2LOCK                   FLASH_SR_OEM2LOCK_Msk
3081 
3082 /*******************  Bits definition for FLASH_CR register  ******************/
3083 #define FLASH_CR_PG_Pos                     (0U)
3084 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)              /*!< 0x00000001 */
3085 #define FLASH_CR_PG                         FLASH_CR_PG_Msk
3086 #define FLASH_CR_PER_Pos                    (1U)
3087 #define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)             /*!< 0x00000002 */
3088 #define FLASH_CR_PER                        FLASH_CR_PER_Msk
3089 #define FLASH_CR_MER1_Pos                   (2U)
3090 #define FLASH_CR_MER1_Msk                   (0x1UL << FLASH_CR_MER1_Pos)            /*!< 0x00000004 */
3091 #define FLASH_CR_MER1                       FLASH_CR_MER1_Msk
3092 #define FLASH_CR_PNB_Pos                    (3U)
3093 #define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)            /*!< 0x000003F8 */
3094 #define FLASH_CR_PNB                        FLASH_CR_PNB_Msk
3095 #define FLASH_CR_STRT_Pos                   (16U)
3096 #define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)            /*!< 0x00010000 */
3097 #define FLASH_CR_STRT                       FLASH_CR_STRT_Msk
3098 #define FLASH_CR_OPTSTRT_Pos                (17U)
3099 #define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)         /*!< 0x00020000 */
3100 #define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk
3101 #define FLASH_CR_FSTPG_Pos                  (18U)
3102 #define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)           /*!< 0x00040000 */
3103 #define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk
3104 #define FLASH_CR_EOPIE_Pos                  (24U)
3105 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)           /*!< 0x01000000 */
3106 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk
3107 #define FLASH_CR_ERRIE_Pos                  (25U)
3108 #define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)           /*!< 0x02000000 */
3109 #define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk
3110 
3111 #define FLASH_CR_OBL_LAUNCH_Pos             (27U)
3112 #define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)      /*!< 0x08000000 */
3113 #define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk
3114 #define FLASH_CR_OPTLOCK_Pos                (30U)
3115 #define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)         /*!< 0x40000000 */
3116 #define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk
3117 #define FLASH_CR_LOCK_Pos                   (31U)
3118 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)            /*!< 0x80000000 */
3119 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk
3120 
3121 /*******************  Bits definition for FLASH_ECCR register  ****************/
3122 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
3123 #define FLASH_ECCR_ADDR_ECC_Msk             (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos)   /*!< 0x00003FFF */
3124 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk
3125 #define FLASH_ECCR_SYSF_ECC_Pos             (20U)
3126 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)      /*!< 0x00100000 */
3127 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk
3128 #define FLASH_ECCR_ECCCIE_Pos               (24U)
3129 #define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)        /*!< 0x01000000 */
3130 #define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk
3131 #define FLASH_ECCR_ECCC_Pos                 (30U)
3132 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)          /*!< 0x40000000 */
3133 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk
3134 #define FLASH_ECCR_ECCD_Pos                 (31U)
3135 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)          /*!< 0x80000000 */
3136 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk
3137 
3138 /*******************  Bits definition for FLASH_OPTR register  ****************/
3139 #define FLASH_OPTR_RDP_Pos                  (0U)
3140 #define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)            /*!< 0x000000FF */
3141 #define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk
3142 #define FLASH_OPTR_BOR_EN_Pos               (8U)
3143 #define FLASH_OPTR_BOR_EN_Msk               (0x1UL << FLASH_OPTR_BOR_EN_Pos)           /*!< 0x00000100 */
3144 #define FLASH_OPTR_BOR_EN                   FLASH_OPTR_BOR_EN_Msk
3145 #define FLASH_OPTR_BORR_LEV_Pos             (9U)
3146 #define FLASH_OPTR_BORR_LEV_Msk             (0x3UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000600 */
3147 #define FLASH_OPTR_BORR_LEV                 FLASH_OPTR_BORR_LEV_Msk
3148 #define FLASH_OPTR_BORR_LEV_0               (0x1UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000200 */
3149 #define FLASH_OPTR_BORR_LEV_1               (0x2UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000400 */
3150 #define FLASH_OPTR_BORF_LEV_Pos             (11U)
3151 #define FLASH_OPTR_BORF_LEV_Msk             (0x3UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001800 */
3152 #define FLASH_OPTR_BORF_LEV                 FLASH_OPTR_BORF_LEV_Msk
3153 #define FLASH_OPTR_BORF_LEV_0               (0x1UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00000800 */
3154 #define FLASH_OPTR_BORF_LEV_1               (0x2UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001000 */
3155 #define FLASH_OPTR_nRST_STOP_Pos            (13U)
3156 #define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00002000 */
3157 #define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk
3158 #define FLASH_OPTR_nRST_STDBY_Pos           (14U)
3159 #define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00004000 */
3160 #define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk
3161 #define FLASH_OPTR_nRST_SHDW_Pos            (15U)
3162 #define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)        /*!< 0x00008000 */
3163 #define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk
3164 #define FLASH_OPTR_IWDG_SW_Pos              (16U)
3165 #define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00010000 */
3166 #define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk
3167 #define FLASH_OPTR_IWDG_STOP_Pos            (17U)
3168 #define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)        /*!< 0x00020000 */
3169 #define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk
3170 #define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
3171 #define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)       /*!< 0x00040000 */
3172 #define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk
3173 #define FLASH_OPTR_WWDG_SW_Pos              (19U)
3174 #define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)          /*!< 0x00080000 */
3175 #define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk
3176 #define FLASH_OPTR_BDRST_Pos                (21U)
3177 #define FLASH_OPTR_BDRST_Msk                (0x1UL << FLASH_OPTR_BDRST_Pos)            /*!< 0x00200000 */
3178 #define FLASH_OPTR_BDRST                    FLASH_OPTR_BDRST_Msk
3179 #define FLASH_OPTR_RAM_PARITY_CHECK_Pos     (22U)
3180 #define FLASH_OPTR_RAM_PARITY_CHECK_Msk     (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
3181 #define FLASH_OPTR_RAM_PARITY_CHECK         FLASH_OPTR_RAM_PARITY_CHECK_Msk
3182 #define FLASH_OPTR_BKPSRAM_HW_ERASE_Pos     (23U)
3183 #define FLASH_OPTR_BKPSRAM_HW_ERASE_Msk     (0x1UL << FLASH_OPTR_BKPSRAM_HW_ERASE_Pos) /*!< 0x00800000 */
3184 #define FLASH_OPTR_BKPSRAM_HW_ERASE         FLASH_OPTR_BKPSRAM_HW_ERASE_Msk
3185 #define FLASH_OPTR_nBOOT_SEL_Pos            (24U)
3186 #define FLASH_OPTR_nBOOT_SEL_Msk            (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)        /*!< 0x01000000 */
3187 #define FLASH_OPTR_nBOOT_SEL                FLASH_OPTR_nBOOT_SEL_Msk
3188 #define FLASH_OPTR_nBOOT1_Pos               (25U)
3189 #define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)           /*!< 0x02000000 */
3190 #define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk
3191 #define FLASH_OPTR_nBOOT0_Pos               (26U)
3192 #define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)           /*!< 0x04000000 */
3193 #define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk
3194 #define FLASH_OPTR_NRST_MODE_Pos            (27U)
3195 #define FLASH_OPTR_NRST_MODE_Msk            (0x3UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x18000000 */
3196 #define FLASH_OPTR_NRST_MODE                FLASH_OPTR_NRST_MODE_Msk
3197 #define FLASH_OPTR_NRST_MODE_0              (0x1UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x08000000 */
3198 #define FLASH_OPTR_NRST_MODE_1              (0x2UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x10000000 */
3199 #define FLASH_OPTR_IRHEN_Pos                (29U)
3200 #define FLASH_OPTR_IRHEN_Msk                (0x1UL << FLASH_OPTR_IRHEN_Pos)            /*!< 0x20000000 */
3201 #define FLASH_OPTR_IRHEN                    FLASH_OPTR_IRHEN_Msk
3202 
3203 
3204 /******************  Bits definition for FLASH_WRP1AR register  ***************/
3205 #define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
3206 #define FLASH_WRP1AR_WRP1A_STRT_Msk         (0xFFFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000FFFF */
3207 #define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk
3208 #define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
3209 #define FLASH_WRP1AR_WRP1A_END_Msk          (0xFFFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0xFFFF0000 */
3210 #define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk
3211 
3212 /******************  Bits definition for FLASH_WRP1BR register  ***************/
3213 #define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
3214 #define FLASH_WRP1BR_WRP1B_STRT_Msk         (0xFFFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000FFFF */
3215 #define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk
3216 #define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
3217 #define FLASH_WRP1BR_WRP1B_END_Msk          (0xFFFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0xFFFF0000 */
3218 #define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk
3219 
3220 
3221 /******************  Bits definition for FLASH_SECR register  *****************/
3222 #define FLASH_SECR_HDP1_PEND_Pos            (0U)
3223 #define FLASH_SECR_HDP1_PEND_Msk            (0x3FUL << FLASH_SECR_HDP1_PEND_Pos)    /*!< 0x0000003F */
3224 #define FLASH_SECR_HDP1_PEND                FLASH_SECR_HDP1_PEND_Msk
3225 #define FLASH_SECR_BOOT_LOCK_Pos            (16U)
3226 #define FLASH_SECR_BOOT_LOCK_Msk            (0x1UL << FLASH_SECR_BOOT_LOCK_Pos)       /*!< 0x00010000 */
3227 #define FLASH_SECR_BOOT_LOCK                FLASH_SECR_BOOT_LOCK_Msk
3228 #define FLASH_SECR_HDP1EN_Pos               (24U)
3229 #define FLASH_SECR_HDP1EN_Msk               (0xFFUL << FLASH_SECR_HDP1EN_Pos)       /*!< 0xFF000000 */
3230 #define FLASH_SECR_HDP1EN                   FLASH_SECR_HDP1EN_Msk
3231 
3232 /******************  Bits definition for FLASH_OEMKEYSR register  *****************/
3233 #define FLASH_OEMKEYSR_OEM1KEYCRC_Pos       (0U)
3234 #define FLASH_OEMKEYSR_OEM1KEYCRC_Msk       (0xFFUL << FLASH_OEMKEYSR_OEM1KEYCRC_Pos)     /*!< 0x000000FF */
3235 #define FLASH_OEMKEYSR_OEM1KEYCRC           FLASH_OEMKEYSR_OEM1KEYCRC_Msk
3236 #define FLASH_OEMKEYSR_OEM2KEYCRC_Pos       (16U)
3237 #define FLASH_OEMKEYSR_OEM2KEYCRC_Msk       (0xFFUL << FLASH_OEMKEYSR_OEM2KEYCRC_Pos)     /*!< 0x00FF0000 */
3238 #define FLASH_OEMKEYSR_OEM2KEYCRC           FLASH_OEMKEYSR_OEM2KEYCRC_Msk
3239 
3240 /******************  Bits definition for FLASH_HDPCR register  *****************/
3241 #define FLASH_HDPCR_HDP1_ACCDIS_Pos         (0U)
3242 #define FLASH_HDPCR_HDP1_ACCDIS_Msk         (0xFFUL << FLASH_HDPCR_HDP1_ACCDIS_Pos)     /*!< 0x000000FF */
3243 #define FLASH_HDPCR_HDP1_ACCDIS             FLASH_HDPCR_HDP1_ACCDIS_Msk
3244 #define FLASH_HDPCR_HDP1EXT_ACCDIS_Pos      (16U)
3245 #define FLASH_HDPCR_HDP1EXT_ACCDIS_Msk      (0xFFUL << FLASH_HDPCR_HDP1EXT_ACCDIS_Pos)     /*!< 0x000000FF */
3246 #define FLASH_HDPCR_HDP1EXT_ACCDIS          FLASH_HDPCR_HDP1EXT_ACCDIS_Msk
3247 
3248 /******************  Bits definition for FLASH_HDPEXTR register  *****************/
3249 #define FLASH_HDPEXTR_HDP1_EXT_Pos          (0U)
3250 #define FLASH_HDPEXTR_HDP1_EXT_Msk          (0x3FUL << FLASH_HDPEXTR_HDP1_EXT_Pos)     /*!< 0x0000003F */
3251 #define FLASH_HDPEXTR_HDP1_EXT              FLASH_HDPEXTR_HDP1_EXT_Msk
3252 
3253 /******************************************************************************/
3254 /*                                                                            */
3255 /*                            General Purpose I/O                             */
3256 /*                                                                            */
3257 /******************************************************************************/
3258 /******************  Bits definition for GPIO_MODER register  *****************/
3259 #define GPIO_MODER_MODE0_Pos           (0U)
3260 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
3261 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
3262 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
3263 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
3264 
3265 #define GPIO_MODER_MODE1_Pos           (2U)
3266 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
3267 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
3268 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
3269 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
3270 
3271 #define GPIO_MODER_MODE2_Pos           (4U)
3272 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
3273 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
3274 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
3275 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
3276 
3277 #define GPIO_MODER_MODE3_Pos           (6U)
3278 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
3279 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
3280 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
3281 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
3282 
3283 #define GPIO_MODER_MODE4_Pos           (8U)
3284 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
3285 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
3286 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
3287 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
3288 
3289 #define GPIO_MODER_MODE5_Pos           (10U)
3290 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
3291 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
3292 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
3293 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
3294 
3295 #define GPIO_MODER_MODE6_Pos           (12U)
3296 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
3297 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
3298 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
3299 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
3300 
3301 #define GPIO_MODER_MODE7_Pos           (14U)
3302 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
3303 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
3304 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
3305 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
3306 
3307 #define GPIO_MODER_MODE8_Pos           (16U)
3308 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
3309 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
3310 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
3311 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
3312 
3313 #define GPIO_MODER_MODE9_Pos           (18U)
3314 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
3315 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
3316 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
3317 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
3318 
3319 #define GPIO_MODER_MODE10_Pos          (20U)
3320 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
3321 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
3322 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
3323 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
3324 
3325 #define GPIO_MODER_MODE11_Pos          (22U)
3326 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
3327 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
3328 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
3329 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
3330 
3331 #define GPIO_MODER_MODE12_Pos          (24U)
3332 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
3333 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
3334 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
3335 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
3336 
3337 #define GPIO_MODER_MODE13_Pos          (26U)
3338 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
3339 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
3340 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
3341 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
3342 
3343 #define GPIO_MODER_MODE14_Pos          (28U)
3344 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
3345 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
3346 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
3347 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
3348 
3349 #define GPIO_MODER_MODE15_Pos          (30U)
3350 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
3351 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
3352 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
3353 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
3354 
3355 /******************  Bits definition for GPIO_OTYPER register  ****************/
3356 #define GPIO_OTYPER_OT0_Pos            (0U)
3357 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
3358 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
3359 #define GPIO_OTYPER_OT1_Pos            (1U)
3360 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
3361 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
3362 #define GPIO_OTYPER_OT2_Pos            (2U)
3363 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
3364 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
3365 #define GPIO_OTYPER_OT3_Pos            (3U)
3366 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
3367 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
3368 #define GPIO_OTYPER_OT4_Pos            (4U)
3369 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
3370 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
3371 #define GPIO_OTYPER_OT5_Pos            (5U)
3372 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
3373 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
3374 #define GPIO_OTYPER_OT6_Pos            (6U)
3375 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
3376 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
3377 #define GPIO_OTYPER_OT7_Pos            (7U)
3378 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
3379 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
3380 #define GPIO_OTYPER_OT8_Pos            (8U)
3381 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
3382 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3383 #define GPIO_OTYPER_OT9_Pos            (9U)
3384 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
3385 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3386 #define GPIO_OTYPER_OT10_Pos           (10U)
3387 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
3388 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3389 #define GPIO_OTYPER_OT11_Pos           (11U)
3390 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
3391 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3392 #define GPIO_OTYPER_OT12_Pos           (12U)
3393 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
3394 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3395 #define GPIO_OTYPER_OT13_Pos           (13U)
3396 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
3397 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3398 #define GPIO_OTYPER_OT14_Pos           (14U)
3399 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
3400 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3401 #define GPIO_OTYPER_OT15_Pos           (15U)
3402 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
3403 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3404 
3405 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3406 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3407 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
3408 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3409 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
3410 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
3411 
3412 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3413 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
3414 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3415 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
3416 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
3417 
3418 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3419 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
3420 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3421 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
3422 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
3423 
3424 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3425 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
3426 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3427 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
3428 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
3429 
3430 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3431 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
3432 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3433 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
3434 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
3435 
3436 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3437 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
3438 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3439 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
3440 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
3441 
3442 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3443 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
3444 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3445 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
3446 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
3447 
3448 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3449 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
3450 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3451 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
3452 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
3453 
3454 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3455 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
3456 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3457 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
3458 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
3459 
3460 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
3461 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
3462 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
3463 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
3464 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
3465 
3466 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
3467 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
3468 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
3469 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
3470 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
3471 
3472 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
3473 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
3474 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
3475 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
3476 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
3477 
3478 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
3479 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
3480 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
3481 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
3482 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
3483 
3484 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
3485 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
3486 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
3487 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
3488 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
3489 
3490 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
3491 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
3492 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
3493 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
3494 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
3495 
3496 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
3497 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
3498 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
3499 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
3500 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
3501 
3502 /******************  Bits definition for GPIO_PUPDR register  *****************/
3503 #define GPIO_PUPDR_PUPD0_Pos           (0U)
3504 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
3505 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
3506 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
3507 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
3508 
3509 #define GPIO_PUPDR_PUPD1_Pos           (2U)
3510 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
3511 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
3512 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
3513 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
3514 
3515 #define GPIO_PUPDR_PUPD2_Pos           (4U)
3516 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
3517 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
3518 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
3519 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
3520 
3521 #define GPIO_PUPDR_PUPD3_Pos           (6U)
3522 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
3523 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
3524 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
3525 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
3526 
3527 #define GPIO_PUPDR_PUPD4_Pos           (8U)
3528 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
3529 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
3530 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
3531 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
3532 
3533 #define GPIO_PUPDR_PUPD5_Pos           (10U)
3534 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
3535 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
3536 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
3537 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
3538 
3539 #define GPIO_PUPDR_PUPD6_Pos           (12U)
3540 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
3541 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
3542 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
3543 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
3544 
3545 #define GPIO_PUPDR_PUPD7_Pos           (14U)
3546 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
3547 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
3548 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
3549 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
3550 
3551 #define GPIO_PUPDR_PUPD8_Pos           (16U)
3552 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
3553 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
3554 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
3555 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
3556 
3557 #define GPIO_PUPDR_PUPD9_Pos           (18U)
3558 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
3559 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
3560 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
3561 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
3562 
3563 #define GPIO_PUPDR_PUPD10_Pos          (20U)
3564 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
3565 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
3566 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
3567 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
3568 
3569 #define GPIO_PUPDR_PUPD11_Pos          (22U)
3570 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
3571 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
3572 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
3573 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
3574 
3575 #define GPIO_PUPDR_PUPD12_Pos          (24U)
3576 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
3577 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
3578 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
3579 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
3580 
3581 #define GPIO_PUPDR_PUPD13_Pos          (26U)
3582 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
3583 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
3584 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
3585 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
3586 
3587 #define GPIO_PUPDR_PUPD14_Pos          (28U)
3588 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
3589 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
3590 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
3591 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
3592 
3593 #define GPIO_PUPDR_PUPD15_Pos          (30U)
3594 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
3595 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
3596 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
3597 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
3598 
3599 /******************  Bits definition for GPIO_IDR register  *******************/
3600 #define GPIO_IDR_ID0_Pos               (0U)
3601 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
3602 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
3603 #define GPIO_IDR_ID1_Pos               (1U)
3604 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
3605 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
3606 #define GPIO_IDR_ID2_Pos               (2U)
3607 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
3608 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
3609 #define GPIO_IDR_ID3_Pos               (3U)
3610 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
3611 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
3612 #define GPIO_IDR_ID4_Pos               (4U)
3613 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
3614 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
3615 #define GPIO_IDR_ID5_Pos               (5U)
3616 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
3617 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
3618 #define GPIO_IDR_ID6_Pos               (6U)
3619 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
3620 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
3621 #define GPIO_IDR_ID7_Pos               (7U)
3622 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
3623 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
3624 #define GPIO_IDR_ID8_Pos               (8U)
3625 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
3626 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
3627 #define GPIO_IDR_ID9_Pos               (9U)
3628 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
3629 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
3630 #define GPIO_IDR_ID10_Pos              (10U)
3631 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
3632 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
3633 #define GPIO_IDR_ID11_Pos              (11U)
3634 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
3635 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
3636 #define GPIO_IDR_ID12_Pos              (12U)
3637 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
3638 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
3639 #define GPIO_IDR_ID13_Pos              (13U)
3640 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
3641 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
3642 #define GPIO_IDR_ID14_Pos              (14U)
3643 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
3644 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
3645 #define GPIO_IDR_ID15_Pos              (15U)
3646 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
3647 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
3648 
3649 /******************  Bits definition for GPIO_ODR register  *******************/
3650 #define GPIO_ODR_OD0_Pos               (0U)
3651 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
3652 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
3653 #define GPIO_ODR_OD1_Pos               (1U)
3654 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
3655 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
3656 #define GPIO_ODR_OD2_Pos               (2U)
3657 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
3658 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
3659 #define GPIO_ODR_OD3_Pos               (3U)
3660 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
3661 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
3662 #define GPIO_ODR_OD4_Pos               (4U)
3663 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
3664 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
3665 #define GPIO_ODR_OD5_Pos               (5U)
3666 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
3667 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
3668 #define GPIO_ODR_OD6_Pos               (6U)
3669 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
3670 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
3671 #define GPIO_ODR_OD7_Pos               (7U)
3672 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
3673 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
3674 #define GPIO_ODR_OD8_Pos               (8U)
3675 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
3676 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
3677 #define GPIO_ODR_OD9_Pos               (9U)
3678 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
3679 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
3680 #define GPIO_ODR_OD10_Pos              (10U)
3681 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
3682 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
3683 #define GPIO_ODR_OD11_Pos              (11U)
3684 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
3685 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
3686 #define GPIO_ODR_OD12_Pos              (12U)
3687 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
3688 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
3689 #define GPIO_ODR_OD13_Pos              (13U)
3690 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
3691 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
3692 #define GPIO_ODR_OD14_Pos              (14U)
3693 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
3694 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
3695 #define GPIO_ODR_OD15_Pos              (15U)
3696 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
3697 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
3698 
3699 /******************  Bits definition for GPIO_BSRR register  ******************/
3700 #define GPIO_BSRR_BS0_Pos              (0U)
3701 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
3702 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
3703 #define GPIO_BSRR_BS1_Pos              (1U)
3704 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
3705 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
3706 #define GPIO_BSRR_BS2_Pos              (2U)
3707 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
3708 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
3709 #define GPIO_BSRR_BS3_Pos              (3U)
3710 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
3711 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
3712 #define GPIO_BSRR_BS4_Pos              (4U)
3713 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
3714 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
3715 #define GPIO_BSRR_BS5_Pos              (5U)
3716 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
3717 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
3718 #define GPIO_BSRR_BS6_Pos              (6U)
3719 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
3720 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
3721 #define GPIO_BSRR_BS7_Pos              (7U)
3722 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
3723 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
3724 #define GPIO_BSRR_BS8_Pos              (8U)
3725 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
3726 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
3727 #define GPIO_BSRR_BS9_Pos              (9U)
3728 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
3729 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
3730 #define GPIO_BSRR_BS10_Pos             (10U)
3731 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
3732 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
3733 #define GPIO_BSRR_BS11_Pos             (11U)
3734 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
3735 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
3736 #define GPIO_BSRR_BS12_Pos             (12U)
3737 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
3738 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
3739 #define GPIO_BSRR_BS13_Pos             (13U)
3740 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
3741 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
3742 #define GPIO_BSRR_BS14_Pos             (14U)
3743 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
3744 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
3745 #define GPIO_BSRR_BS15_Pos             (15U)
3746 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
3747 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
3748 #define GPIO_BSRR_BR0_Pos              (16U)
3749 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
3750 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
3751 #define GPIO_BSRR_BR1_Pos              (17U)
3752 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
3753 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
3754 #define GPIO_BSRR_BR2_Pos              (18U)
3755 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
3756 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
3757 #define GPIO_BSRR_BR3_Pos              (19U)
3758 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
3759 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
3760 #define GPIO_BSRR_BR4_Pos              (20U)
3761 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
3762 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
3763 #define GPIO_BSRR_BR5_Pos              (21U)
3764 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
3765 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
3766 #define GPIO_BSRR_BR6_Pos              (22U)
3767 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
3768 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
3769 #define GPIO_BSRR_BR7_Pos              (23U)
3770 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
3771 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
3772 #define GPIO_BSRR_BR8_Pos              (24U)
3773 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
3774 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
3775 #define GPIO_BSRR_BR9_Pos              (25U)
3776 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
3777 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
3778 #define GPIO_BSRR_BR10_Pos             (26U)
3779 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
3780 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
3781 #define GPIO_BSRR_BR11_Pos             (27U)
3782 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
3783 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
3784 #define GPIO_BSRR_BR12_Pos             (28U)
3785 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
3786 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
3787 #define GPIO_BSRR_BR13_Pos             (29U)
3788 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
3789 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
3790 #define GPIO_BSRR_BR14_Pos             (30U)
3791 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
3792 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
3793 #define GPIO_BSRR_BR15_Pos             (31U)
3794 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
3795 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
3796 
3797 /****************** Bit definition for GPIO_LCKR register *********************/
3798 #define GPIO_LCKR_LCK0_Pos             (0U)
3799 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
3800 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
3801 #define GPIO_LCKR_LCK1_Pos             (1U)
3802 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
3803 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
3804 #define GPIO_LCKR_LCK2_Pos             (2U)
3805 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
3806 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
3807 #define GPIO_LCKR_LCK3_Pos             (3U)
3808 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
3809 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
3810 #define GPIO_LCKR_LCK4_Pos             (4U)
3811 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
3812 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
3813 #define GPIO_LCKR_LCK5_Pos             (5U)
3814 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
3815 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
3816 #define GPIO_LCKR_LCK6_Pos             (6U)
3817 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
3818 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
3819 #define GPIO_LCKR_LCK7_Pos             (7U)
3820 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
3821 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
3822 #define GPIO_LCKR_LCK8_Pos             (8U)
3823 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
3824 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
3825 #define GPIO_LCKR_LCK9_Pos             (9U)
3826 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
3827 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
3828 #define GPIO_LCKR_LCK10_Pos            (10U)
3829 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
3830 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
3831 #define GPIO_LCKR_LCK11_Pos            (11U)
3832 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
3833 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
3834 #define GPIO_LCKR_LCK12_Pos            (12U)
3835 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
3836 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
3837 #define GPIO_LCKR_LCK13_Pos            (13U)
3838 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
3839 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
3840 #define GPIO_LCKR_LCK14_Pos            (14U)
3841 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
3842 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
3843 #define GPIO_LCKR_LCK15_Pos            (15U)
3844 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
3845 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
3846 #define GPIO_LCKR_LCKK_Pos             (16U)
3847 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
3848 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
3849 
3850 /****************** Bit definition for GPIO_AFRL register  ********************/
3851 #define GPIO_AFRL_AFSEL0_Pos           (0U)
3852 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
3853 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
3854 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
3855 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
3856 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
3857 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
3858 #define GPIO_AFRL_AFSEL1_Pos           (4U)
3859 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
3860 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
3861 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
3862 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
3863 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
3864 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
3865 #define GPIO_AFRL_AFSEL2_Pos           (8U)
3866 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
3867 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
3868 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
3869 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
3870 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
3871 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
3872 #define GPIO_AFRL_AFSEL3_Pos           (12U)
3873 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
3874 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
3875 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
3876 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
3877 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
3878 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
3879 #define GPIO_AFRL_AFSEL4_Pos           (16U)
3880 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
3881 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
3882 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
3883 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
3884 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
3885 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
3886 #define GPIO_AFRL_AFSEL5_Pos           (20U)
3887 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
3888 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
3889 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
3890 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
3891 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
3892 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
3893 #define GPIO_AFRL_AFSEL6_Pos           (24U)
3894 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
3895 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
3896 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
3897 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
3898 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
3899 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
3900 #define GPIO_AFRL_AFSEL7_Pos           (28U)
3901 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
3902 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
3903 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
3904 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
3905 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
3906 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
3907 
3908 /* Legacy defines */
3909 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
3910 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
3911 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
3912 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
3913 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
3914 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
3915 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
3916 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
3917 
3918 /****************** Bit definition for GPIO_AFRH register  ********************/
3919 #define GPIO_AFRH_AFSEL8_Pos           (0U)
3920 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
3921 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
3922 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
3923 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
3924 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
3925 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
3926 #define GPIO_AFRH_AFSEL9_Pos           (4U)
3927 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
3928 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
3929 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
3930 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
3931 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
3932 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
3933 #define GPIO_AFRH_AFSEL10_Pos          (8U)
3934 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
3935 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
3936 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
3937 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
3938 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
3939 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
3940 #define GPIO_AFRH_AFSEL11_Pos          (12U)
3941 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
3942 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
3943 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
3944 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
3945 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
3946 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
3947 #define GPIO_AFRH_AFSEL12_Pos          (16U)
3948 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
3949 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
3950 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
3951 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
3952 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
3953 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
3954 #define GPIO_AFRH_AFSEL13_Pos          (20U)
3955 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
3956 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
3957 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
3958 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
3959 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
3960 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
3961 #define GPIO_AFRH_AFSEL14_Pos          (24U)
3962 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
3963 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
3964 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
3965 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
3966 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
3967 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
3968 #define GPIO_AFRH_AFSEL15_Pos          (28U)
3969 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
3970 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
3971 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
3972 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
3973 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
3974 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
3975 
3976 /* Legacy defines */
3977 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
3978 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
3979 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
3980 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
3981 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
3982 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
3983 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
3984 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
3985 
3986 /******************************************************************************/
3987 /*                                                                            */
3988 /*                      Inter-integrated Circuit Interface (I2C)              */
3989 /*                                                                            */
3990 /******************************************************************************/
3991 /*******************  Bit definition for I2C_CR1 register  *******************/
3992 #define I2C_CR1_PE_Pos                      (0U)
3993 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
3994 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
3995 #define I2C_CR1_TXIE_Pos                    (1U)
3996 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
3997 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
3998 #define I2C_CR1_RXIE_Pos                    (2U)
3999 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
4000 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
4001 #define I2C_CR1_ADDRIE_Pos                  (3U)
4002 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
4003 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
4004 #define I2C_CR1_NACKIE_Pos                  (4U)
4005 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
4006 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
4007 #define I2C_CR1_STOPIE_Pos                  (5U)
4008 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
4009 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
4010 #define I2C_CR1_TCIE_Pos                    (6U)
4011 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
4012 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
4013 #define I2C_CR1_ERRIE_Pos                   (7U)
4014 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
4015 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
4016 #define I2C_CR1_DNF_Pos                     (8U)
4017 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
4018 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
4019 #define I2C_CR1_ANFOFF_Pos                  (12U)
4020 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
4021 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
4022 #define I2C_CR1_TXDMAEN_Pos                 (14U)
4023 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
4024 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
4025 #define I2C_CR1_RXDMAEN_Pos                 (15U)
4026 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
4027 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
4028 #define I2C_CR1_SBC_Pos                     (16U)
4029 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
4030 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
4031 #define I2C_CR1_NOSTRETCH_Pos               (17U)
4032 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
4033 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
4034 #define I2C_CR1_WUPEN_Pos                   (18U)
4035 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
4036 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
4037 #define I2C_CR1_GCEN_Pos                    (19U)
4038 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
4039 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
4040 #define I2C_CR1_FMP_Pos                     (24U)
4041 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
4042 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
4043 #define I2C_CR1_ADDRACLR_Pos                (30U)
4044 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
4045 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
4046 #define I2C_CR1_STOPFACLR_Pos               (31U)
4047 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
4048 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
4049 
4050 /******************  Bit definition for I2C_CR2 register  ********************/
4051 #define I2C_CR2_SADD_Pos                    (0U)
4052 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
4053 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
4054 #define I2C_CR2_RD_WRN_Pos                  (10U)
4055 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
4056 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
4057 #define I2C_CR2_ADD10_Pos                   (11U)
4058 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
4059 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
4060 #define I2C_CR2_HEAD10R_Pos                 (12U)
4061 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
4062 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
4063 #define I2C_CR2_START_Pos                   (13U)
4064 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
4065 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
4066 #define I2C_CR2_STOP_Pos                    (14U)
4067 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
4068 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
4069 #define I2C_CR2_NACK_Pos                    (15U)
4070 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
4071 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
4072 #define I2C_CR2_NBYTES_Pos                  (16U)
4073 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
4074 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
4075 #define I2C_CR2_RELOAD_Pos                  (24U)
4076 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
4077 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
4078 #define I2C_CR2_AUTOEND_Pos                 (25U)
4079 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
4080 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
4081 
4082 /*******************  Bit definition for I2C_OAR1 register  ******************/
4083 #define I2C_OAR1_OA1_Pos                    (0U)
4084 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
4085 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
4086 #define I2C_OAR1_OA1MODE_Pos                (10U)
4087 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
4088 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
4089 #define I2C_OAR1_OA1EN_Pos                  (15U)
4090 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
4091 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
4092 
4093 /*******************  Bit definition for I2C_OAR2 register  ******************/
4094 #define I2C_OAR2_OA2_Pos                    (1U)
4095 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
4096 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
4097 #define I2C_OAR2_OA2MSK_Pos                 (8U)
4098 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
4099 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
4100 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
4101 #define I2C_OAR2_OA2MASK01_Pos              (8U)
4102 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
4103 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
4104 #define I2C_OAR2_OA2MASK02_Pos              (9U)
4105 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
4106 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4107 #define I2C_OAR2_OA2MASK03_Pos              (8U)
4108 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
4109 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4110 #define I2C_OAR2_OA2MASK04_Pos              (10U)
4111 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
4112 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4113 #define I2C_OAR2_OA2MASK05_Pos              (8U)
4114 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
4115 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4116 #define I2C_OAR2_OA2MASK06_Pos              (9U)
4117 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
4118 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
4119 #define I2C_OAR2_OA2MASK07_Pos              (8U)
4120 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
4121 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
4122 #define I2C_OAR2_OA2EN_Pos                  (15U)
4123 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
4124 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
4125 
4126 /*******************  Bit definition for I2C_TIMINGR register *******************/
4127 #define I2C_TIMINGR_SCLL_Pos                (0U)
4128 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
4129 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
4130 #define I2C_TIMINGR_SCLH_Pos                (8U)
4131 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
4132 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
4133 #define I2C_TIMINGR_SDADEL_Pos              (16U)
4134 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
4135 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
4136 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
4137 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
4138 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
4139 #define I2C_TIMINGR_PRESC_Pos               (28U)
4140 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
4141 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
4142 
4143 /******************  Bit definition for I2C_ISR register  *********************/
4144 #define I2C_ISR_TXE_Pos                     (0U)
4145 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
4146 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
4147 #define I2C_ISR_TXIS_Pos                    (1U)
4148 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
4149 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
4150 #define I2C_ISR_RXNE_Pos                    (2U)
4151 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
4152 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
4153 #define I2C_ISR_ADDR_Pos                    (3U)
4154 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
4155 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
4156 #define I2C_ISR_NACKF_Pos                   (4U)
4157 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
4158 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
4159 #define I2C_ISR_STOPF_Pos                   (5U)
4160 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
4161 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
4162 #define I2C_ISR_TC_Pos                      (6U)
4163 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
4164 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
4165 #define I2C_ISR_TCR_Pos                     (7U)
4166 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
4167 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
4168 #define I2C_ISR_BERR_Pos                    (8U)
4169 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
4170 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
4171 #define I2C_ISR_ARLO_Pos                    (9U)
4172 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
4173 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
4174 #define I2C_ISR_OVR_Pos                     (10U)
4175 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
4176 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
4177 #define I2C_ISR_BUSY_Pos                    (15U)
4178 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
4179 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
4180 #define I2C_ISR_DIR_Pos                     (16U)
4181 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
4182 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
4183 #define I2C_ISR_ADDCODE_Pos                 (17U)
4184 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
4185 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
4186 
4187 /******************  Bit definition for I2C_ICR register  *********************/
4188 #define I2C_ICR_ADDRCF_Pos                  (3U)
4189 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
4190 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
4191 #define I2C_ICR_NACKCF_Pos                  (4U)
4192 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
4193 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
4194 #define I2C_ICR_STOPCF_Pos                  (5U)
4195 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
4196 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
4197 #define I2C_ICR_BERRCF_Pos                  (8U)
4198 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
4199 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
4200 #define I2C_ICR_ARLOCF_Pos                  (9U)
4201 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
4202 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
4203 #define I2C_ICR_OVRCF_Pos                   (10U)
4204 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
4205 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
4206 
4207 /******************  Bit definition for I2C_RXDR register  *********************/
4208 #define I2C_RXDR_RXDATA_Pos                 (0U)
4209 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
4210 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
4211 
4212 /******************  Bit definition for I2C_TXDR register  *********************/
4213 #define I2C_TXDR_TXDATA_Pos                 (0U)
4214 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
4215 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
4216 
4217 /******************************************************************************/
4218 /*                                                                            */
4219 /*                           Independent WATCHDOG                             */
4220 /*                                                                            */
4221 /******************************************************************************/
4222 /*******************  Bit definition for IWDG_KR register  ********************/
4223 #define IWDG_KR_KEY_Pos      (0U)
4224 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
4225 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
4226 
4227 /*******************  Bit definition for IWDG_PR register  ********************/
4228 #define IWDG_PR_PR_Pos       (0U)
4229 #define IWDG_PR_PR_Msk       (0xFUL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
4230 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                     /*!< PR[3:0] (Prescaler divider)         */
4231 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
4232 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
4233 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
4234 #define IWDG_PR_PR_3         (0x8UL << IWDG_PR_PR_Pos)                          /*!< 0x00000008 */
4235 
4236 /*******************  Bit definition for IWDG_RLR register  *******************/
4237 #define IWDG_RLR_RL_Pos      (0U)
4238 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
4239 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
4240 
4241 /*******************  Bit definition for IWDG_SR register  ********************/
4242 #define IWDG_SR_PVU_Pos      (0U)
4243 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
4244 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
4245 #define IWDG_SR_RVU_Pos      (1U)
4246 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
4247 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
4248 #define IWDG_SR_WVU_Pos      (2U)
4249 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
4250 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
4251 #define IWDG_SR_EWU_Pos      (3U)
4252 #define IWDG_SR_EWU_Msk      (0x1UL << IWDG_SR_EWU_Pos)                        /*!< 0x00000008 */
4253 #define IWDG_SR_EWU          IWDG_SR_EWU_Msk                                   /*!< Watchdog interrupt comparator value update */
4254 #define IWDG_SR_ONF_Pos      (8U)
4255 #define IWDG_SR_ONF_Msk      (0x1UL << IWDG_SR_ONF_Pos)                        /*!< 0x00000100 */
4256 #define IWDG_SR_ONF          IWDG_SR_ONF_Msk                                   /*!< Watchdog Enable status bit */
4257 #define IWDG_SR_EWIF_Pos     (14U)
4258 #define IWDG_SR_EWIF_Msk     (0x1UL << IWDG_SR_EWIF_Pos)                       /*!< 0x00004000 */
4259 #define IWDG_SR_EWIF         IWDG_SR_EWIF_Msk                                  /*!< Watchdog early interrupt flag */
4260 
4261 /*******************  Bit definition for IWDG_WINR register  ********************/
4262 #define IWDG_WINR_WIN_Pos    (0U)
4263 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
4264 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
4265 
4266 /******************  Bit definition for IWDG_EWCR register  *******************/
4267 #define IWDG_EWCR_EWIT_Pos                  (0U)
4268 #define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
4269 #define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
4270 #define IWDG_EWCR_EWIC_Pos                  (14U)
4271 #define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00004000 */
4272 #define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
4273 #define IWDG_EWCR_EWIE_Pos                  (15U)
4274 #define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00008000 */
4275 #define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */
4276 
4277 
4278 /******************************************************************************/
4279 /*                                                                            */
4280 /*                         Operational Amplifier (OPAMP)                      */
4281 /*                                                                            */
4282 /******************************************************************************/
4283 /*********************  Bit definition for OPAMPx_CSR register  ***************/
4284 #define OPAMP_CSR_OPAEN_Pos                 (0U)
4285 #define OPAMP_CSR_OPAEN_Msk                 (0x1UL << OPAMP_CSR_OPAEN_Pos)            /*!< 0x00000001 */
4286 #define OPAMP_CSR_OPAEN                     OPAMP_CSR_OPAEN_Msk                       /*!< OPAMP enable */
4287 
4288 #define OPAMP_CSR_OPALPM_Pos                (1U)
4289 #define OPAMP_CSR_OPALPM_Msk                (0x1UL << OPAMP_CSR_OPALPM_Pos)           /*!< 0x00000002 */
4290 #define OPAMP_CSR_OPALPM                    OPAMP_CSR_OPALPM_Msk                      /*!< Operational amplifier Low Power Mode */
4291 
4292 #define OPAMP_CSR_OPAMODE_Pos               (2U)
4293 #define OPAMP_CSR_OPAMODE_Msk               (0x3UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x0000000C */
4294 #define OPAMP_CSR_OPAMODE                   OPAMP_CSR_OPAMODE_Msk                     /*!< Operational amplifier PGA mode */
4295 #define OPAMP_CSR_OPAMODE_0                 (0x1UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000004 */
4296 #define OPAMP_CSR_OPAMODE_1                 (0x2UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000008 */
4297 
4298 #define OPAMP_CSR_PGA_GAIN_Pos              (4U)
4299 #define OPAMP_CSR_PGA_GAIN_Msk              (0x3UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000030 */
4300 #define OPAMP_CSR_PGA_GAIN                  OPAMP_CSR_PGA_GAIN_Msk                    /*!< Operational amplifier Programmable amplifier gain value */
4301 #define OPAMP_CSR_PGA_GAIN_0                (0x1UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000010 */
4302 #define OPAMP_CSR_PGA_GAIN_1                (0x2UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000020 */
4303 
4304 #define OPAMP_CSR_VM_SEL_Pos                (8U)
4305 #define OPAMP_CSR_VM_SEL_Msk                (0x3UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000300 */
4306 #define OPAMP_CSR_VM_SEL                    OPAMP_CSR_VM_SEL_Msk                      /*!< Inverting input selection */
4307 #define OPAMP_CSR_VM_SEL_0                  (0x1UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000100 */
4308 #define OPAMP_CSR_VM_SEL_1                  (0x2UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000200 */
4309 
4310 #define OPAMP_CSR_VP_SEL_Pos                (10U)
4311 #define OPAMP_CSR_VP_SEL_Msk                (0x1UL << OPAMP_CSR_VP_SEL_Pos)           /*!< 0x00000400 */
4312 #define OPAMP_CSR_VP_SEL                    OPAMP_CSR_VP_SEL_Msk                      /*!< Non inverted input selection */
4313 
4314 #define OPAMP_CSR_CALON_Pos                 (12U)
4315 #define OPAMP_CSR_CALON_Msk                 (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00001000 */
4316 #define OPAMP_CSR_CALON                     OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
4317 
4318 #define OPAMP_CSR_CALSEL_Pos                (13U)
4319 #define OPAMP_CSR_CALSEL_Msk                (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
4320 #define OPAMP_CSR_CALSEL                    OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
4321 
4322 #define OPAMP_CSR_USERTRIM_Pos              (14U)
4323 #define OPAMP_CSR_USERTRIM_Msk              (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00004000 */
4324 #define OPAMP_CSR_USERTRIM                  OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
4325 
4326 #define OPAMP_CSR_CALOUT_Pos                (15U)
4327 #define OPAMP_CSR_CALOUT_Msk                (0x1UL << OPAMP_CSR_CALOUT_Pos)           /*!< 0x00008000 */
4328 #define OPAMP_CSR_CALOUT                    OPAMP_CSR_CALOUT_Msk                      /*!< Operational amplifier calibration output */
4329 
4330 #define OPAMP_CSR_OPARANGE_Pos              (31U)
4331 #define OPAMP_CSR_OPARANGE_Msk              (0x1UL << OPAMP_CSR_OPARANGE_Pos)         /*!< 0x80000000 */
4332 #define OPAMP_CSR_OPARANGE                  OPAMP_CSR_OPARANGE_Msk                    /*!< Operational amplifier range setting */
4333 
4334 /*******************  Bit definition for OPAMPx_OTR register  ******************/
4335 #define OPAMP_OTR_TRIMOFFSETN_Pos           (0U)
4336 #define OPAMP_OTR_TRIMOFFSETN_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)     /*!< 0x0000001F */
4337 #define OPAMP_OTR_TRIMOFFSETN               OPAMP_OTR_TRIMOFFSETN_Msk                 /*!< Trim for NMOS differential pairs */
4338 #define OPAMP_OTR_TRIMOFFSETP_Pos           (8U)
4339 #define OPAMP_OTR_TRIMOFFSETP_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)     /*!< 0x00001F00 */
4340 #define OPAMP_OTR_TRIMOFFSETP               OPAMP_OTR_TRIMOFFSETP_Msk                 /*!< Trim for PMOS differential pairs */
4341 
4342 /*******************  Bit definition for OPAMPx_LPOTR register  ****************/
4343 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos       (0U)
4344 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
4345 #define OPAMP_LPOTR_TRIMLPOFFSETN           OPAMP_LPOTR_TRIMLPOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
4346 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos       (8U)
4347 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
4348 #define OPAMP_LPOTR_TRIMLPOFFSETP           OPAMP_LPOTR_TRIMLPOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
4349 
4350 /******************************************************************************/
4351 /*                                                                            */
4352 /*                             Power Control                                  */
4353 /*                                                                            */
4354 /******************************************************************************/
4355 
4356 /********************  Bit definition for PWR_CR1 register  *******************/
4357 #define PWR_CR1_LPMS_Pos               (0U)
4358 #define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
4359 #define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< LPMS[2:0] Low-power mode selection field     */
4360 #define PWR_CR1_LPMS_0                 (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
4361 #define PWR_CR1_LPMS_1                 (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
4362 #define PWR_CR1_LPMS_2                 (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
4363 
4364 #define PWR_CR1_FPD_STOP_Pos           (3U)
4365 #define PWR_CR1_FPD_STOP_Msk           (0x1UL << PWR_CR1_FPD_STOP_Pos)         /*!< 0x00000008 */
4366 #define PWR_CR1_FPD_STOP               PWR_CR1_FPD_STOP_Msk                    /*!< Flash power down mode during stop */
4367 #define PWR_CR1_FPD_LPRUN_Pos          (4U)
4368 #define PWR_CR1_FPD_LPRUN_Msk          (0x1UL << PWR_CR1_FPD_LPRUN_Pos)        /*!< 0x00000010 */
4369 #define PWR_CR1_FPD_LPRUN              PWR_CR1_FPD_LPRUN_Msk                   /*!< Flash power down mode during low power run */
4370 #define PWR_CR1_FPD_LPSLP_Pos          (5U)
4371 #define PWR_CR1_FPD_LPSLP_Msk          (0x1UL << PWR_CR1_FPD_LPSLP_Pos)        /*!< 0x00000020 */
4372 #define PWR_CR1_FPD_LPSLP              PWR_CR1_FPD_LPSLP_Msk                   /*!< Flash power down mode during low power sleep */
4373 #define PWR_CR1_DBP_Pos                (8U)
4374 #define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
4375 #define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable backup protection */
4376 #define PWR_CR1_VOS_Pos                (9U)
4377 #define PWR_CR1_VOS_Msk                (0x3UL << PWR_CR1_VOS_Pos)              /*!< 0x00000600 */
4378 #define PWR_CR1_VOS                    PWR_CR1_VOS_Msk                         /*!< VOS[1:0] VOltage Scaling range Selection field     */
4379 #define PWR_CR1_VOS_0                  (0x1UL << PWR_CR1_VOS_Pos)              /*!< 0x00000200 */
4380 #define PWR_CR1_VOS_1                  (0x2UL << PWR_CR1_VOS_Pos)              /*!< 0x00000400 */
4381 #define PWR_CR1_LPR_Pos                (14U)
4382 #define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
4383 #define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Low Power Run */
4384 
4385 /********************  Bit definition for PWR_CR2 register  *******************/
4386 #define PWR_CR2_PVDE_Pos               (0U)
4387 #define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
4388 #define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Programmable Voltage detector enable */
4389 #define PWR_CR2_PLS_Pos                (1U)
4390 #define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
4391 #define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power Voltage Detector Level selection */
4392 #define PWR_CR2_PLS_0                  (0x1UL << PWR_CR2_PLS_Pos)              /*!< 0x00000002 */
4393 #define PWR_CR2_PLS_1                  (0x2UL << PWR_CR2_PLS_Pos)              /*!< 0x00000004 */
4394 #define PWR_CR2_PLS_2                  (0x4UL << PWR_CR2_PLS_Pos)              /*!< 0x00000008 */
4395 #define PWR_CR2_PVME3_Pos              (5U)
4396 #define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000020 */
4397 #define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripheral Voltage Monitoring Enable of VDDADC */
4398 #define PWR_CR2_PVME4_Pos              (6U)
4399 #define PWR_CR2_PVME4_Msk              (0x1UL << PWR_CR2_PVME4_Pos)            /*!< 0x00000040 */
4400 #define PWR_CR2_PVME4                  PWR_CR2_PVME4_Msk                       /*!< Peripheral Voltage Monitoring Enable of VDDDAC */
4401 
4402 /********************  Bit definition for PWR_CR3 register  *******************/
4403 #define PWR_CR3_EWUP1_Pos              (0U)
4404 #define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
4405 #define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP pin 1 */
4406 #define PWR_CR3_EWUP2_Pos              (1U)
4407 #define PWR_CR3_EWUP2_Msk              (0x1UL << PWR_CR3_EWUP2_Pos)            /*!< 0x00000002 */
4408 #define PWR_CR3_EWUP2                  PWR_CR3_EWUP2_Msk                       /*!< Enable external WKUP pin 2 */
4409 #define PWR_CR3_EWUP3_Pos              (2U)
4410 #define PWR_CR3_EWUP3_Msk              (0x1UL << PWR_CR3_EWUP3_Pos)            /*!< 0x00000004 */
4411 #define PWR_CR3_EWUP3                  PWR_CR3_EWUP3_Msk                       /*!< Enable external WKUP pin 3 */
4412 #define PWR_CR3_EWUP4_Pos              (3U)
4413 #define PWR_CR3_EWUP4_Msk              (0x1UL << PWR_CR3_EWUP4_Pos)            /*!< 0x00000008 */
4414 #define PWR_CR3_EWUP4                  PWR_CR3_EWUP4_Msk                       /*!< Enable external WKUP pin 4 */
4415 #define PWR_CR3_EWUP5_Pos              (4U)
4416 #define PWR_CR3_EWUP5_Msk              (0x1UL << PWR_CR3_EWUP5_Pos)            /*!< 0x00000010 */
4417 #define PWR_CR3_EWUP5                  PWR_CR3_EWUP5_Msk                       /*!< Enable external WKUP pin 5 */
4418 #define PWR_CR3_EWUP7_Pos              (6U)
4419 #define PWR_CR3_EWUP7_Msk              (0x1UL << PWR_CR3_EWUP7_Pos)            /*!< 0x00000040 */
4420 #define PWR_CR3_EWUP7                  PWR_CR3_EWUP7_Msk                       /*!< Enable external WKUP pin 7 */
4421 
4422 #define PWR_CR3_RRS_Pos                (8U)
4423 #define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000100 */
4424 #define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< Ram retention in STANDBY mode */
4425 #define PWR_CR3_ENULP_Pos              (9U)
4426 #define PWR_CR3_ENULP_Msk              (0x1UL << PWR_CR3_ENULP_Pos)            /*!< 0x00000200 */
4427 #define PWR_CR3_ENULP                  PWR_CR3_ENULP_Msk                       /*!< Enable ULP BORL, BORH and PVD (resistor bridge sampling) for STOP2 and all Standby modes */
4428 #define PWR_CR3_APC_Pos                (10U)
4429 #define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
4430 #define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration */
4431 #define PWR_CR3_EIWUL_Pos              (15U)
4432 #define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00008000 */
4433 #define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Enable Internal Wake-up line */
4434 
4435 /********************  Bit definition for PWR_CR4 register  ********************/
4436 #define PWR_CR4_WP1_Pos                (0U)
4437 #define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
4438 #define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up pin 1 polarity */
4439 #define PWR_CR4_WP2_Pos                (1U)
4440 #define PWR_CR4_WP2_Msk                (0x1UL << PWR_CR4_WP2_Pos)              /*!< 0x00000002 */
4441 #define PWR_CR4_WP2                    PWR_CR4_WP2_Msk                         /*!< Wake-Up pin 2 polarity */
4442 #define PWR_CR4_WP3_Pos                (2U)
4443 #define PWR_CR4_WP3_Msk                (0x1UL << PWR_CR4_WP3_Pos)              /*!< 0x00000004 */
4444 #define PWR_CR4_WP3                    PWR_CR4_WP3_Msk                         /*!< Wake-Up pin 3 polarity */
4445 #define PWR_CR4_WP4_Pos                (3U)
4446 #define PWR_CR4_WP4_Msk                (0x1UL << PWR_CR4_WP4_Pos)              /*!< 0x00000008 */
4447 #define PWR_CR4_WP4                    PWR_CR4_WP4_Msk                         /*!< Wake-Up pin 4 polarity */
4448 #define PWR_CR4_WP5_Pos                (4U)
4449 #define PWR_CR4_WP5_Msk                (0x1UL << PWR_CR4_WP5_Pos)              /*!< 0x00000010 */
4450 #define PWR_CR4_WP5                    PWR_CR4_WP5_Msk                         /*!< Wake-Up pin 5 polarity */
4451 #define PWR_CR4_WP7_Pos                (6U)
4452 #define PWR_CR4_WP7_Msk                (0x1UL << PWR_CR4_WP7_Pos)              /*!< 0x00000040 */
4453 #define PWR_CR4_WP7                    PWR_CR4_WP7_Msk                         /*!< Wake-Up pin 7 polarity */
4454 #define PWR_CR4_VBE_Pos                (8U)
4455 #define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
4456 #define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT Battery charging Enable */
4457 #define PWR_CR4_VBRS_Pos               (9U)
4458 #define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
4459 #define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT Battery charging Resistor Selection */
4460 
4461 /********************  Bit definition for PWR_SR1 register  ********************/
4462 #define PWR_SR1_WUF1_Pos               (0U)
4463 #define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
4464 #define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Flag 1 */
4465 #define PWR_SR1_WUF2_Pos               (1U)
4466 #define PWR_SR1_WUF2_Msk               (0x1UL << PWR_SR1_WUF2_Pos)             /*!< 0x00000002 */
4467 #define PWR_SR1_WUF2                   PWR_SR1_WUF2_Msk                        /*!< Wakeup Flag 2 */
4468 #define PWR_SR1_WUF3_Pos               (2U)
4469 #define PWR_SR1_WUF3_Msk               (0x1UL << PWR_SR1_WUF3_Pos)             /*!< 0x00000004 */
4470 #define PWR_SR1_WUF3                   PWR_SR1_WUF3_Msk                        /*!< Wakeup Flag 3 */
4471 #define PWR_SR1_WUF4_Pos               (3U)
4472 #define PWR_SR1_WUF4_Msk               (0x1UL << PWR_SR1_WUF4_Pos)             /*!< 0x00000008 */
4473 #define PWR_SR1_WUF4                   PWR_SR1_WUF4_Msk                        /*!< Wakeup Flag 4 */
4474 #define PWR_SR1_WUF5_Pos               (4U)
4475 #define PWR_SR1_WUF5_Msk               (0x1UL << PWR_SR1_WUF5_Pos)             /*!< 0x00000010 */
4476 #define PWR_SR1_WUF5                   PWR_SR1_WUF5_Msk                        /*!< Wakeup Flag 5 */
4477 #define PWR_SR1_WUF7_Pos               (6U)
4478 #define PWR_SR1_WUF7_Msk               (0x1UL << PWR_SR1_WUF7_Pos)             /*!< 0x00000040 */
4479 #define PWR_SR1_WUF7                   PWR_SR1_WUF7_Msk                        /*!< Wakeup Flag 7 */
4480 
4481 #define PWR_SR1_SBF_Pos                (8U)
4482 #define PWR_SR1_SBF_Msk                (0x1UL << PWR_SR1_SBF_Pos)              /*!< 0x00000100 */
4483 #define PWR_SR1_SBF                    PWR_SR1_SBF_Msk                         /*!< Standby Flag  */
4484 
4485 #define PWR_SR1_STOPF_Pos              (9U)
4486 #define PWR_SR1_STOPF_Msk              (0x7UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000E00 */
4487 #define PWR_SR1_STOPF                  PWR_SR1_STOPF_Msk                       /*!< STOPF[2:0] Stop Flags */
4488 #define PWR_SR1_STOPF_0                (0x1UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000200 */
4489 #define PWR_SR1_STOPF_1                (0x2UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000400 */
4490 #define PWR_SR1_STOPF_2                (0x4UL << PWR_SR1_STOPF_Pos)            /*!< 0x00000800 */
4491 #define PWR_SR1_WUFI_Pos               (15U)
4492 #define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
4493 #define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Wakeup Flag Internal */
4494 
4495 /********************  Bit definition for PWR_SR2 register  ********************/
4496 #define PWR_SR2_FLASH_RDY_Pos          (7U)
4497 #define PWR_SR2_FLASH_RDY_Msk          (0x1UL << PWR_SR2_FLASH_RDY_Pos)        /*!< 0x00000080 */
4498 #define PWR_SR2_FLASH_RDY              PWR_SR2_FLASH_RDY_Msk                   /*!< Flash Ready */
4499 #define PWR_SR2_REGLPS_Pos             (8U)
4500 #define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
4501 #define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Regulator Low Power started    */
4502 #define PWR_SR2_REGLPF_Pos             (9U)
4503 #define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
4504 #define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Regulator Low Power flag    */
4505 #define PWR_SR2_VOSF_Pos               (10U)
4506 #define PWR_SR2_VOSF_Msk               (0x1UL << PWR_SR2_VOSF_Pos)             /*!< 0x00000400 */
4507 #define PWR_SR2_VOSF                   PWR_SR2_VOSF_Msk                        /*!< VOltage Scaling Flag    */
4508 #define PWR_SR2_PVDO_Pos               (11U)
4509 #define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
4510 #define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power Voltage Detector Output    */
4511 #define PWR_SR2_PVMO3_Pos              (14U)
4512 #define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
4513 #define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< PVMO ADC & PVME ADC    */
4514 #define PWR_SR2_PVMO4_Pos              (15U)
4515 #define PWR_SR2_PVMO4_Msk              (0x1UL << PWR_SR2_PVMO4_Pos)            /*!< 0x00008000 */
4516 #define PWR_SR2_PVMO4                  PWR_SR2_PVMO4_Msk                       /*!< PVMO DAC & PVME DAC    */
4517 
4518 /********************  Bit definition for PWR_SCR register  ********************/
4519 #define PWR_SCR_CWUF1_Pos              (0U)
4520 #define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
4521 #define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Flag 1 */
4522 #define PWR_SCR_CWUF2_Pos              (1U)
4523 #define PWR_SCR_CWUF2_Msk              (0x1UL << PWR_SCR_CWUF2_Pos)            /*!< 0x00000002 */
4524 #define PWR_SCR_CWUF2                  PWR_SCR_CWUF2_Msk                       /*!< Clear Wake-up Flag 2 */
4525 #define PWR_SCR_CWUF3_Pos              (2U)
4526 #define PWR_SCR_CWUF3_Msk              (0x1UL << PWR_SCR_CWUF3_Pos)            /*!< 0x00000004 */
4527 #define PWR_SCR_CWUF3                  PWR_SCR_CWUF3_Msk                       /*!< Clear Wake-up Flag 3 */
4528 #define PWR_SCR_CWUF4_Pos              (3U)
4529 #define PWR_SCR_CWUF4_Msk              (0x1UL << PWR_SCR_CWUF4_Pos)            /*!< 0x00000008 */
4530 #define PWR_SCR_CWUF4                  PWR_SCR_CWUF4_Msk                       /*!< Clear Wake-up Flag 4 */
4531 #define PWR_SCR_CWUF5_Pos              (4U)
4532 #define PWR_SCR_CWUF5_Msk              (0x1UL << PWR_SCR_CWUF5_Pos)            /*!< 0x00000010 */
4533 #define PWR_SCR_CWUF5                  PWR_SCR_CWUF5_Msk                       /*!< Clear Wake-up Flag 5 */
4534 #define PWR_SCR_CWUF7_Pos              (6U)
4535 #define PWR_SCR_CWUF7_Msk              (0x1UL << PWR_SCR_CWUF7_Pos)            /*!< 0x00000040 */
4536 #define PWR_SCR_CWUF7                  PWR_SCR_CWUF7_Msk                       /*!< Clear Wake-up Flag 7 */
4537 #define PWR_SCR_CSBF_Pos               (8U)
4538 #define PWR_SCR_CSBF_Msk               (0x1UL << PWR_SCR_CSBF_Pos)             /*!< 0x00000100 */
4539 #define PWR_SCR_CSBF                   PWR_SCR_CSBF_Msk                        /*!< Clear Standby Flag  */
4540 
4541 /********************  Bit definition for PWR_PUCRA register  *****************/
4542 #define PWR_PUCRA_PU0_Pos         (0U)
4543 #define PWR_PUCRA_PU0_Msk         (0x1UL << PWR_PUCRA_PU0_Pos)                 /*!< 0x00000001 */
4544 #define PWR_PUCRA_PU0             PWR_PUCRA_PU0_Msk                            /*!< Pin PA0 Pull-Up set */
4545 #define PWR_PUCRA_PU1_Pos         (1U)
4546 #define PWR_PUCRA_PU1_Msk         (0x1UL << PWR_PUCRA_PU1_Pos)                 /*!< 0x00000002 */
4547 #define PWR_PUCRA_PU1             PWR_PUCRA_PU1_Msk                            /*!< Pin PA1 Pull-Up set */
4548 #define PWR_PUCRA_PU2_Pos         (2U)
4549 #define PWR_PUCRA_PU2_Msk         (0x1UL << PWR_PUCRA_PU2_Pos)                 /*!< 0x00000004 */
4550 #define PWR_PUCRA_PU2             PWR_PUCRA_PU2_Msk                            /*!< Pin PA2 Pull-Up set */
4551 #define PWR_PUCRA_PU3_Pos         (3U)
4552 #define PWR_PUCRA_PU3_Msk         (0x1UL << PWR_PUCRA_PU3_Pos)                 /*!< 0x00000008 */
4553 #define PWR_PUCRA_PU3             PWR_PUCRA_PU3_Msk                            /*!< Pin PA3 Pull-Up set */
4554 #define PWR_PUCRA_PU4_Pos         (4U)
4555 #define PWR_PUCRA_PU4_Msk         (0x1UL << PWR_PUCRA_PU4_Pos)                 /*!< 0x00000010 */
4556 #define PWR_PUCRA_PU4             PWR_PUCRA_PU4_Msk                            /*!< Pin PA4 Pull-Up set */
4557 #define PWR_PUCRA_PU5_Pos         (5U)
4558 #define PWR_PUCRA_PU5_Msk         (0x1UL << PWR_PUCRA_PU5_Pos)                 /*!< 0x00000020 */
4559 #define PWR_PUCRA_PU5             PWR_PUCRA_PU5_Msk                            /*!< Pin PA5 Pull-Up set */
4560 #define PWR_PUCRA_PU6_Pos         (6U)
4561 #define PWR_PUCRA_PU6_Msk         (0x1UL << PWR_PUCRA_PU6_Pos)                 /*!< 0x00000040 */
4562 #define PWR_PUCRA_PU6             PWR_PUCRA_PU6_Msk                            /*!< Pin PA6 Pull-Up set */
4563 #define PWR_PUCRA_PU7_Pos         (7U)
4564 #define PWR_PUCRA_PU7_Msk         (0x1UL << PWR_PUCRA_PU7_Pos)                 /*!< 0x00000080 */
4565 #define PWR_PUCRA_PU7             PWR_PUCRA_PU7_Msk                            /*!< Pin PA7 Pull-Up set */
4566 #define PWR_PUCRA_PU8_Pos         (8U)
4567 #define PWR_PUCRA_PU8_Msk         (0x1UL << PWR_PUCRA_PU8_Pos)                 /*!< 0x00000100 */
4568 #define PWR_PUCRA_PU8             PWR_PUCRA_PU8_Msk                            /*!< Pin PA8 Pull-Up set */
4569 #define PWR_PUCRA_PU9_Pos         (9U)
4570 #define PWR_PUCRA_PU9_Msk         (0x1UL << PWR_PUCRA_PU9_Pos)                 /*!< 0x00000200 */
4571 #define PWR_PUCRA_PU9             PWR_PUCRA_PU9_Msk                            /*!< Pin PA9 Pull-Up set */
4572 #define PWR_PUCRA_PU10_Pos        (10U)
4573 #define PWR_PUCRA_PU10_Msk        (0x1UL << PWR_PUCRA_PU10_Pos)                /*!< 0x00000400 */
4574 #define PWR_PUCRA_PU10            PWR_PUCRA_PU10_Msk                           /*!< Pin PA10 Pull-Up set */
4575 #define PWR_PUCRA_PU11_Pos        (11U)
4576 #define PWR_PUCRA_PU11_Msk        (0x1UL << PWR_PUCRA_PU11_Pos)                /*!< 0x00000800 */
4577 #define PWR_PUCRA_PU11            PWR_PUCRA_PU11_Msk                           /*!< Pin PA11 Pull-Up set */
4578 #define PWR_PUCRA_PU12_Pos        (12U)
4579 #define PWR_PUCRA_PU12_Msk        (0x1UL << PWR_PUCRA_PU12_Pos)                /*!< 0x00001000 */
4580 #define PWR_PUCRA_PU12            PWR_PUCRA_PU12_Msk                           /*!< Pin PA12 Pull-Up set */
4581 #define PWR_PUCRA_PU13_Pos        (13U)
4582 #define PWR_PUCRA_PU13_Msk        (0x1UL << PWR_PUCRA_PU13_Pos)                /*!< 0x00002000 */
4583 #define PWR_PUCRA_PU13            PWR_PUCRA_PU13_Msk                           /*!< Pin PA13 Pull-Up set */
4584 #define PWR_PUCRA_PU14_Pos        (14U)
4585 #define PWR_PUCRA_PU14_Msk        (0x1UL << PWR_PUCRA_PU14_Pos)                /*!< 0x00004000 */
4586 #define PWR_PUCRA_PU14            PWR_PUCRA_PU14_Msk                           /*!< Pin PA14 Pull-Up set */
4587 #define PWR_PUCRA_PU15_Pos        (15U)
4588 #define PWR_PUCRA_PU15_Msk        (0x1UL << PWR_PUCRA_PU15_Pos)                /*!< 0x00008000 */
4589 #define PWR_PUCRA_PU15            PWR_PUCRA_PU15_Msk                           /*!< Pin PA15 Pull-Up set */
4590 
4591 /********************  Bit definition for PWR_PDCRA register  *****************/
4592 #define PWR_PDCRA_PD0_Pos         (0U)
4593 #define PWR_PDCRA_PD0_Msk         (0x1UL << PWR_PDCRA_PD0_Pos)                 /*!< 0x00000001 */
4594 #define PWR_PDCRA_PD0             PWR_PDCRA_PD0_Msk                            /*!< Pin PA0 Pull-Down set */
4595 #define PWR_PDCRA_PD1_Pos         (1U)
4596 #define PWR_PDCRA_PD1_Msk         (0x1UL << PWR_PDCRA_PD1_Pos)                 /*!< 0x00000002 */
4597 #define PWR_PDCRA_PD1             PWR_PDCRA_PD1_Msk                            /*!< Pin PA1 Pull-Down set */
4598 #define PWR_PDCRA_PD2_Pos         (2U)
4599 #define PWR_PDCRA_PD2_Msk         (0x1UL << PWR_PDCRA_PD2_Pos)                 /*!< 0x00000004 */
4600 #define PWR_PDCRA_PD2             PWR_PDCRA_PD2_Msk                            /*!< Pin PA2 Pull-Down set */
4601 #define PWR_PDCRA_PD3_Pos         (3U)
4602 #define PWR_PDCRA_PD3_Msk         (0x1UL << PWR_PDCRA_PD3_Pos)                 /*!< 0x00000008 */
4603 #define PWR_PDCRA_PD3             PWR_PDCRA_PD3_Msk                            /*!< Pin PA3 Pull-Down set */
4604 #define PWR_PDCRA_PD4_Pos         (4U)
4605 #define PWR_PDCRA_PD4_Msk         (0x1UL << PWR_PDCRA_PD4_Pos)                 /*!< 0x00000010 */
4606 #define PWR_PDCRA_PD4             PWR_PDCRA_PD4_Msk                            /*!< Pin PA4 Pull-Down set */
4607 #define PWR_PDCRA_PD5_Pos         (5U)
4608 #define PWR_PDCRA_PD5_Msk         (0x1UL << PWR_PDCRA_PD5_Pos)                 /*!< 0x00000020 */
4609 #define PWR_PDCRA_PD5             PWR_PDCRA_PD5_Msk                            /*!< Pin PA5 Pull-Down set */
4610 #define PWR_PDCRA_PD6_Pos         (6U)
4611 #define PWR_PDCRA_PD6_Msk         (0x1UL << PWR_PDCRA_PD6_Pos)                 /*!< 0x00000040 */
4612 #define PWR_PDCRA_PD6             PWR_PDCRA_PD6_Msk                            /*!< Pin PA6 Pull-Down set */
4613 #define PWR_PDCRA_PD7_Pos         (7U)
4614 #define PWR_PDCRA_PD7_Msk         (0x1UL << PWR_PDCRA_PD7_Pos)                 /*!< 0x00000080 */
4615 #define PWR_PDCRA_PD7             PWR_PDCRA_PD7_Msk                            /*!< Pin PA7 Pull-Down set */
4616 #define PWR_PDCRA_PD8_Pos         (8U)
4617 #define PWR_PDCRA_PD8_Msk         (0x1UL << PWR_PDCRA_PD8_Pos)                 /*!< 0x00000100 */
4618 #define PWR_PDCRA_PD8             PWR_PDCRA_PD8_Msk                            /*!< Pin PA8 Pull-Down set */
4619 #define PWR_PDCRA_PD9_Pos         (9U)
4620 #define PWR_PDCRA_PD9_Msk         (0x1UL << PWR_PDCRA_PD9_Pos)                 /*!< 0x00000200 */
4621 #define PWR_PDCRA_PD9             PWR_PDCRA_PD9_Msk                            /*!< Pin PA9 Pull-Down set */
4622 #define PWR_PDCRA_PD10_Pos        (10U)
4623 #define PWR_PDCRA_PD10_Msk        (0x1UL << PWR_PDCRA_PD10_Pos)                /*!< 0x00000400 */
4624 #define PWR_PDCRA_PD10            PWR_PDCRA_PD10_Msk                           /*!< Pin PA10 Pull-Down set */
4625 #define PWR_PDCRA_PD11_Pos        (11U)
4626 #define PWR_PDCRA_PD11_Msk        (0x1UL << PWR_PDCRA_PD11_Pos)                /*!< 0x00000800 */
4627 #define PWR_PDCRA_PD11            PWR_PDCRA_PD11_Msk                           /*!< Pin PA11 Pull-Down set */
4628 #define PWR_PDCRA_PD12_Pos        (12U)
4629 #define PWR_PDCRA_PD12_Msk        (0x1UL << PWR_PDCRA_PD12_Pos)                /*!< 0x00001000 */
4630 #define PWR_PDCRA_PD12            PWR_PDCRA_PD12_Msk                           /*!< Pin PA12 Pull-Down set */
4631 #define PWR_PDCRA_PD13_Pos        (13U)
4632 #define PWR_PDCRA_PD13_Msk        (0x1UL << PWR_PDCRA_PD13_Pos)                /*!< 0x00002000 */
4633 #define PWR_PDCRA_PD13            PWR_PDCRA_PD13_Msk                           /*!< Pin PA13 Pull-Down set */
4634 #define PWR_PDCRA_PD14_Pos        (14U)
4635 #define PWR_PDCRA_PD14_Msk        (0x1UL << PWR_PDCRA_PD14_Pos)                /*!< 0x00004000 */
4636 #define PWR_PDCRA_PD14            PWR_PDCRA_PD14_Msk                           /*!< Pin PA14 Pull-Down set */
4637 #define PWR_PDCRA_PD15_Pos        (15U)
4638 #define PWR_PDCRA_PD15_Msk        (0x1UL << PWR_PDCRA_PD15_Pos)                /*!< 0x00008000 */
4639 #define PWR_PDCRA_PD15            PWR_PDCRA_PD15_Msk                           /*!< Pin PA15 Pull-Down set */
4640 
4641 /********************  Bit definition for PWR_PUCRB register  *****************/
4642 #define PWR_PUCRB_PU0_Pos         (0U)
4643 #define PWR_PUCRB_PU0_Msk         (0x1UL << PWR_PUCRB_PU0_Pos)                 /*!< 0x00000001 */
4644 #define PWR_PUCRB_PU0             PWR_PUCRB_PU0_Msk                            /*!< Pin PB0 Pull-Up set */
4645 #define PWR_PUCRB_PU1_Pos         (1U)
4646 #define PWR_PUCRB_PU1_Msk         (0x1UL << PWR_PUCRB_PU1_Pos)                 /*!< 0x00000002 */
4647 #define PWR_PUCRB_PU1             PWR_PUCRB_PU1_Msk                            /*!< Pin PB1 Pull-Up set */
4648 #define PWR_PUCRB_PU2_Pos         (2U)
4649 #define PWR_PUCRB_PU2_Msk         (0x1UL << PWR_PUCRB_PU2_Pos)                 /*!< 0x00000004 */
4650 #define PWR_PUCRB_PU2             PWR_PUCRB_PU2_Msk                            /*!< Pin PB2 Pull-Up set */
4651 #define PWR_PUCRB_PU3_Pos         (3U)
4652 #define PWR_PUCRB_PU3_Msk         (0x1UL << PWR_PUCRB_PU3_Pos)                 /*!< 0x00000008 */
4653 #define PWR_PUCRB_PU3             PWR_PUCRB_PU3_Msk                            /*!< Pin PB3 Pull-Up set */
4654 #define PWR_PUCRB_PU4_Pos         (4U)
4655 #define PWR_PUCRB_PU4_Msk         (0x1UL << PWR_PUCRB_PU4_Pos)                 /*!< 0x00000010 */
4656 #define PWR_PUCRB_PU4             PWR_PUCRB_PU4_Msk                            /*!< Pin PB4 Pull-Up set */
4657 #define PWR_PUCRB_PU5_Pos         (5U)
4658 #define PWR_PUCRB_PU5_Msk         (0x1UL << PWR_PUCRB_PU5_Pos)                 /*!< 0x00000020 */
4659 #define PWR_PUCRB_PU5             PWR_PUCRB_PU5_Msk                            /*!< Pin PB5 Pull-Up set */
4660 #define PWR_PUCRB_PU6_Pos         (6U)
4661 #define PWR_PUCRB_PU6_Msk         (0x1UL << PWR_PUCRB_PU6_Pos)                 /*!< 0x00000040 */
4662 #define PWR_PUCRB_PU6             PWR_PUCRB_PU6_Msk                            /*!< Pin PB6 Pull-Up set */
4663 #define PWR_PUCRB_PU7_Pos         (7U)
4664 #define PWR_PUCRB_PU7_Msk         (0x1UL << PWR_PUCRB_PU7_Pos)                 /*!< 0x00000080 */
4665 #define PWR_PUCRB_PU7             PWR_PUCRB_PU7_Msk                            /*!< Pin PB7 Pull-Up set */
4666 #define PWR_PUCRB_PU8_Pos         (8U)
4667 #define PWR_PUCRB_PU8_Msk         (0x1UL << PWR_PUCRB_PU8_Pos)                 /*!< 0x00000100 */
4668 #define PWR_PUCRB_PU8             PWR_PUCRB_PU8_Msk                            /*!< Pin PB8 Pull-Up set */
4669 #define PWR_PUCRB_PU9_Pos         (9U)
4670 #define PWR_PUCRB_PU9_Msk         (0x1UL << PWR_PUCRB_PU9_Pos)                 /*!< 0x00000200 */
4671 #define PWR_PUCRB_PU9             PWR_PUCRB_PU9_Msk                            /*!< Pin PB9 Pull-Up set */
4672 #define PWR_PUCRB_PU10_Pos        (10U)
4673 #define PWR_PUCRB_PU10_Msk        (0x1UL << PWR_PUCRB_PU10_Pos)                /*!< 0x00000400 */
4674 #define PWR_PUCRB_PU10            PWR_PUCRB_PU10_Msk                           /*!< Pin PB10 Pull-Up set */
4675 #define PWR_PUCRB_PU11_Pos        (11U)
4676 #define PWR_PUCRB_PU11_Msk        (0x1UL << PWR_PUCRB_PU11_Pos)                /*!< 0x00000800 */
4677 #define PWR_PUCRB_PU11            PWR_PUCRB_PU11_Msk                           /*!< Pin PB11 Pull-Up set */
4678 #define PWR_PUCRB_PU12_Pos        (12U)
4679 #define PWR_PUCRB_PU12_Msk        (0x1UL << PWR_PUCRB_PU12_Pos)                /*!< 0x00001000 */
4680 #define PWR_PUCRB_PU12            PWR_PUCRB_PU12_Msk                           /*!< Pin PB12 Pull-Up set */
4681 #define PWR_PUCRB_PU13_Pos        (13U)
4682 #define PWR_PUCRB_PU13_Msk        (0x1UL << PWR_PUCRB_PU13_Pos)                /*!< 0x00002000 */
4683 #define PWR_PUCRB_PU13            PWR_PUCRB_PU13_Msk                           /*!< Pin PB13 Pull-Up set */
4684 #define PWR_PUCRB_PU14_Pos        (14U)
4685 #define PWR_PUCRB_PU14_Msk        (0x1UL << PWR_PUCRB_PU14_Pos)                /*!< 0x00004000 */
4686 #define PWR_PUCRB_PU14            PWR_PUCRB_PU14_Msk                           /*!< Pin PB14 Pull-Up set */
4687 #define PWR_PUCRB_PU15_Pos        (15U)
4688 #define PWR_PUCRB_PU15_Msk        (0x1UL << PWR_PUCRB_PU15_Pos)                /*!< 0x00008000 */
4689 #define PWR_PUCRB_PU15            PWR_PUCRB_PU15_Msk                           /*!< Pin PB15 Pull-Up set */
4690 
4691 /********************  Bit definition for PWR_PDCRB register  *****************/
4692 #define PWR_PDCRB_PD0_Pos         (0U)
4693 #define PWR_PDCRB_PD0_Msk         (0x1UL << PWR_PDCRB_PD0_Pos)                 /*!< 0x00000001 */
4694 #define PWR_PDCRB_PD0             PWR_PDCRB_PD0_Msk                            /*!< Pin PB0 Pull-Down set */
4695 #define PWR_PDCRB_PD1_Pos         (1U)
4696 #define PWR_PDCRB_PD1_Msk         (0x1UL << PWR_PDCRB_PD1_Pos)                 /*!< 0x00000002 */
4697 #define PWR_PDCRB_PD1             PWR_PDCRB_PD1_Msk                            /*!< Pin PB1 Pull-Down set */
4698 #define PWR_PDCRB_PD2_Pos         (2U)
4699 #define PWR_PDCRB_PD2_Msk         (0x1UL << PWR_PDCRB_PD2_Pos)                 /*!< 0x00000004 */
4700 #define PWR_PDCRB_PD2             PWR_PDCRB_PD2_Msk                            /*!< Pin PB2 Pull-Down set */
4701 #define PWR_PDCRB_PD3_Pos         (3U)
4702 #define PWR_PDCRB_PD3_Msk         (0x1UL << PWR_PDCRB_PD3_Pos)                 /*!< 0x00000008 */
4703 #define PWR_PDCRB_PD3             PWR_PDCRB_PD3_Msk                            /*!< Pin PB3 Pull-Down set */
4704 #define PWR_PDCRB_PD4_Pos         (4U)
4705 #define PWR_PDCRB_PD4_Msk         (0x1UL << PWR_PDCRB_PD4_Pos)                 /*!< 0x00000010 */
4706 #define PWR_PDCRB_PD4             PWR_PDCRB_PD4_Msk                            /*!< Pin PB4 Pull-Down set */
4707 #define PWR_PDCRB_PD5_Pos         (5U)
4708 #define PWR_PDCRB_PD5_Msk         (0x1UL << PWR_PDCRB_PD5_Pos)                 /*!< 0x00000020 */
4709 #define PWR_PDCRB_PD5             PWR_PDCRB_PD5_Msk                            /*!< Pin PB5 Pull-Down set */
4710 #define PWR_PDCRB_PD6_Pos         (6U)
4711 #define PWR_PDCRB_PD6_Msk         (0x1UL << PWR_PDCRB_PD6_Pos)                 /*!< 0x00000040 */
4712 #define PWR_PDCRB_PD6             PWR_PDCRB_PD6_Msk                            /*!< Pin PB6 Pull-Down set */
4713 #define PWR_PDCRB_PD7_Pos         (7U)
4714 #define PWR_PDCRB_PD7_Msk         (0x1UL << PWR_PDCRB_PD7_Pos)                 /*!< 0x00000080 */
4715 #define PWR_PDCRB_PD7             PWR_PDCRB_PD7_Msk                            /*!< Pin PB7 Pull-Down set */
4716 #define PWR_PDCRB_PD8_Pos         (8U)
4717 #define PWR_PDCRB_PD8_Msk         (0x1UL << PWR_PDCRB_PD8_Pos)                 /*!< 0x00000100 */
4718 #define PWR_PDCRB_PD8             PWR_PDCRB_PD8_Msk                            /*!< Pin PB8 Pull-Down set */
4719 #define PWR_PDCRB_PD9_Pos         (9U)
4720 #define PWR_PDCRB_PD9_Msk         (0x1UL << PWR_PDCRB_PD9_Pos)                 /*!< 0x00000200 */
4721 #define PWR_PDCRB_PD9             PWR_PDCRB_PD9_Msk                            /*!< Pin PB9 Pull-Down set */
4722 #define PWR_PDCRB_PD10_Pos        (10U)
4723 #define PWR_PDCRB_PD10_Msk        (0x1UL << PWR_PDCRB_PD10_Pos)                /*!< 0x00000400 */
4724 #define PWR_PDCRB_PD10            PWR_PDCRB_PD10_Msk                           /*!< Pin PB10 Pull-Down set */
4725 #define PWR_PDCRB_PD11_Pos        (11U)
4726 #define PWR_PDCRB_PD11_Msk        (0x1UL << PWR_PDCRB_PD11_Pos)                /*!< 0x00000800 */
4727 #define PWR_PDCRB_PD11            PWR_PDCRB_PD11_Msk                           /*!< Pin PB11 Pull-Down set */
4728 #define PWR_PDCRB_PD12_Pos        (12U)
4729 #define PWR_PDCRB_PD12_Msk        (0x1UL << PWR_PDCRB_PD12_Pos)                /*!< 0x00001000 */
4730 #define PWR_PDCRB_PD12            PWR_PDCRB_PD12_Msk                           /*!< Pin PB12 Pull-Down set */
4731 #define PWR_PDCRB_PD13_Pos        (13U)
4732 #define PWR_PDCRB_PD13_Msk        (0x1UL << PWR_PDCRB_PD13_Pos)                /*!< 0x00002000 */
4733 #define PWR_PDCRB_PD13            PWR_PDCRB_PD13_Msk                           /*!< Pin PB13 Pull-Down set */
4734 #define PWR_PDCRB_PD14_Pos        (14U)
4735 #define PWR_PDCRB_PD14_Msk        (0x1UL << PWR_PDCRB_PD14_Pos)                /*!< 0x00004000 */
4736 #define PWR_PDCRB_PD14            PWR_PDCRB_PD14_Msk                           /*!< Pin PB14 Pull-Down set */
4737 #define PWR_PDCRB_PD15_Pos        (15U)
4738 #define PWR_PDCRB_PD15_Msk        (0x1UL << PWR_PDCRB_PD15_Pos)                /*!< 0x00008000 */
4739 #define PWR_PDCRB_PD15            PWR_PDCRB_PD15_Msk                           /*!< Pin PB15 Pull-Down set */
4740 
4741 /********************  Bit definition for PWR_PUCRC register  *****************/
4742 #define PWR_PUCRC_PU0_Pos         (0U)
4743 #define PWR_PUCRC_PU0_Msk         (0x1UL << PWR_PUCRC_PU0_Pos)                 /*!< 0x00000001 */
4744 #define PWR_PUCRC_PU0             PWR_PUCRC_PU0_Msk                            /*!< Pin PC0 Pull-Up set */
4745 #define PWR_PUCRC_PU1_Pos         (1U)
4746 #define PWR_PUCRC_PU1_Msk         (0x1UL << PWR_PUCRC_PU1_Pos)                 /*!< 0x00000002 */
4747 #define PWR_PUCRC_PU1             PWR_PUCRC_PU1_Msk                            /*!< Pin PC1 Pull-Up set */
4748 #define PWR_PUCRC_PU2_Pos         (2U)
4749 #define PWR_PUCRC_PU2_Msk         (0x1UL << PWR_PUCRC_PU2_Pos)                 /*!< 0x00000004 */
4750 #define PWR_PUCRC_PU2             PWR_PUCRC_PU2_Msk                            /*!< Pin PC2 Pull-Up set */
4751 #define PWR_PUCRC_PU3_Pos         (3U)
4752 #define PWR_PUCRC_PU3_Msk         (0x1UL << PWR_PUCRC_PU3_Pos)                 /*!< 0x00000008 */
4753 #define PWR_PUCRC_PU3             PWR_PUCRC_PU3_Msk                            /*!< Pin PC3 Pull-Up set */
4754 #define PWR_PUCRC_PU4_Pos         (4U)
4755 #define PWR_PUCRC_PU4_Msk         (0x1UL << PWR_PUCRC_PU4_Pos)                 /*!< 0x00000010 */
4756 #define PWR_PUCRC_PU4             PWR_PUCRB_PD4_Msk                            /*!< Pin PC4 Pull-Up set */
4757 #define PWR_PUCRC_PU5_Pos         (5U)
4758 #define PWR_PUCRC_PU5_Msk         (0x1UL << PWR_PUCRC_PU5_Pos)                 /*!< 0x00000020 */
4759 #define PWR_PUCRC_PU5             PWR_PUCRC_PU5_Msk                            /*!< Pin PC5 Pull-Up set */
4760 #define PWR_PUCRC_PU6_Pos         (6U)
4761 #define PWR_PUCRC_PU6_Msk         (0x1UL << PWR_PUCRC_PU6_Pos)                 /*!< 0x00000040 */
4762 #define PWR_PUCRC_PU6             PWR_PUCRC_PU6_Msk                            /*!< Pin PC6 Pull-Up set */
4763 #define PWR_PUCRC_PU7_Pos         (7U)
4764 #define PWR_PUCRC_PU7_Msk         (0x1UL << PWR_PUCRC_PU7_Pos)                 /*!< 0x00000080 */
4765 #define PWR_PUCRC_PU7             PWR_PUCRC_PU7_Msk                            /*!< Pin PC7 Pull-Up set */
4766 #define PWR_PUCRC_PU8_Pos         (8U)
4767 #define PWR_PUCRC_PU8_Msk         (0x1UL << PWR_PUCRC_PU8_Pos)                 /*!< 0x00000100 */
4768 #define PWR_PUCRC_PU8             PWR_PUCRC_PU8_Msk                            /*!< Pin PC8 Pull-Up set */
4769 #define PWR_PUCRC_PU9_Pos         (9U)
4770 #define PWR_PUCRC_PU9_Msk         (0x1UL << PWR_PUCRC_PU9_Pos)                 /*!< 0x00000200 */
4771 #define PWR_PUCRC_PU9             PWR_PUCRC_PU9_Msk                            /*!< Pin PC9 Pull-Up set */
4772 #define PWR_PUCRC_PU10_Pos        (10U)
4773 #define PWR_PUCRC_PU10_Msk        (0x1UL << PWR_PUCRC_PU10_Pos)                /*!< 0x00000400 */
4774 #define PWR_PUCRC_PU10            PWR_PUCRC_PU10_Msk                           /*!< Pin PC10 Pull-Up set */
4775 #define PWR_PUCRC_PU11_Pos        (11U)
4776 #define PWR_PUCRC_PU11_Msk        (0x1UL << PWR_PUCRC_PU11_Pos)                /*!< 0x00000800 */
4777 #define PWR_PUCRC_PU11            PWR_PUCRC_PU11_Msk                           /*!< Pin PC11 Pull-Up set */
4778 #define PWR_PUCRC_PU12_Pos        (12U)
4779 #define PWR_PUCRC_PU12_Msk        (0x1UL << PWR_PUCRC_PU12_Pos)                /*!< 0x00001000 */
4780 #define PWR_PUCRC_PU12            PWR_PUCRC_PU12_Msk                           /*!< Pin PC12 Pull-Up set */
4781 #define PWR_PUCRC_PU13_Pos        (13U)
4782 #define PWR_PUCRC_PU13_Msk        (0x1UL << PWR_PUCRC_PU13_Pos)                /*!< 0x00002000 */
4783 #define PWR_PUCRC_PU13            PWR_PUCRC_PU13_Msk                           /*!< Pin PC13 Pull-Up set */
4784 #define PWR_PUCRC_PU14_Pos        (14U)
4785 #define PWR_PUCRC_PU14_Msk        (0x1UL << PWR_PUCRC_PU14_Pos)                /*!< 0x00004000 */
4786 #define PWR_PUCRC_PU14            PWR_PUCRC_PU14_Msk                           /*!< Pin PC14 Pull-Up set */
4787 #define PWR_PUCRC_PU15_Pos        (15U)
4788 #define PWR_PUCRC_PU15_Msk        (0x1UL << PWR_PUCRC_PU15_Pos)                /*!< 0x00008000 */
4789 #define PWR_PUCRC_PU15            PWR_PUCRC_PU15_Msk                           /*!< Pin PC15 Pull-Up set */
4790 
4791 /********************  Bit definition for PWR_PDCRC register  *****************/
4792 #define PWR_PDCRC_PD0_Pos         (0U)
4793 #define PWR_PDCRC_PD0_Msk         (0x1UL << PWR_PDCRC_PD0_Pos)                 /*!< 0x00000001 */
4794 #define PWR_PDCRC_PD0             PWR_PDCRC_PD0_Msk                            /*!< Pin PC0 Pull-Down set */
4795 #define PWR_PDCRC_PD1_Pos         (1U)
4796 #define PWR_PDCRC_PD1_Msk         (0x1UL << PWR_PDCRC_PD1_Pos)                 /*!< 0x00000002 */
4797 #define PWR_PDCRC_PD1             PWR_PDCRC_PD1_Msk                            /*!< Pin PC1 Pull-Down set */
4798 #define PWR_PDCRC_PD2_Pos         (2U)
4799 #define PWR_PDCRC_PD2_Msk         (0x1UL << PWR_PDCRC_PD2_Pos)                 /*!< 0x00000004 */
4800 #define PWR_PDCRC_PD2             PWR_PDCRC_PD2_Msk                            /*!< Pin PC2 Pull-Down set */
4801 #define PWR_PDCRC_PD3_Pos         (3U)
4802 #define PWR_PDCRC_PD3_Msk         (0x1UL << PWR_PDCRC_PD3_Pos)                 /*!< 0x00000008 */
4803 #define PWR_PDCRC_PD3             PWR_PDCRC_PD3_Msk                            /*!< Pin PC3 Pull-Down set */
4804 #define PWR_PDCRC_PD4_Pos         (4U)
4805 #define PWR_PDCRC_PD4_Msk         (0x1UL << PWR_PDCRC_PD4_Pos)                 /*!< 0x00000010 */
4806 #define PWR_PDCRC_PD4             PWR_PUCRB_PD4_Msk                            /*!< Pin PC4 Pull-Down set */
4807 #define PWR_PDCRC_PD5_Pos         (5U)
4808 #define PWR_PDCRC_PD5_Msk         (0x1UL << PWR_PDCRC_PD5_Pos)                 /*!< 0x00000020 */
4809 #define PWR_PDCRC_PD5             PWR_PDCRC_PD5_Msk                            /*!< Pin PC5 Pull-Down set */
4810 #define PWR_PDCRC_PD6_Pos         (6U)
4811 #define PWR_PDCRC_PD6_Msk         (0x1UL << PWR_PDCRC_PD6_Pos)                 /*!< 0x00000040 */
4812 #define PWR_PDCRC_PD6             PWR_PDCRC_PD6_Msk                            /*!< Pin PC6 Pull-Down set */
4813 #define PWR_PDCRC_PD7_Pos         (7U)
4814 #define PWR_PDCRC_PD7_Msk         (0x1UL << PWR_PDCRC_PD7_Pos)                 /*!< 0x00000080 */
4815 #define PWR_PDCRC_PD7             PWR_PDCRC_PD7_Msk                            /*!< Pin PC7 Pull-Down set */
4816 #define PWR_PDCRC_PD8_Pos         (8U)
4817 #define PWR_PDCRC_PD8_Msk         (0x1UL << PWR_PDCRC_PD8_Pos)                 /*!< 0x00000100 */
4818 #define PWR_PDCRC_PD8             PWR_PDCRC_PD8_Msk                            /*!< Pin PC8 Pull-Down set */
4819 #define PWR_PDCRC_PD9_Pos         (9U)
4820 #define PWR_PDCRC_PD9_Msk         (0x1UL << PWR_PDCRC_PD9_Pos)                 /*!< 0x00000200 */
4821 #define PWR_PDCRC_PD9             PWR_PDCRC_PD9_Msk                            /*!< Pin PC9 Pull-Down set */
4822 #define PWR_PDCRC_PD10_Pos        (10U)
4823 #define PWR_PDCRC_PD10_Msk        (0x1UL << PWR_PDCRC_PD10_Pos)                /*!< 0x00000400 */
4824 #define PWR_PDCRC_PD10            PWR_PDCRC_PD10_Msk                           /*!< Pin PC10 Pull-Down set */
4825 #define PWR_PDCRC_PD11_Pos        (11U)
4826 #define PWR_PDCRC_PD11_Msk        (0x1UL << PWR_PDCRC_PD11_Pos)                /*!< 0x00000800 */
4827 #define PWR_PDCRC_PD11            PWR_PDCRC_PD11_Msk                           /*!< Pin PC11 Pull-Down set */
4828 #define PWR_PDCRC_PD12_Pos        (12U)
4829 #define PWR_PDCRC_PD12_Msk        (0x1UL << PWR_PDCRC_PD12_Pos)                /*!< 0x00001000 */
4830 #define PWR_PDCRC_PD12            PWR_PDCRC_PD12_Msk                           /*!< Pin PC12 Pull-Down set */
4831 #define PWR_PDCRC_PD13_Pos        (13U)
4832 #define PWR_PDCRC_PD13_Msk        (0x1UL << PWR_PDCRC_PD13_Pos)                /*!< 0x00002000 */
4833 #define PWR_PDCRC_PD13            PWR_PDCRC_PD13_Msk                           /*!< Pin PC13 Pull-Down set */
4834 #define PWR_PDCRC_PD14_Pos        (14U)
4835 #define PWR_PDCRC_PD14_Msk        (0x1UL << PWR_PDCRC_PD14_Pos)                /*!< 0x00004000 */
4836 #define PWR_PDCRC_PD14            PWR_PDCRC_PD14_Msk                           /*!< Pin PC14 Pull-Down set */
4837 #define PWR_PDCRC_PD15_Pos        (15U)
4838 #define PWR_PDCRC_PD15_Msk        (0x1UL << PWR_PDCRC_PD15_Pos)                /*!< 0x00008000 */
4839 #define PWR_PDCRC_PD15            PWR_PDCRC_PD15_Msk                           /*!< Pin PC15 Pull-Down set */
4840 
4841 /********************  Bit definition for PWR_PUCRD register  *****************/
4842 #define PWR_PUCRD_PU2_Pos         (2U)
4843 #define PWR_PUCRD_PU2_Msk         (0x1UL << PWR_PUCRD_PU2_Pos)                 /*!< 0x00000004 */
4844 #define PWR_PUCRD_PU2             PWR_PUCRD_PU2_Msk                            /*!< Pin PD2 Pull-Up set */
4845 
4846 /********************  Bit definition for PWR_PDCRD register  *****************/
4847 #define PWR_PDCRD_PD2_Pos         (2U)
4848 #define PWR_PDCRD_PD2_Msk         (0x1UL << PWR_PDCRD_PD2_Pos)                 /*!< 0x00000004 */
4849 #define PWR_PDCRD_PD2             PWR_PDCRD_PD2_Msk                            /*!< Pin PD2 Pull-Down set */
4850 
4851 
4852 /********************  Bit definition for PWR_PUCRF register  *****************/
4853 #define PWR_PUCRF_PU0_Pos         (0U)
4854 #define PWR_PUCRF_PU0_Msk         (0x1UL << PWR_PUCRF_PU0_Pos)                 /*!< 0x00000001 */
4855 #define PWR_PUCRF_PU0             PWR_PUCRF_PU0_Msk                            /*!< Pin PF0 Pull-Up set */
4856 #define PWR_PUCRF_PU1_Pos         (1U)
4857 #define PWR_PUCRF_PU1_Msk         (0x1UL << PWR_PUCRF_PU1_Pos)                 /*!< 0x00000002 */
4858 #define PWR_PUCRF_PU1             PWR_PUCRF_PU1_Msk                            /*!< Pin PF1 Pull-Up set */
4859 #define PWR_PUCRF_PU2_Pos         (2U)
4860 #define PWR_PUCRF_PU2_Msk         (0x1UL << PWR_PUCRF_PU2_Pos)                 /*!< 0x00000004 */
4861 #define PWR_PUCRF_PU2             PWR_PUCRF_PU2_Msk                            /*!< Pin PF2 Pull-Up set */
4862 #define PWR_PUCRF_PU3_Pos         (3U)
4863 #define PWR_PUCRF_PU3_Msk         (0x1UL << PWR_PUCRF_PU3_Pos)                 /*!< 0x00000008 */
4864 #define PWR_PUCRF_PU3             PWR_PUCRF_PU3_Msk                            /*!< Pin PF3 Pull-Up set */
4865 
4866 /********************  Bit definition for PWR_PDCRF register  *****************/
4867 #define PWR_PDCRF_PD0_Pos         (0U)
4868 #define PWR_PDCRF_PD0_Msk         (0x1UL << PWR_PDCRF_PD0_Pos)                 /*!< 0x00000001 */
4869 #define PWR_PDCRF_PD0             PWR_PDCRF_PD0_Msk                            /*!< Pin PF0 Pull-Down set */
4870 #define PWR_PDCRF_PD1_Pos         (1U)
4871 #define PWR_PDCRF_PD1_Msk         (0x1UL << PWR_PDCRF_PD1_Pos)                 /*!< 0x00000002 */
4872 #define PWR_PDCRF_PD1             PWR_PDCRF_PD1_Msk                            /*!< Pin PF1 Pull-Down set */
4873 #define PWR_PDCRF_PD2_Pos         (2U)
4874 #define PWR_PDCRF_PD2_Msk         (0x1UL << PWR_PDCRF_PD2_Pos)                 /*!< 0x00000004 */
4875 #define PWR_PDCRF_PD2             PWR_PDCRF_PD2_Msk                            /*!< Pin PF2 Pull-Down set */
4876 #define PWR_PDCRF_PD3_Pos         (3U)
4877 #define PWR_PDCRF_PD3_Msk         (0x1UL << PWR_PDCRF_PD3_Pos)                 /*!< 0x00000008 */
4878 #define PWR_PDCRF_PD3             PWR_PDCRF_PD3_Msk                            /*!< Pin PF3 Pull-Down set */
4879 
4880 
4881 /******************************************************************************/
4882 /*                                                                            */
4883 /*                           Reset and Clock Control                          */
4884 /*                                                                            */
4885 /******************************************************************************/
4886 
4887 /********************  Bit definition for RCC_CR register  ********************/
4888 #define RCC_CR_MSION_Pos                     (0U)
4889 #define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
4890 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
4891 #define RCC_CR_MSIRDY_Pos                    (1U)
4892 #define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
4893 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
4894 #define RCC_CR_MSIPLLEN_Pos                  (2U)
4895 #define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
4896 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
4897 #define RCC_CR_MSIRGSEL_Pos                  (3U)
4898 #define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
4899 #define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
4900 
4901 /*!< MSIRANGE configuration : 12 frequency ranges available */
4902 #define RCC_CR_MSIRANGE_Pos                  (4U)
4903 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
4904 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
4905 #define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
4906 #define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
4907 #define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
4908 #define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
4909 #define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
4910 #define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
4911 #define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
4912 #define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
4913 #define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
4914 #define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
4915 #define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
4916 #define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
4917 
4918 #define RCC_CR_HSION_Pos                     (8U)
4919 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
4920 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
4921 #define RCC_CR_HSIKERON_Pos                  (9U)
4922 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
4923 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
4924 #define RCC_CR_HSIRDY_Pos                    (10U)
4925 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
4926 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
4927 #define RCC_CR_HSIASFS_Pos                   (11U)
4928 #define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
4929 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
4930 
4931 #define RCC_CR_HSEON_Pos                     (16U)
4932 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
4933 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
4934 #define RCC_CR_HSERDY_Pos                    (17U)
4935 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
4936 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
4937 #define RCC_CR_HSEBYP_Pos                    (18U)
4938 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
4939 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
4940 #define RCC_CR_CSSON_Pos                     (19U)
4941 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
4942 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
4943 
4944 #define RCC_CR_PLLON_Pos                     (24U)
4945 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
4946 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
4947 #define RCC_CR_PLLRDY_Pos                    (25U)
4948 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
4949 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
4950 
4951 /********************  Bit definition for RCC_ICSCR register  ***************/
4952 /*!< MSICAL configuration */
4953 #define RCC_ICSCR_MSICAL_Pos                 (0U)
4954 #define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
4955 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
4956 #define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */
4957 #define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */
4958 #define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */
4959 #define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */
4960 #define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */
4961 #define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */
4962 #define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */
4963 #define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */
4964 
4965 /*!< MSITRIM configuration */
4966 #define RCC_ICSCR_MSITRIM_Pos                (8U)
4967 #define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
4968 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
4969 #define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
4970 #define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
4971 #define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
4972 #define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
4973 #define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
4974 #define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
4975 #define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
4976 #define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
4977 
4978 /*!< HSICAL configuration */
4979 #define RCC_ICSCR_HSICAL_Pos                 (16U)
4980 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
4981 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
4982 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
4983 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
4984 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
4985 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
4986 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
4987 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
4988 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
4989 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
4990 
4991 /*!< HSITRIM configuration */
4992 #define RCC_ICSCR_HSITRIM_Pos                (24U)
4993 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
4994 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
4995 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
4996 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
4997 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
4998 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
4999 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
5000 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
5001 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
5002 
5003 /********************  Bit definition for RCC_CFGR register  ***************/
5004 /*!< SW configuration */
5005 #define RCC_CFGR_SW_Pos                (0U)
5006 #define RCC_CFGR_SW_Msk                (0x7UL << RCC_CFGR_SW_Pos)              /*!< 0x00000007 */
5007 #define RCC_CFGR_SW                    RCC_CFGR_SW_Msk                         /*!< SW[2:0] bits (System clock Switch) */
5008 #define RCC_CFGR_SW_0                  (0x1UL << RCC_CFGR_SW_Pos)              /*!< 0x00000001 */
5009 #define RCC_CFGR_SW_1                  (0x2UL << RCC_CFGR_SW_Pos)              /*!< 0x00000002 */
5010 #define RCC_CFGR_SW_2                  (0x4UL << RCC_CFGR_SW_Pos)              /*!< 0x00000004 */
5011 
5012 /*!< SWS configuration */
5013 #define RCC_CFGR_SWS_Pos               (3U)
5014 #define RCC_CFGR_SWS_Msk               (0x7UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000038 */
5015 #define RCC_CFGR_SWS                   RCC_CFGR_SWS_Msk                        /*!< SWS[2:0] bits (System Clock Switch Status) */
5016 #define RCC_CFGR_SWS_0                 (0x1UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000008 */
5017 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
5018 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
5019 
5020 /*!< HPRE configuration */
5021 #define RCC_CFGR_HPRE_Pos              (8U)
5022 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
5023 #define RCC_CFGR_HPRE                  RCC_CFGR_HPRE_Msk                       /*!< HPRE[3:0] bits (AHB prescaler) */
5024 #define RCC_CFGR_HPRE_0                (0x1UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000100 */
5025 #define RCC_CFGR_HPRE_1                (0x2UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000200 */
5026 #define RCC_CFGR_HPRE_2                (0x4UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000400 */
5027 #define RCC_CFGR_HPRE_3                (0x8UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000800 */
5028 
5029 /*!< PPRE configuration */
5030 #define RCC_CFGR_PPRE_Pos              (12U)
5031 #define RCC_CFGR_PPRE_Msk              (0x7UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00007000 */
5032 #define RCC_CFGR_PPRE                  RCC_CFGR_PPRE_Msk                       /*!< PRE1[2:0] bits (APB prescaler) */
5033 #define RCC_CFGR_PPRE_0                (0x1UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00001000 */
5034 #define RCC_CFGR_PPRE_1                (0x2UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00002000 */
5035 #define RCC_CFGR_PPRE_2                (0x4UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00004000 */
5036 
5037 /*!< STOPWUCK configuration */
5038 #define RCC_CFGR_STOPWUCK_Pos          (15U)
5039 #define RCC_CFGR_STOPWUCK_Msk          (0x1UL << RCC_CFGR_STOPWUCK_Pos)        /*!< 0x00008000 */
5040 #define RCC_CFGR_STOPWUCK              RCC_CFGR_STOPWUCK_Msk                   /*!< Wake Up from stop and CSS backup clock selection */
5041 
5042 /*!< MCOSEL configuration */
5043 #define RCC_CFGR_MCO2SEL_Pos            (16U)
5044 #define RCC_CFGR_MCO2SEL_Msk            (0xFUL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x000F0000 */
5045 #define RCC_CFGR_MCO2SEL                RCC_CFGR_MCO2SEL_Msk                   /*!< MCO2SEL [3:0] bits (Clock output selection) */
5046 #define RCC_CFGR_MCO2SEL_0              (0x1UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00010000 */
5047 #define RCC_CFGR_MCO2SEL_1              (0x2UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00020000 */
5048 #define RCC_CFGR_MCO2SEL_2              (0x4UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00040000 */
5049 #define RCC_CFGR_MCO2SEL_3              (0x8UL << RCC_CFGR_MCO2SEL_Pos)        /*!< 0x00080000 */
5050 
5051 /*!< MCO Prescaler configuration */
5052 #define RCC_CFGR_MCO2PRE_Pos            (20U)
5053 #define RCC_CFGR_MCO2PRE_Msk            (0xFUL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00F00000 */
5054 #define RCC_CFGR_MCO2PRE                RCC_CFGR_MCO2PRE_Msk                   /*!< MCO1 prescaler [3:0] */
5055 #define RCC_CFGR_MCO2PRE_0              (0x1UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00100000 */
5056 #define RCC_CFGR_MCO2PRE_1              (0x2UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00200000 */
5057 #define RCC_CFGR_MCO2PRE_2              (0x4UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00400000 */
5058 #define RCC_CFGR_MCO2PRE_3              (0x8UL << RCC_CFGR_MCO2PRE_Pos)        /*!< 0x00800000 */
5059 
5060 /*!< MCOSEL configuration */
5061 #define RCC_CFGR_MCO1SEL_Pos            (24U)
5062 #define RCC_CFGR_MCO1SEL_Msk            (0xFUL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x0F000000 */
5063 #define RCC_CFGR_MCO1SEL                RCC_CFGR_MCO1SEL_Msk                   /*!< MCO1SEL [3:0] bits (Clock output selection) */
5064 #define RCC_CFGR_MCO1SEL_0              (0x1UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x01000000 */
5065 #define RCC_CFGR_MCO1SEL_1              (0x2UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x02000000 */
5066 #define RCC_CFGR_MCO1SEL_2              (0x4UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x04000000 */
5067 #define RCC_CFGR_MCO1SEL_3              (0x8UL << RCC_CFGR_MCO1SEL_Pos)        /*!< 0x08000000 */
5068 
5069 /*!< MCO Prescaler configuration */
5070 #define RCC_CFGR_MCO1PRE_Pos            (28U)
5071 #define RCC_CFGR_MCO1PRE_Msk            (0xFUL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0xF0000000 */
5072 #define RCC_CFGR_MCO1PRE                RCC_CFGR_MCO1PRE_Msk                   /*!< MCO1 prescaler [3:0] */
5073 #define RCC_CFGR_MCO1PRE_0              (0x1UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x10000000 */
5074 #define RCC_CFGR_MCO1PRE_1              (0x2UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x20000000 */
5075 #define RCC_CFGR_MCO1PRE_2              (0x4UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x40000000 */
5076 #define RCC_CFGR_MCO1PRE_3              (0x8UL << RCC_CFGR_MCO1PRE_Pos)        /*!< 0x80000000 */
5077 
5078 /********************  Bit definition for RCC_PLLCFGR register  ***************/
5079 #define RCC_PLLCFGR_PLLSRC_Pos         (0U)
5080 #define RCC_PLLCFGR_PLLSRC_Msk         (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)       /*!< 0x00000003 */
5081 #define RCC_PLLCFGR_PLLSRC             RCC_PLLCFGR_PLLSRC_Msk
5082 #define RCC_PLLCFGR_PLLSRC_0           (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)       /*!< 0x00000001 */
5083 #define RCC_PLLCFGR_PLLSRC_1           (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)       /*!< 0x00000002 */
5084 
5085 #define RCC_PLLCFGR_PLLM_Pos           (4U)
5086 #define RCC_PLLCFGR_PLLM_Msk           (0x7UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000070 */
5087 #define RCC_PLLCFGR_PLLM               RCC_PLLCFGR_PLLM_Msk
5088 #define RCC_PLLCFGR_PLLM_0             (0x1UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000010 */
5089 #define RCC_PLLCFGR_PLLM_1             (0x2UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000020 */
5090 #define RCC_PLLCFGR_PLLM_2             (0x4UL << RCC_PLLCFGR_PLLM_Pos)         /*!< 0x00000040 */
5091 
5092 #define RCC_PLLCFGR_PLLN_Pos           (8U)
5093 #define RCC_PLLCFGR_PLLN_Msk           (0x7FUL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00007F00 */
5094 #define RCC_PLLCFGR_PLLN               RCC_PLLCFGR_PLLN_Msk
5095 #define RCC_PLLCFGR_PLLN_0             (0x01UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000100 */
5096 #define RCC_PLLCFGR_PLLN_1             (0x02UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000200 */
5097 #define RCC_PLLCFGR_PLLN_2             (0x04UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000400 */
5098 #define RCC_PLLCFGR_PLLN_3             (0x08UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00000800 */
5099 #define RCC_PLLCFGR_PLLN_4             (0x10UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00001000 */
5100 #define RCC_PLLCFGR_PLLN_5             (0x20UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00002000 */
5101 #define RCC_PLLCFGR_PLLN_6             (0x40UL << RCC_PLLCFGR_PLLN_Pos)        /*!< 0x00004000 */
5102 
5103 #define RCC_PLLCFGR_PLLPEN_Pos         (16U)
5104 #define RCC_PLLCFGR_PLLPEN_Msk         (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)       /*!< 0x00010000 */
5105 #define RCC_PLLCFGR_PLLPEN             RCC_PLLCFGR_PLLPEN_Msk
5106 #define RCC_PLLCFGR_PLLP_Pos           (17U)
5107 #define RCC_PLLCFGR_PLLP_Msk           (0x1FUL << RCC_PLLCFGR_PLLP_Pos)        /*!< 0x003E0000 */
5108 #define RCC_PLLCFGR_PLLP               RCC_PLLCFGR_PLLP_Msk
5109 #define RCC_PLLCFGR_PLLP_0             (0x1UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00020000 */
5110 #define RCC_PLLCFGR_PLLP_1             (0x2UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00040000 */
5111 #define RCC_PLLCFGR_PLLP_2             (0x4UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00080000 */
5112 #define RCC_PLLCFGR_PLLP_3             (0x8UL << RCC_PLLCFGR_PLLP_Pos)         /*!< 0x00100000 */
5113 #define RCC_PLLCFGR_PLLP_4             (0x10UL << RCC_PLLCFGR_PLLP_Pos)        /*!< 0x00200000 */
5114 
5115 #define RCC_PLLCFGR_PLLQEN_Pos         (24U)
5116 #define RCC_PLLCFGR_PLLQEN_Msk         (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)       /*!< 0x01000000 */
5117 #define RCC_PLLCFGR_PLLQEN             RCC_PLLCFGR_PLLQEN_Msk
5118 
5119 #define RCC_PLLCFGR_PLLQ_Pos           (25U)
5120 #define RCC_PLLCFGR_PLLQ_Msk           (0x7UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x0E000000 */
5121 #define RCC_PLLCFGR_PLLQ               RCC_PLLCFGR_PLLQ_Msk
5122 #define RCC_PLLCFGR_PLLQ_0             (0x1UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x02000000 */
5123 #define RCC_PLLCFGR_PLLQ_1             (0x2UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x04000000 */
5124 #define RCC_PLLCFGR_PLLQ_2             (0x4UL << RCC_PLLCFGR_PLLQ_Pos)         /*!< 0x08000000 */
5125 
5126 #define RCC_PLLCFGR_PLLREN_Pos         (28U)
5127 #define RCC_PLLCFGR_PLLREN_Msk         (0x1UL << RCC_PLLCFGR_PLLREN_Pos)       /*!< 0x01000000 */
5128 #define RCC_PLLCFGR_PLLREN             RCC_PLLCFGR_PLLREN_Msk
5129 #define RCC_PLLCFGR_PLLR_Pos           (29U)
5130 #define RCC_PLLCFGR_PLLR_Msk           (0x7UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0xE0000000 */
5131 #define RCC_PLLCFGR_PLLR               RCC_PLLCFGR_PLLR_Msk
5132 #define RCC_PLLCFGR_PLLR_0             (0x1UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0x20000000 */
5133 #define RCC_PLLCFGR_PLLR_1             (0x2UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0x40000000 */
5134 #define RCC_PLLCFGR_PLLR_2             (0x4UL << RCC_PLLCFGR_PLLR_Pos)         /*!< 0x80000000 */
5135 
5136 /********************  Bit definition for RCC_CIER register  ******************/
5137 #define RCC_CIER_LSIRDYIE_Pos          (0U)
5138 #define RCC_CIER_LSIRDYIE_Msk          (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
5139 #define RCC_CIER_LSIRDYIE              RCC_CIER_LSIRDYIE_Msk
5140 #define RCC_CIER_LSERDYIE_Pos          (1U)
5141 #define RCC_CIER_LSERDYIE_Msk          (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
5142 #define RCC_CIER_LSERDYIE              RCC_CIER_LSERDYIE_Msk
5143 #define RCC_CIER_MSIRDYIE_Pos          (2U)
5144 #define RCC_CIER_MSIRDYIE_Msk          (0x1UL << RCC_CIER_MSIRDYIE_Pos)        /*!< 0x00000004 */
5145 #define RCC_CIER_MSIRDYIE              RCC_CIER_MSIRDYIE_Msk
5146 #define RCC_CIER_HSIRDYIE_Pos          (3U)
5147 #define RCC_CIER_HSIRDYIE_Msk          (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
5148 #define RCC_CIER_HSIRDYIE              RCC_CIER_HSIRDYIE_Msk
5149 #define RCC_CIER_HSERDYIE_Pos          (4U)
5150 #define RCC_CIER_HSERDYIE_Msk          (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
5151 #define RCC_CIER_HSERDYIE              RCC_CIER_HSERDYIE_Msk
5152 #define RCC_CIER_PLLRDYIE_Pos          (5U)
5153 #define RCC_CIER_PLLRDYIE_Msk          (0x1UL << RCC_CIER_PLLRDYIE_Pos)        /*!< 0x00000020 */
5154 #define RCC_CIER_PLLRDYIE              RCC_CIER_PLLRDYIE_Msk
5155 
5156 #define RCC_CIER_LSECSSIE_Pos          (9U)
5157 #define RCC_CIER_LSECSSIE_Msk          (0x1UL << RCC_CIER_LSECSSIE_Pos)        /*!< 0x00000200 */
5158 #define RCC_CIER_LSECSSIE              RCC_CIER_LSECSSIE_Msk
5159 /********************  Bit definition for RCC_CIFR register  ******************/
5160 #define RCC_CIFR_LSIRDYF_Pos           (0U)
5161 #define RCC_CIFR_LSIRDYF_Msk           (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
5162 #define RCC_CIFR_LSIRDYF               RCC_CIFR_LSIRDYF_Msk
5163 #define RCC_CIFR_LSERDYF_Pos           (1U)
5164 #define RCC_CIFR_LSERDYF_Msk           (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
5165 #define RCC_CIFR_LSERDYF               RCC_CIFR_LSERDYF_Msk
5166 #define RCC_CIFR_MSIRDYF_Pos           (2U)
5167 #define RCC_CIFR_MSIRDYF_Msk           (0x1UL << RCC_CIFR_MSIRDYF_Pos)         /*!< 0x00000004 */
5168 #define RCC_CIFR_MSIRDYF               RCC_CIFR_MSIRDYF_Msk
5169 #define RCC_CIFR_HSIRDYF_Pos           (3U)
5170 #define RCC_CIFR_HSIRDYF_Msk           (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000008 */
5171 #define RCC_CIFR_HSIRDYF               RCC_CIFR_HSIRDYF_Msk
5172 #define RCC_CIFR_HSERDYF_Pos           (4U)
5173 #define RCC_CIFR_HSERDYF_Msk           (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000010 */
5174 #define RCC_CIFR_HSERDYF               RCC_CIFR_HSERDYF_Msk
5175 #define RCC_CIFR_PLLRDYF_Pos           (5U)
5176 #define RCC_CIFR_PLLRDYF_Msk           (0x1UL << RCC_CIFR_PLLRDYF_Pos)         /*!< 0x00000020 */
5177 #define RCC_CIFR_PLLRDYF               RCC_CIFR_PLLRDYF_Msk
5178 
5179 #define RCC_CIFR_CSSF_Pos              (8U)
5180 #define RCC_CIFR_CSSF_Msk              (0x1UL << RCC_CIFR_CSSF_Pos)            /*!< 0x00000100 */
5181 #define RCC_CIFR_CSSF                  RCC_CIFR_CSSF_Msk
5182 #define RCC_CIFR_LSECSSF_Pos           (9U)
5183 #define RCC_CIFR_LSECSSF_Msk           (0x1UL << RCC_CIFR_LSECSSF_Pos)         /*!< 0x00000200 */
5184 #define RCC_CIFR_LSECSSF               RCC_CIFR_LSECSSF_Msk
5185 /********************  Bit definition for RCC_CICR register  ******************/
5186 #define RCC_CICR_LSIRDYC_Pos           (0U)
5187 #define RCC_CICR_LSIRDYC_Msk           (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
5188 #define RCC_CICR_LSIRDYC               RCC_CICR_LSIRDYC_Msk
5189 #define RCC_CICR_LSERDYC_Pos           (1U)
5190 #define RCC_CICR_LSERDYC_Msk           (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
5191 #define RCC_CICR_LSERDYC               RCC_CICR_LSERDYC_Msk
5192 #define RCC_CICR_MSIRDYC_Pos           (2U)
5193 #define RCC_CICR_MSIRDYC_Msk           (0x1UL << RCC_CICR_MSIRDYC_Pos)         /*!< 0x00000004 */
5194 #define RCC_CICR_MSIRDYC               RCC_CICR_MSIRDYC_Msk
5195 #define RCC_CICR_HSIRDYC_Pos           (3U)
5196 #define RCC_CICR_HSIRDYC_Msk           (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000008 */
5197 #define RCC_CICR_HSIRDYC               RCC_CICR_HSIRDYC_Msk
5198 #define RCC_CICR_HSERDYC_Pos           (4U)
5199 #define RCC_CICR_HSERDYC_Msk           (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000010 */
5200 #define RCC_CICR_HSERDYC               RCC_CICR_HSERDYC_Msk
5201 #define RCC_CICR_PLLRDYC_Pos           (5U)
5202 #define RCC_CICR_PLLRDYC_Msk           (0x1UL << RCC_CICR_PLLRDYC_Pos)         /*!< 0x00000020 */
5203 #define RCC_CICR_PLLRDYC               RCC_CICR_PLLRDYC_Msk
5204 
5205 #define RCC_CICR_CSSC_Pos              (8U)
5206 #define RCC_CICR_CSSC_Msk              (0x1UL << RCC_CICR_CSSC_Pos)            /*!< 0x00000100 */
5207 #define RCC_CICR_CSSC                  RCC_CICR_CSSC_Msk
5208 #define RCC_CICR_LSECSSC_Pos           (9U)
5209 #define RCC_CICR_LSECSSC_Msk           (0x1UL << RCC_CICR_LSECSSC_Pos)         /*!< 0x00000200 */
5210 #define RCC_CICR_LSECSSC               RCC_CICR_LSECSSC_Msk
5211 /********************  Bit definition for RCC_AHB1RSTR register  ***************/
5212 #define RCC_AHBRSTR_DMA1RST_Pos       (0U)
5213 #define RCC_AHBRSTR_DMA1RST_Msk       (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)       /*!< 0x00000001 */
5214 #define RCC_AHBRSTR_DMA1RST           RCC_AHBRSTR_DMA1RST_Msk
5215 #define RCC_AHBRSTR_FLASHRST_Pos      (8U)
5216 #define RCC_AHBRSTR_FLASHRST_Msk      (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)      /*!< 0x00000100 */
5217 #define RCC_AHBRSTR_FLASHRST          RCC_AHBRSTR_FLASHRST_Msk
5218 #define RCC_AHBRSTR_CRCRST_Pos        (12U)
5219 #define RCC_AHBRSTR_CRCRST_Msk        (0x1UL << RCC_AHBRSTR_CRCRST_Pos)        /*!< 0x00001000 */
5220 #define RCC_AHBRSTR_CRCRST            RCC_AHBRSTR_CRCRST_Msk
5221 #define RCC_AHBRSTR_RNGRST_Pos        (18U)
5222 #define RCC_AHBRSTR_RNGRST_Msk        (0x1UL << RCC_AHBRSTR_RNGRST_Pos)        /*!< 0x00040000 */
5223 #define RCC_AHBRSTR_RNGRST            RCC_AHBRSTR_RNGRST_Msk
5224 #define RCC_AHBRSTR_TSCRST_Pos        (24U)
5225 #define RCC_AHBRSTR_TSCRST_Msk        (0x1UL << RCC_AHBRSTR_TSCRST_Pos)        /*!< 0x01000000 */
5226 #define RCC_AHBRSTR_TSCRST            RCC_AHBRSTR_TSCRST_Msk
5227 
5228 /********************  Bit definition for RCC_IOPRSTR register  **************/
5229 #define RCC_IOPRSTR_GPIOARST_Pos       (0U)
5230 #define RCC_IOPRSTR_GPIOARST_Msk       (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)     /*!< 0x00000001 */
5231 #define RCC_IOPRSTR_GPIOARST           RCC_IOPRSTR_GPIOARST_Msk
5232 #define RCC_IOPRSTR_GPIOBRST_Pos       (1U)
5233 #define RCC_IOPRSTR_GPIOBRST_Msk       (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)     /*!< 0x00000002 */
5234 #define RCC_IOPRSTR_GPIOBRST           RCC_IOPRSTR_GPIOBRST_Msk
5235 #define RCC_IOPRSTR_GPIOCRST_Pos       (2U)
5236 #define RCC_IOPRSTR_GPIOCRST_Msk       (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)     /*!< 0x00000004 */
5237 #define RCC_IOPRSTR_GPIOCRST           RCC_IOPRSTR_GPIOCRST_Msk
5238 #define RCC_IOPRSTR_GPIODRST_Pos       (3U)
5239 #define RCC_IOPRSTR_GPIODRST_Msk       (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)     /*!< 0x00000008 */
5240 #define RCC_IOPRSTR_GPIODRST           RCC_IOPRSTR_GPIODRST_Msk
5241 #define RCC_IOPRSTR_GPIOFRST_Pos       (5U)
5242 #define RCC_IOPRSTR_GPIOFRST_Msk       (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)     /*!< 0x00000020 */
5243 #define RCC_IOPRSTR_GPIOFRST           RCC_IOPRSTR_GPIOFRST_Msk
5244 
5245 /********************  Bit definition for RCC_APBRSTR1 register  **************/
5246 #define RCC_APBRSTR1_TIM2RST_Pos       (0U)
5247 #define RCC_APBRSTR1_TIM2RST_Msk       (0x1UL << RCC_APBRSTR1_TIM2RST_Pos)     /*!< 0x00000001 */
5248 #define RCC_APBRSTR1_TIM2RST           RCC_APBRSTR1_TIM2RST_Msk
5249 #define RCC_APBRSTR1_TIM3RST_Pos       (1U)
5250 #define RCC_APBRSTR1_TIM3RST_Msk       (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)     /*!< 0x00000002 */
5251 #define RCC_APBRSTR1_TIM3RST           RCC_APBRSTR1_TIM3RST_Msk
5252 #define RCC_APBRSTR1_TIM6RST_Pos       (4U)
5253 #define RCC_APBRSTR1_TIM6RST_Msk       (0x1UL << RCC_APBRSTR1_TIM6RST_Pos)     /*!< 0x00000010 */
5254 #define RCC_APBRSTR1_TIM6RST           RCC_APBRSTR1_TIM6RST_Msk
5255 #define RCC_APBRSTR1_TIM7RST_Pos       (5U)
5256 #define RCC_APBRSTR1_TIM7RST_Msk       (0x1UL << RCC_APBRSTR1_TIM7RST_Pos)     /*!< 0x00000020 */
5257 #define RCC_APBRSTR1_TIM7RST           RCC_APBRSTR1_TIM7RST_Msk
5258 #define RCC_APBRSTR1_LPUART2RST_Pos    (7U)
5259 #define RCC_APBRSTR1_LPUART2RST_Msk    (0x1UL << RCC_APBRSTR1_LPUART2RST_Pos)  /*!< 0x00000080 */
5260 #define RCC_APBRSTR1_LPUART2RST        RCC_APBRSTR1_LPUART2RST_Msk
5261 #define RCC_APBRSTR1_SPI2RST_Pos       (14U)
5262 #define RCC_APBRSTR1_SPI2RST_Msk       (0x1UL << RCC_APBRSTR1_SPI2RST_Pos)     /*!< 0x00004000 */
5263 #define RCC_APBRSTR1_SPI2RST           RCC_APBRSTR1_SPI2RST_Msk
5264 #define RCC_APBRSTR1_USART2RST_Pos     (17U)
5265 #define RCC_APBRSTR1_USART2RST_Msk     (0x1UL << RCC_APBRSTR1_USART2RST_Pos)   /*!< 0x00020000 */
5266 #define RCC_APBRSTR1_USART2RST         RCC_APBRSTR1_USART2RST_Msk
5267 #define RCC_APBRSTR1_USART3RST_Pos     (18U)
5268 #define RCC_APBRSTR1_USART3RST_Msk     (0x1UL << RCC_APBRSTR1_USART3RST_Pos)   /*!< 0x00040000 */
5269 #define RCC_APBRSTR1_USART3RST         RCC_APBRSTR1_USART3RST_Msk
5270 #define RCC_APBRSTR1_USART4RST_Pos     (19U)
5271 #define RCC_APBRSTR1_USART4RST_Msk     (0x1UL << RCC_APBRSTR1_USART4RST_Pos)   /*!< 0x00080000 */
5272 #define RCC_APBRSTR1_USART4RST         RCC_APBRSTR1_USART4RST_Msk
5273 #define RCC_APBRSTR1_LPUART1RST_Pos    (20U)
5274 #define RCC_APBRSTR1_LPUART1RST_Msk    (0x1UL << RCC_APBRSTR1_LPUART1RST_Pos)  /*!< 0x00010000 */
5275 #define RCC_APBRSTR1_LPUART1RST        RCC_APBRSTR1_LPUART1RST_Msk
5276 #define RCC_APBRSTR1_I2C1RST_Pos       (21U)
5277 #define RCC_APBRSTR1_I2C1RST_Msk       (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)     /*!< 0x00200000 */
5278 #define RCC_APBRSTR1_I2C1RST           RCC_APBRSTR1_I2C1RST_Msk
5279 #define RCC_APBRSTR1_I2C2RST_Pos       (22U)
5280 #define RCC_APBRSTR1_I2C2RST_Msk       (0x1UL << RCC_APBRSTR1_I2C2RST_Pos)     /*!< 0x00400000 */
5281 #define RCC_APBRSTR1_I2C2RST           RCC_APBRSTR1_I2C2RST_Msk
5282 #define RCC_APBRSTR1_I2C3RST_Pos       (23U)
5283 #define RCC_APBRSTR1_I2C3RST_Msk       (0x1UL << RCC_APBRSTR1_I2C3RST_Pos)     /*!< 0x00800000 */
5284 #define RCC_APBRSTR1_I2C3RST           RCC_APBRSTR1_I2C3RST_Msk
5285 #define RCC_APBRSTR1_OPAMPRST_Pos      (24U)
5286 #define RCC_APBRSTR1_OPAMPRST_Msk      (0x1UL << RCC_APBRSTR1_OPAMPRST_Pos)    /*!< 0x01000000 */
5287 #define RCC_APBRSTR1_OPAMPRST          RCC_APBRSTR1_OPAMPRST_Msk
5288 #define RCC_APBRSTR1_PWRRST_Pos        (28U)
5289 #define RCC_APBRSTR1_PWRRST_Msk        (0x1UL << RCC_APBRSTR1_PWRRST_Pos)      /*!< 0x10000000 */
5290 #define RCC_APBRSTR1_PWRRST            RCC_APBRSTR1_PWRRST_Msk
5291 #define RCC_APBRSTR1_DAC1RST_Pos       (29U)
5292 #define RCC_APBRSTR1_DAC1RST_Msk       (0x1UL << RCC_APBRSTR1_DAC1RST_Pos)     /*!< 0x20000000 */
5293 #define RCC_APBRSTR1_DAC1RST           RCC_APBRSTR1_DAC1RST_Msk
5294 #define RCC_APBRSTR1_LPTIM2RST_Pos     (30U)
5295 #define RCC_APBRSTR1_LPTIM2RST_Msk     (0x1UL << RCC_APBRSTR1_LPTIM2RST_Pos)   /*!< 0x40000000 */
5296 #define RCC_APBRSTR1_LPTIM2RST         RCC_APBRSTR1_LPTIM2RST_Msk
5297 #define RCC_APBRSTR1_LPTIM1RST_Pos     (31U)
5298 #define RCC_APBRSTR1_LPTIM1RST_Msk     (0x1UL << RCC_APBRSTR1_LPTIM1RST_Pos)   /*!< 0x80000000 */
5299 #define RCC_APBRSTR1_LPTIM1RST         RCC_APBRSTR1_LPTIM1RST_Msk
5300 
5301 /********************  Bit definition for RCC_APB2RSTR register  **************/
5302 #define RCC_APBRSTR2_SYSCFGRST_Pos     (0U)
5303 #define RCC_APBRSTR2_SYSCFGRST_Msk     (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)   /*!< 0x00000001 */
5304 #define RCC_APBRSTR2_SYSCFGRST         RCC_APBRSTR2_SYSCFGRST_Msk
5305 #define RCC_APBRSTR2_TIM1RST_Pos       (11U)
5306 #define RCC_APBRSTR2_TIM1RST_Msk       (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)     /*!< 0x00000800 */
5307 #define RCC_APBRSTR2_TIM1RST           RCC_APBRSTR2_TIM1RST_Msk
5308 #define RCC_APBRSTR2_SPI1RST_Pos       (12U)
5309 #define RCC_APBRSTR2_SPI1RST_Msk       (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)     /*!< 0x00001000 */
5310 #define RCC_APBRSTR2_SPI1RST           RCC_APBRSTR2_SPI1RST_Msk
5311 #define RCC_APBRSTR2_USART1RST_Pos     (14U)
5312 #define RCC_APBRSTR2_USART1RST_Msk     (0x1UL << RCC_APBRSTR2_USART1RST_Pos)   /*!< 0x00004000 */
5313 #define RCC_APBRSTR2_USART1RST         RCC_APBRSTR2_USART1RST_Msk
5314 #define RCC_APBRSTR2_TIM15RST_Pos      (16U)
5315 #define RCC_APBRSTR2_TIM15RST_Msk      (0x1UL << RCC_APBRSTR2_TIM15RST_Pos)    /*!< 0x00010000 */
5316 #define RCC_APBRSTR2_TIM15RST          RCC_APBRSTR2_TIM15RST_Msk
5317 #define RCC_APBRSTR2_TIM16RST_Pos      (17U)
5318 #define RCC_APBRSTR2_TIM16RST_Msk      (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)    /*!< 0x00020000 */
5319 #define RCC_APBRSTR2_TIM16RST          RCC_APBRSTR2_TIM16RST_Msk
5320 #define RCC_APBRSTR2_ADCRST_Pos        (20U)
5321 #define RCC_APBRSTR2_ADCRST_Msk        (0x1UL << RCC_APBRSTR2_ADCRST_Pos)      /*!< 0x00100000 */
5322 #define RCC_APBRSTR2_ADCRST            RCC_APBRSTR2_ADCRST_Msk
5323 
5324 /********************  Bit definition for RCC_AHBENR register  ****************/
5325 #define RCC_AHBENR_DMA1EN_Pos          (0U)
5326 #define RCC_AHBENR_DMA1EN_Msk          (0x1UL << RCC_AHBENR_DMA1EN_Pos)        /*!< 0x00000001 */
5327 #define RCC_AHBENR_DMA1EN              RCC_AHBENR_DMA1EN_Msk
5328 #define RCC_AHBENR_FLASHEN_Pos         (8U)
5329 #define RCC_AHBENR_FLASHEN_Msk         (0x1UL << RCC_AHBENR_FLASHEN_Pos)       /*!< 0x00000100 */
5330 #define RCC_AHBENR_FLASHEN             RCC_AHBENR_FLASHEN_Msk
5331 #define RCC_AHBENR_CRCEN_Pos           (12U)
5332 #define RCC_AHBENR_CRCEN_Msk           (0x1UL << RCC_AHBENR_CRCEN_Pos)         /*!< 0x00001000 */
5333 #define RCC_AHBENR_CRCEN               RCC_AHBENR_CRCEN_Msk
5334 #define RCC_AHBENR_RNGEN_Pos           (18U)
5335 #define RCC_AHBENR_RNGEN_Msk           (0x1UL << RCC_AHBENR_RNGEN_Pos)         /*!< 0x00040000 */
5336 #define RCC_AHBENR_RNGEN               RCC_AHBENR_RNGEN_Msk
5337 #define RCC_AHBENR_TSCEN_Pos           (24U)
5338 #define RCC_AHBENR_TSCEN_Msk           (0x1UL << RCC_AHBENR_TSCEN_Pos)         /*!< 0x01000000 */
5339 #define RCC_AHBENR_TSCEN               RCC_AHBENR_TSCEN_Msk
5340 
5341 /********************  Bit definition for RCC_IOPENR register  ****************/
5342 #define RCC_IOPENR_GPIOAEN_Pos         (0U)
5343 #define RCC_IOPENR_GPIOAEN_Msk         (0x1UL << RCC_IOPENR_GPIOAEN_Pos)       /*!< 0x00000001 */
5344 #define RCC_IOPENR_GPIOAEN             RCC_IOPENR_GPIOAEN_Msk
5345 #define RCC_IOPENR_GPIOBEN_Pos         (1U)
5346 #define RCC_IOPENR_GPIOBEN_Msk         (0x1UL << RCC_IOPENR_GPIOBEN_Pos)       /*!< 0x00000002 */
5347 #define RCC_IOPENR_GPIOBEN             RCC_IOPENR_GPIOBEN_Msk
5348 #define RCC_IOPENR_GPIOCEN_Pos         (2U)
5349 #define RCC_IOPENR_GPIOCEN_Msk         (0x1UL << RCC_IOPENR_GPIOCEN_Pos)       /*!< 0x00000004 */
5350 #define RCC_IOPENR_GPIOCEN             RCC_IOPENR_GPIOCEN_Msk
5351 #define RCC_IOPENR_GPIODEN_Pos         (3U)
5352 #define RCC_IOPENR_GPIODEN_Msk         (0x1UL << RCC_IOPENR_GPIODEN_Pos)       /*!< 0x00000008 */
5353 #define RCC_IOPENR_GPIODEN             RCC_IOPENR_GPIODEN_Msk
5354 #define RCC_IOPENR_GPIOFEN_Pos         (5U)
5355 #define RCC_IOPENR_GPIOFEN_Msk         (0x1UL << RCC_IOPENR_GPIOFEN_Pos)       /*!< 0x00000020 */
5356 #define RCC_IOPENR_GPIOFEN             RCC_IOPENR_GPIOFEN_Msk
5357 
5358 /********************  Bit definition for RCC_DBGCFGR register  ****************/
5359 #define RCC_DBGCFGR_DBGEN_Pos          (0U)
5360 #define RCC_DBGCFGR_DBGEN_Msk          (0x1UL << RCC_DBGCFGR_DBGEN_Pos)        /*!< 0x00000001 */
5361 #define RCC_DBGCFGR_DBGEN              RCC_DBGCFGR_DBGEN_Msk
5362 #define RCC_DBGCFGR_DBGRST_Pos         (1U)
5363 #define RCC_DBGCFGR_DBGRST_Msk         (0x1UL << RCC_DBGCFGR_DBGRST_Pos)       /*!< 0x00000002 */
5364 #define RCC_DBGCFGR_DBGRST             RCC_DBGCFGR_DBGRST_Msk
5365 
5366 /********************  Bit definition for RCC_APB1ENR register  ***************/
5367 #define RCC_APBENR1_TIM2EN_Pos         (0U)
5368 #define RCC_APBENR1_TIM2EN_Msk         (0x1UL << RCC_APBENR1_TIM2EN_Pos)       /*!< 0x00000001 */
5369 #define RCC_APBENR1_TIM2EN             RCC_APBENR1_TIM2EN_Msk
5370 #define RCC_APBENR1_TIM3EN_Pos         (1U)
5371 #define RCC_APBENR1_TIM3EN_Msk         (0x1UL << RCC_APBENR1_TIM3EN_Pos)       /*!< 0x00000002 */
5372 #define RCC_APBENR1_TIM3EN             RCC_APBENR1_TIM3EN_Msk
5373 #define RCC_APBENR1_TIM6EN_Pos         (4U)
5374 #define RCC_APBENR1_TIM6EN_Msk         (0x1UL << RCC_APBENR1_TIM6EN_Pos)       /*!< 0x00000010 */
5375 #define RCC_APBENR1_TIM6EN             RCC_APBENR1_TIM6EN_Msk
5376 #define RCC_APBENR1_TIM7EN_Pos         (5U)
5377 #define RCC_APBENR1_TIM7EN_Msk         (0x1UL << RCC_APBENR1_TIM7EN_Pos)       /*!< 0x00000020 */
5378 #define RCC_APBENR1_TIM7EN             RCC_APBENR1_TIM7EN_Msk
5379 #define RCC_APBENR1_LPUART2EN_Pos      (7U)
5380 #define RCC_APBENR1_LPUART2EN_Msk      (0x1UL << RCC_APBENR1_LPUART2EN_Pos)    /*!< 0x00000080 */
5381 #define RCC_APBENR1_LPUART2EN          RCC_APBENR1_LPUART2EN_Msk
5382 #define RCC_APBENR1_RTCAPBEN_Pos       (10U)
5383 #define RCC_APBENR1_RTCAPBEN_Msk       (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)     /*!< 0x00000400 */
5384 #define RCC_APBENR1_RTCAPBEN           RCC_APBENR1_RTCAPBEN_Msk
5385 #define RCC_APBENR1_WWDGEN_Pos         (11U)
5386 #define RCC_APBENR1_WWDGEN_Msk         (0x1UL << RCC_APBENR1_WWDGEN_Pos)       /*!< 0x00000800 */
5387 #define RCC_APBENR1_WWDGEN             RCC_APBENR1_WWDGEN_Msk
5388 #define RCC_APBENR1_SPI2EN_Pos         (14U)
5389 #define RCC_APBENR1_SPI2EN_Msk         (0x1UL << RCC_APBENR1_SPI2EN_Pos)       /*!< 0x00004000 */
5390 #define RCC_APBENR1_SPI2EN             RCC_APBENR1_SPI2EN_Msk
5391 #define RCC_APBENR1_USART2EN_Pos       (17U)
5392 #define RCC_APBENR1_USART2EN_Msk       (0x1UL << RCC_APBENR1_USART2EN_Pos)     /*!< 0x00020000 */
5393 #define RCC_APBENR1_USART2EN           RCC_APBENR1_USART2EN_Msk
5394 #define RCC_APBENR1_USART3EN_Pos       (18U)
5395 #define RCC_APBENR1_USART3EN_Msk       (0x1UL << RCC_APBENR1_USART3EN_Pos)     /*!< 0x00040000 */
5396 #define RCC_APBENR1_USART3EN           RCC_APBENR1_USART3EN_Msk
5397 #define RCC_APBENR1_USART4EN_Pos       (19U)
5398 #define RCC_APBENR1_USART4EN_Msk       (0x1UL << RCC_APBENR1_USART4EN_Pos)     /*!< 0x00080000 */
5399 #define RCC_APBENR1_USART4EN           RCC_APBENR1_USART4EN_Msk
5400 #define RCC_APBENR1_LPUART1EN_Pos      (20U)
5401 #define RCC_APBENR1_LPUART1EN_Msk      (0x1UL << RCC_APBENR1_LPUART1EN_Pos)    /*!< 0x00010000 */
5402 #define RCC_APBENR1_LPUART1EN          RCC_APBENR1_LPUART1EN_Msk
5403 #define RCC_APBENR1_I2C1EN_Pos         (21U)
5404 #define RCC_APBENR1_I2C1EN_Msk         (0x1UL << RCC_APBENR1_I2C1EN_Pos)       /*!< 0x00200000 */
5405 #define RCC_APBENR1_I2C1EN             RCC_APBENR1_I2C1EN_Msk
5406 #define RCC_APBENR1_I2C2EN_Pos         (22U)
5407 #define RCC_APBENR1_I2C2EN_Msk         (0x1UL << RCC_APBENR1_I2C2EN_Pos)       /*!< 0x00400000 */
5408 #define RCC_APBENR1_I2C2EN             RCC_APBENR1_I2C2EN_Msk
5409 #define RCC_APBENR1_I2C3EN_Pos         (23U)
5410 #define RCC_APBENR1_I2C3EN_Msk         (0x1UL << RCC_APBENR1_I2C3EN_Pos)       /*!< 0x00800000 */
5411 #define RCC_APBENR1_I2C3EN             RCC_APBENR1_I2C3EN_Msk
5412 #define RCC_APBENR1_OPAMPEN_Pos        (24U)
5413 #define RCC_APBENR1_OPAMPEN_Msk        (0x1UL << RCC_APBENR1_OPAMPEN_Pos)      /*!< 0x01000000 */
5414 #define RCC_APBENR1_OPAMPEN            RCC_APBENR1_OPAMPEN_Msk
5415 #define RCC_APBENR1_PWREN_Pos          (28U)
5416 #define RCC_APBENR1_PWREN_Msk          (0x1UL << RCC_APBENR1_PWREN_Pos)        /*!< 0x10000000 */
5417 #define RCC_APBENR1_PWREN              RCC_APBENR1_PWREN_Msk
5418 #define RCC_APBENR1_DAC1EN_Pos         (29U)
5419 #define RCC_APBENR1_DAC1EN_Msk         (0x1UL << RCC_APBENR1_DAC1EN_Pos)       /*!< 0x20000000 */
5420 #define RCC_APBENR1_DAC1EN             RCC_APBENR1_DAC1EN_Msk
5421 #define RCC_APBENR1_LPTIM2EN_Pos       (30U)
5422 #define RCC_APBENR1_LPTIM2EN_Msk       (0x1UL << RCC_APBENR1_LPTIM2EN_Pos)     /*!< 0x40000000 */
5423 #define RCC_APBENR1_LPTIM2EN           RCC_APBENR1_LPTIM2EN_Msk
5424 #define RCC_APBENR1_LPTIM1EN_Pos       (31U)
5425 #define RCC_APBENR1_LPTIM1EN_Msk       (0x1UL << RCC_APBENR1_LPTIM1EN_Pos)     /*!< 0x80000000 */
5426 #define RCC_APBENR1_LPTIM1EN           RCC_APBENR1_LPTIM1EN_Msk
5427 
5428 /********************  Bit definition for RCC_APB2ENR register  **************/
5429 #define RCC_APBENR2_SYSCFGEN_Pos       (0U)
5430 #define RCC_APBENR2_SYSCFGEN_Msk       (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)     /*!< 0x00000001 */
5431 #define RCC_APBENR2_SYSCFGEN           RCC_APBENR2_SYSCFGEN_Msk
5432 #define RCC_APBENR2_TIM1EN_Pos         (11U)
5433 #define RCC_APBENR2_TIM1EN_Msk         (0x1UL << RCC_APBENR2_TIM1EN_Pos)       /*!< 0x00000800 */
5434 #define RCC_APBENR2_TIM1EN             RCC_APBENR2_TIM1EN_Msk
5435 #define RCC_APBENR2_SPI1EN_Pos         (12U)
5436 #define RCC_APBENR2_SPI1EN_Msk         (0x1UL << RCC_APBENR2_SPI1EN_Pos)       /*!< 0x00001000 */
5437 #define RCC_APBENR2_SPI1EN             RCC_APBENR2_SPI1EN_Msk
5438 #define RCC_APBENR2_USART1EN_Pos       (14U)
5439 #define RCC_APBENR2_USART1EN_Msk       (0x1UL << RCC_APBENR2_USART1EN_Pos)     /*!< 0x00004000 */
5440 #define RCC_APBENR2_USART1EN           RCC_APBENR2_USART1EN_Msk
5441 #define RCC_APBENR2_TIM15EN_Pos        (16U)
5442 #define RCC_APBENR2_TIM15EN_Msk        (0x1UL << RCC_APBENR2_TIM15EN_Pos)      /*!< 0x00008000 */
5443 #define RCC_APBENR2_TIM15EN            RCC_APBENR2_TIM15EN_Msk
5444 #define RCC_APBENR2_TIM16EN_Pos        (17U)
5445 #define RCC_APBENR2_TIM16EN_Msk        (0x1UL << RCC_APBENR2_TIM16EN_Pos)      /*!< 0x00020000 */
5446 #define RCC_APBENR2_TIM16EN            RCC_APBENR2_TIM16EN_Msk
5447 #define RCC_APBENR2_ADCEN_Pos          (20U)
5448 #define RCC_APBENR2_ADCEN_Msk          (0x1UL << RCC_APBENR2_ADCEN_Pos)        /*!< 0x00100000 */
5449 #define RCC_APBENR2_ADCEN              RCC_APBENR2_ADCEN_Msk
5450 
5451 /********************  Bit definition for RCC_AHBSMENR register  *************/
5452 #define RCC_AHBSMENR_DMA1SMEN_Pos      (0U)
5453 #define RCC_AHBSMENR_DMA1SMEN_Msk      (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)    /*!< 0x00000001 */
5454 #define RCC_AHBSMENR_DMA1SMEN          RCC_AHBSMENR_DMA1SMEN_Msk
5455 #define RCC_AHBSMENR_FLASHSMEN_Pos     (8U)
5456 #define RCC_AHBSMENR_FLASHSMEN_Msk     (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)   /*!< 0x00000100 */
5457 #define RCC_AHBSMENR_FLASHSMEN         RCC_AHBSMENR_FLASHSMEN_Msk
5458 #define RCC_AHBSMENR_SRAM1SMEN_Pos     (9U)
5459 #define RCC_AHBSMENR_SRAM1SMEN_Msk     (0x1UL << RCC_AHBSMENR_SRAM1SMEN_Pos)   /*!< 0x00000200 */
5460 #define RCC_AHBSMENR_SRAM1SMEN         RCC_AHBSMENR_SRAM1SMEN_Msk
5461 #define RCC_AHBSMENR_CRCSMEN_Pos       (12U)
5462 #define RCC_AHBSMENR_CRCSMEN_Msk       (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)     /*!< 0x00001000 */
5463 #define RCC_AHBSMENR_CRCSMEN           RCC_AHBSMENR_CRCSMEN_Msk
5464 #define RCC_AHBSMENR_RNGSMEN_Pos       (18U)
5465 #define RCC_AHBSMENR_RNGSMEN_Msk       (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)     /*!< 0x00040000 */
5466 #define RCC_AHBSMENR_RNGSMEN           RCC_AHBSMENR_RNGSMEN_Msk
5467 #define RCC_AHBSMENR_TSCSMEN_Pos       (24U)
5468 #define RCC_AHBSMENR_TSCSMEN_Msk       (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)     /*!< 0x01000000 */
5469 #define RCC_AHBSMENR_TSCSMEN           RCC_AHBSMENR_TSCSMEN_Msk
5470 
5471 /********************  Bit definition for RCC_IOPSMENR register  *************/
5472 #define RCC_IOPSMENR_GPIOASMEN_Pos     (0U)
5473 #define RCC_IOPSMENR_GPIOASMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)   /*!< 0x00000001 */
5474 #define RCC_IOPSMENR_GPIOASMEN         RCC_IOPSMENR_GPIOASMEN_Msk
5475 #define RCC_IOPSMENR_GPIOBSMEN_Pos     (1U)
5476 #define RCC_IOPSMENR_GPIOBSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)   /*!< 0x00000002 */
5477 #define RCC_IOPSMENR_GPIOBSMEN         RCC_IOPSMENR_GPIOBSMEN_Msk
5478 #define RCC_IOPSMENR_GPIOCSMEN_Pos     (2U)
5479 #define RCC_IOPSMENR_GPIOCSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)   /*!< 0x00000004 */
5480 #define RCC_IOPSMENR_GPIOCSMEN         RCC_IOPSMENR_GPIOCSMEN_Msk
5481 #define RCC_IOPSMENR_GPIODSMEN_Pos     (3U)
5482 #define RCC_IOPSMENR_GPIODSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)   /*!< 0x00000008 */
5483 #define RCC_IOPSMENR_GPIODSMEN         RCC_IOPSMENR_GPIODSMEN_Msk
5484 #define RCC_IOPSMENR_GPIOFSMEN_Pos     (5U)
5485 #define RCC_IOPSMENR_GPIOFSMEN_Msk     (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)   /*!< 0x00000020 */
5486 #define RCC_IOPSMENR_GPIOFSMEN         RCC_IOPSMENR_GPIOFSMEN_Msk
5487 
5488 /********************  Bit definition for RCC_APB1SMENR register  *************/
5489 #define RCC_APBSMENR1_TIM2SMEN_Pos     (0U)
5490 #define RCC_APBSMENR1_TIM2SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM2SMEN_Pos)   /*!< 0x00000001 */
5491 #define RCC_APBSMENR1_TIM2SMEN         RCC_APBSMENR1_TIM2SMEN_Msk
5492 #define RCC_APBSMENR1_TIM3SMEN_Pos     (1U)
5493 #define RCC_APBSMENR1_TIM3SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)   /*!< 0x00000002 */
5494 #define RCC_APBSMENR1_TIM3SMEN         RCC_APBSMENR1_TIM3SMEN_Msk
5495 #define RCC_APBSMENR1_TIM6SMEN_Pos     (4U)
5496 #define RCC_APBSMENR1_TIM6SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM6SMEN_Pos)   /*!< 0x00000010 */
5497 #define RCC_APBSMENR1_TIM6SMEN         RCC_APBSMENR1_TIM6SMEN_Msk
5498 #define RCC_APBSMENR1_TIM7SMEN_Pos     (5U)
5499 #define RCC_APBSMENR1_TIM7SMEN_Msk     (0x1UL << RCC_APBSMENR1_TIM7SMEN_Pos)   /*!< 0x00000020 */
5500 #define RCC_APBSMENR1_TIM7SMEN         RCC_APBSMENR1_TIM7SMEN_Msk
5501 #define RCC_APBSMENR1_LPUART2SMEN_Pos  (7U)
5502 #define RCC_APBSMENR1_LPUART2SMEN_Msk  (0x1UL << RCC_APBSMENR1_LPUART2SMEN_Pos)/*!< 0x00000080 */
5503 #define RCC_APBSMENR1_LPUART2SMEN      RCC_APBSMENR1_LPUART2SMEN_Msk
5504 #define RCC_APBSMENR1_RTCAPBSMEN_Pos   (10U)
5505 #define RCC_APBSMENR1_RTCAPBSMEN_Msk   (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
5506 #define RCC_APBSMENR1_RTCAPBSMEN       RCC_APBSMENR1_RTCAPBSMEN_Msk
5507 #define RCC_APBSMENR1_WWDGSMEN_Pos     (11U)
5508 #define RCC_APBSMENR1_WWDGSMEN_Msk     (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)   /*!< 0x00000800 */
5509 #define RCC_APBSMENR1_WWDGSMEN         RCC_APBSMENR1_WWDGSMEN_Msk
5510 #define RCC_APBSMENR1_SPI2SMEN_Pos     (14U)
5511 #define RCC_APBSMENR1_SPI2SMEN_Msk     (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos)   /*!< 0x00004000 */
5512 #define RCC_APBSMENR1_SPI2SMEN         RCC_APBSMENR1_SPI2SMEN_Msk
5513 #define RCC_APBSMENR1_USART2SMEN_Pos   (17U)
5514 #define RCC_APBSMENR1_USART2SMEN_Msk   (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
5515 #define RCC_APBSMENR1_USART2SMEN       RCC_APBSMENR1_USART2SMEN_Msk
5516 #define RCC_APBSMENR1_USART3SMEN_Pos   (18U)
5517 #define RCC_APBSMENR1_USART3SMEN_Msk   (0x1UL << RCC_APBSMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
5518 #define RCC_APBSMENR1_USART3SMEN       RCC_APBSMENR1_USART3SMEN_Msk
5519 #define RCC_APBSMENR1_USART4SMEN_Pos   (19U)
5520 #define RCC_APBSMENR1_USART4SMEN_Msk   (0x1UL << RCC_APBSMENR1_USART4SMEN_Pos) /*!< 0x00080000 */
5521 #define RCC_APBSMENR1_USART4SMEN       RCC_APBSMENR1_USART4SMEN_Msk
5522 #define RCC_APBSMENR1_LPUART1SMEN_Pos  (20U)
5523 #define RCC_APBSMENR1_LPUART1SMEN_Msk  (0x1UL << RCC_APBSMENR1_LPUART1SMEN_Pos)/*!< 0x00100000 */
5524 #define RCC_APBSMENR1_LPUART1SMEN      RCC_APBSMENR1_LPUART1SMEN_Msk
5525 #define RCC_APBSMENR1_I2C1SMEN_Pos     (21U)
5526 #define RCC_APBSMENR1_I2C1SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)   /*!< 0x00200000 */
5527 #define RCC_APBSMENR1_I2C1SMEN         RCC_APBSMENR1_I2C1SMEN_Msk
5528 #define RCC_APBSMENR1_I2C2SMEN_Pos     (22U)
5529 #define RCC_APBSMENR1_I2C2SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos)   /*!< 0x00400000 */
5530 #define RCC_APBSMENR1_I2C2SMEN         RCC_APBSMENR1_I2C2SMEN_Msk
5531 #define RCC_APBSMENR1_I2C3SMEN_Pos     (23U)
5532 #define RCC_APBSMENR1_I2C3SMEN_Msk     (0x1UL << RCC_APBSMENR1_I2C3SMEN_Pos)   /*!< 0x00800000 */
5533 #define RCC_APBSMENR1_I2C3SMEN         RCC_APBSMENR1_I2C3SMEN_Msk
5534 #define RCC_APBSMENR1_OPAMPSMEN_Pos    (24U)
5535 #define RCC_APBSMENR1_OPAMPSMEN_Msk    (0x1UL << RCC_APBSMENR1_OPAMPSMEN_Pos)  /*!< 0x01000000 */
5536 #define RCC_APBSMENR1_OPAMPSMEN        RCC_APBSMENR1_OPAMPSMEN_Msk
5537 #define RCC_APBSMENR1_PWRSMEN_Pos      (28U)
5538 #define RCC_APBSMENR1_PWRSMEN_Msk      (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)    /*!< 0x10000000 */
5539 #define RCC_APBSMENR1_PWRSMEN          RCC_APBSMENR1_PWRSMEN_Msk
5540 #define RCC_APBSMENR1_DAC1SMEN_Pos     (29U)
5541 #define RCC_APBSMENR1_DAC1SMEN_Msk     (0x1UL << RCC_APBSMENR1_DAC1SMEN_Pos)   /*!< 0x20000000 */
5542 #define RCC_APBSMENR1_DAC1SMEN         RCC_APBSMENR1_DAC1SMEN_Msk
5543 #define RCC_APBSMENR1_LPTIM2SMEN_Pos   (30U)
5544 #define RCC_APBSMENR1_LPTIM2SMEN_Msk   (0x1UL << RCC_APBSMENR1_LPTIM2SMEN_Pos) /*!< 0x40000000 */
5545 #define RCC_APBSMENR1_LPTIM2SMEN       RCC_APBSMENR1_LPTIM2SMEN_Msk
5546 #define RCC_APBSMENR1_LPTIM1SMEN_Pos   (31U)
5547 #define RCC_APBSMENR1_LPTIM1SMEN_Msk   (0x1UL << RCC_APBSMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
5548 #define RCC_APBSMENR1_LPTIM1SMEN       RCC_APBSMENR1_LPTIM1SMEN_Msk
5549 
5550 /********************  Bit definition for RCC_APBSMENR2 register  *************/
5551 #define RCC_APBSMENR2_SYSCFGSMEN_Pos   (0U)
5552 #define RCC_APBSMENR2_SYSCFGSMEN_Msk   (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
5553 #define RCC_APBSMENR2_SYSCFGSMEN       RCC_APBSMENR2_SYSCFGSMEN_Msk
5554 #define RCC_APBSMENR2_TIM1SMEN_Pos     (11U)
5555 #define RCC_APBSMENR2_TIM1SMEN_Msk     (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)   /*!< 0x00000800 */
5556 #define RCC_APBSMENR2_TIM1SMEN         RCC_APBSMENR2_TIM1SMEN_Msk
5557 #define RCC_APBSMENR2_SPI1SMEN_Pos     (12U)
5558 #define RCC_APBSMENR2_SPI1SMEN_Msk     (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)   /*!< 0x00001000 */
5559 #define RCC_APBSMENR2_SPI1SMEN         RCC_APBSMENR2_SPI1SMEN_Msk
5560 #define RCC_APBSMENR2_USART1SMEN_Pos   (14U)
5561 #define RCC_APBSMENR2_USART1SMEN_Msk   (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
5562 #define RCC_APBSMENR2_USART1SMEN       RCC_APBSMENR2_USART1SMEN_Msk
5563 #define RCC_APBSMENR2_TIM15SMEN_Pos    (16U)
5564 #define RCC_APBSMENR2_TIM15SMEN_Msk    (0x1UL << RCC_APBSMENR2_TIM15SMEN_Pos)  /*!< 0x00010000 */
5565 #define RCC_APBSMENR2_TIM15SMEN        RCC_APBSMENR2_TIM15SMEN_Msk
5566 #define RCC_APBSMENR2_TIM16SMEN_Pos    (17U)
5567 #define RCC_APBSMENR2_TIM16SMEN_Msk    (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos)  /*!< 0x00020000 */
5568 #define RCC_APBSMENR2_TIM16SMEN        RCC_APBSMENR2_TIM16SMEN_Msk
5569 #define RCC_APBSMENR2_ADCSMEN_Pos      (20U)
5570 #define RCC_APBSMENR2_ADCSMEN_Msk      (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)    /*!< 0x00100000 */
5571 #define RCC_APBSMENR2_ADCSMEN          RCC_APBSMENR2_ADCSMEN_Msk
5572 
5573 /********************  Bit definition for RCC_CCIPR register  ******************/
5574 #define RCC_CCIPR_USART1SEL_Pos        (0U)
5575 #define RCC_CCIPR_USART1SEL_Msk        (0x3UL << RCC_CCIPR_USART1SEL_Pos)      /*!< 0x00000003 */
5576 #define RCC_CCIPR_USART1SEL            RCC_CCIPR_USART1SEL_Msk
5577 #define RCC_CCIPR_USART1SEL_0          (0x1UL << RCC_CCIPR_USART1SEL_Pos)      /*!< 0x00000001 */
5578 #define RCC_CCIPR_USART1SEL_1          (0x2UL << RCC_CCIPR_USART1SEL_Pos)      /*!< 0x00000002 */
5579 #define RCC_CCIPR_USART2SEL_Pos        (2U)
5580 #define RCC_CCIPR_USART2SEL_Msk        (0x3UL << RCC_CCIPR_USART2SEL_Pos)      /*!< 0x0000000C */
5581 #define RCC_CCIPR_USART2SEL            RCC_CCIPR_USART2SEL_Msk
5582 #define RCC_CCIPR_USART2SEL_0          (0x1UL << RCC_CCIPR_USART2SEL_Pos)      /*!< 0x00000004 */
5583 #define RCC_CCIPR_USART2SEL_1          (0x2UL << RCC_CCIPR_USART2SEL_Pos)      /*!< 0x00000008 */
5584 #define RCC_CCIPR_LPUART2SEL_Pos       (8U)
5585 #define RCC_CCIPR_LPUART2SEL_Msk       (0x3UL << RCC_CCIPR_LPUART2SEL_Pos)     /*!< 0x00000300 */
5586 #define RCC_CCIPR_LPUART2SEL           RCC_CCIPR_LPUART2SEL_Msk
5587 #define RCC_CCIPR_LPUART2SEL_0         (0x1UL << RCC_CCIPR_LPUART2SEL_Pos)     /*!< 0x00000100 */
5588 #define RCC_CCIPR_LPUART2SEL_1         (0x2UL << RCC_CCIPR_LPUART2SEL_Pos)     /*!< 0x00000200 */
5589 #define RCC_CCIPR_LPUART1SEL_Pos       (10U)
5590 #define RCC_CCIPR_LPUART1SEL_Msk       (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)     /*!< 0x00000C00 */
5591 #define RCC_CCIPR_LPUART1SEL           RCC_CCIPR_LPUART1SEL_Msk
5592 #define RCC_CCIPR_LPUART1SEL_0         (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)     /*!< 0x00000400 */
5593 #define RCC_CCIPR_LPUART1SEL_1         (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)     /*!< 0x00000800 */
5594 #define RCC_CCIPR_I2C1SEL_Pos          (12U)
5595 #define RCC_CCIPR_I2C1SEL_Msk          (0x3UL << RCC_CCIPR_I2C1SEL_Pos)        /*!< 0x00003000 */
5596 #define RCC_CCIPR_I2C1SEL              RCC_CCIPR_I2C1SEL_Msk
5597 #define RCC_CCIPR_I2C1SEL_0            (0x1UL << RCC_CCIPR_I2C1SEL_Pos)        /*!< 0x00001000 */
5598 #define RCC_CCIPR_I2C1SEL_1            (0x2UL << RCC_CCIPR_I2C1SEL_Pos)        /*!< 0x00002000 */
5599 #define RCC_CCIPR_I2C3SEL_Pos          (16U)
5600 #define RCC_CCIPR_I2C3SEL_Msk          (0x3UL << RCC_CCIPR_I2C3SEL_Pos)        /*!< 0x00030000 */
5601 #define RCC_CCIPR_I2C3SEL              RCC_CCIPR_I2C3SEL_Msk
5602 #define RCC_CCIPR_I2C3SEL_0            (0x1UL << RCC_CCIPR_I2C3SEL_Pos)        /*!< 0x00010000 */
5603 #define RCC_CCIPR_I2C3SEL_1            (0x2UL << RCC_CCIPR_I2C3SEL_Pos)        /*!< 0x00020000 */
5604 #define RCC_CCIPR_LPTIM1SEL_Pos        (18U)
5605 #define RCC_CCIPR_LPTIM1SEL_Msk        (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)      /*!< 0x000C0000 */
5606 #define RCC_CCIPR_LPTIM1SEL            RCC_CCIPR_LPTIM1SEL_Msk
5607 #define RCC_CCIPR_LPTIM1SEL_0          (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)      /*!< 0x00040000 */
5608 #define RCC_CCIPR_LPTIM1SEL_1          (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)      /*!< 0x00080000 */
5609 #define RCC_CCIPR_LPTIM2SEL_Pos        (20U)
5610 #define RCC_CCIPR_LPTIM2SEL_Msk        (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)      /*!< 0x00300000 */
5611 #define RCC_CCIPR_LPTIM2SEL            RCC_CCIPR_LPTIM2SEL_Msk
5612 #define RCC_CCIPR_LPTIM2SEL_0          (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)      /*!< 0x00100000 */
5613 #define RCC_CCIPR_LPTIM2SEL_1          (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)      /*!< 0x00200000 */
5614 #define RCC_CCIPR_TIM1SEL_Pos          (24U)
5615 #define RCC_CCIPR_TIM1SEL_Msk          (0x1UL << RCC_CCIPR_TIM1SEL_Pos)        /*!< 0x01000000 */
5616 #define RCC_CCIPR_TIM1SEL              RCC_CCIPR_TIM1SEL_Msk
5617 #define RCC_CCIPR_TIM15SEL_Pos         (25U)
5618 #define RCC_CCIPR_TIM15SEL_Msk         (0x1UL << RCC_CCIPR_TIM15SEL_Pos)       /*!< 0x02000000 */
5619 #define RCC_CCIPR_TIM15SEL             RCC_CCIPR_TIM15SEL_Msk
5620 #define RCC_CCIPR_CLK48SEL_Pos         (26U)
5621 #define RCC_CCIPR_CLK48SEL_Msk         (0x3UL << RCC_CCIPR_CLK48SEL_Pos)         /*!< 0x0C000000 */
5622 #define RCC_CCIPR_CLK48SEL             RCC_CCIPR_CLK48SEL_Msk
5623 #define RCC_CCIPR_CLK48SEL_0           (0x1UL << RCC_CCIPR_CLK48SEL_Pos)       /*!< 0x04000000 */
5624 #define RCC_CCIPR_CLK48SEL_1           (0x2UL << RCC_CCIPR_CLK48SEL_Pos)       /*!< 0x08000000 */
5625 #define RCC_CCIPR_ADCSEL_Pos           (28U)
5626 #define RCC_CCIPR_ADCSEL_Msk           (0x3UL << RCC_CCIPR_ADCSEL_Pos)         /*!< 0x30000000 */
5627 #define RCC_CCIPR_ADCSEL               RCC_CCIPR_ADCSEL_Msk
5628 #define RCC_CCIPR_ADCSEL_0             (0x1UL << RCC_CCIPR_ADCSEL_Pos)         /*!< 0x10000000 */
5629 #define RCC_CCIPR_ADCSEL_1             (0x2UL << RCC_CCIPR_ADCSEL_Pos)         /*!< 0x20000000 */
5630 
5631 /********************  Bit definition for RCC_BDCR register  ******************/
5632 #define RCC_BDCR_LSEON_Pos             (0U)
5633 #define RCC_BDCR_LSEON_Msk             (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
5634 #define RCC_BDCR_LSEON                 RCC_BDCR_LSEON_Msk
5635 #define RCC_BDCR_LSERDY_Pos            (1U)
5636 #define RCC_BDCR_LSERDY_Msk            (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
5637 #define RCC_BDCR_LSERDY                RCC_BDCR_LSERDY_Msk
5638 #define RCC_BDCR_LSEBYP_Pos            (2U)
5639 #define RCC_BDCR_LSEBYP_Msk            (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
5640 #define RCC_BDCR_LSEBYP                RCC_BDCR_LSEBYP_Msk
5641 #define RCC_BDCR_LSEDRV_Pos            (3U)
5642 #define RCC_BDCR_LSEDRV_Msk            (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
5643 #define RCC_BDCR_LSEDRV                RCC_BDCR_LSEDRV_Msk
5644 #define RCC_BDCR_LSEDRV_0              (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
5645 #define RCC_BDCR_LSEDRV_1              (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
5646 #define RCC_BDCR_LSECSSON_Pos          (5U)
5647 #define RCC_BDCR_LSECSSON_Msk          (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
5648 #define RCC_BDCR_LSECSSON              RCC_BDCR_LSECSSON_Msk
5649 #define RCC_BDCR_LSECSSD_Pos           (6U)
5650 #define RCC_BDCR_LSECSSD_Msk           (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
5651 #define RCC_BDCR_LSECSSD               RCC_BDCR_LSECSSD_Msk
5652 #define RCC_BDCR_LSESYSEN_Pos          (7U)
5653 #define RCC_BDCR_LSESYSEN_Msk          (0x1UL << RCC_BDCR_LSESYSEN_Pos)        /*!< 0x00000080 */
5654 #define RCC_BDCR_LSESYSEN              RCC_BDCR_LSESYSEN_Msk
5655 #define RCC_BDCR_RTCSEL_Pos            (8U)
5656 #define RCC_BDCR_RTCSEL_Msk            (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
5657 #define RCC_BDCR_RTCSEL                RCC_BDCR_RTCSEL_Msk
5658 #define RCC_BDCR_RTCSEL_0              (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
5659 #define RCC_BDCR_RTCSEL_1              (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
5660 #define RCC_BDCR_LSESYSRDY_Pos         (11U)
5661 #define RCC_BDCR_LSESYSRDY_Msk         (0x1UL << RCC_BDCR_LSESYSRDY_Pos)       /*!< 0x00000800 */
5662 #define RCC_BDCR_LSESYSRDY             RCC_BDCR_LSESYSRDY_Msk
5663 #define RCC_BDCR_RTCEN_Pos             (15U)
5664 #define RCC_BDCR_RTCEN_Msk             (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
5665 #define RCC_BDCR_RTCEN                 RCC_BDCR_RTCEN_Msk
5666 #define RCC_BDCR_BDRST_Pos             (16U)
5667 #define RCC_BDCR_BDRST_Msk             (0x1UL << RCC_BDCR_BDRST_Pos)           /*!< 0x00010000 */
5668 #define RCC_BDCR_BDRST                 RCC_BDCR_BDRST_Msk
5669 #define RCC_BDCR_LSCOEN_Pos            (24U)
5670 #define RCC_BDCR_LSCOEN_Msk            (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
5671 #define RCC_BDCR_LSCOEN                RCC_BDCR_LSCOEN_Msk
5672 #define RCC_BDCR_LSCOSEL_Pos           (25U)
5673 #define RCC_BDCR_LSCOSEL_Msk           (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
5674 #define RCC_BDCR_LSCOSEL               RCC_BDCR_LSCOSEL_Msk
5675 
5676 /********************  Bit definition for RCC_CSR register  *******************/
5677 #define RCC_CSR_LSION_Pos              (0U)
5678 #define RCC_CSR_LSION_Msk              (0x1UL << RCC_CSR_LSION_Pos)            /*!< 0x00000001 */
5679 #define RCC_CSR_LSION                  RCC_CSR_LSION_Msk
5680 #define RCC_CSR_LSIRDY_Pos             (1U)
5681 #define RCC_CSR_LSIRDY_Msk             (0x1UL << RCC_CSR_LSIRDY_Pos)           /*!< 0x00000002 */
5682 #define RCC_CSR_LSIRDY                 RCC_CSR_LSIRDY_Msk
5683 #define RCC_CSR_LSIPREDIV_Pos          (2U)
5684 #define RCC_CSR_LSIPREDIV_Msk          (0x1UL << RCC_CSR_LSIPREDIV_Pos)        /*!< 0x00000004 */
5685 #define RCC_CSR_LSIPREDIV              RCC_CSR_LSIPREDIV_Msk
5686 #define RCC_CSR_MSISTBYRG_Pos          (8U)
5687 #define RCC_CSR_MSISTBYRG_Msk          (0xFUL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000F00 */
5688 #define RCC_CSR_MSISTBYRG              RCC_CSR_MSISTBYRG_Msk
5689 #define RCC_CSR_MSISTBYRG_1            (0x4UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000400 */
5690 #define RCC_CSR_MSISTBYRG_2            (0x5UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000500 */
5691 #define RCC_CSR_MSISTBYRG_4            (0x6UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000600 */
5692 #define RCC_CSR_MSISTBYRG_8            (0x7UL << RCC_CSR_MSISTBYRG_Pos)        /*!< 0x00000700 */
5693 #define RCC_CSR_RMVF_Pos               (23U)
5694 #define RCC_CSR_RMVF_Msk               (0x1UL << RCC_CSR_RMVF_Pos)             /*!< 0x00800000 */
5695 #define RCC_CSR_RMVF                   RCC_CSR_RMVF_Msk
5696 #define RCC_CSR_OBLRSTF_Pos            (25U)
5697 #define RCC_CSR_OBLRSTF_Msk            (0x1UL << RCC_CSR_OBLRSTF_Pos)          /*!< 0x02000000 */
5698 #define RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF_Msk
5699 #define RCC_CSR_PINRSTF_Pos            (26U)
5700 #define RCC_CSR_PINRSTF_Msk            (0x1UL << RCC_CSR_PINRSTF_Pos)          /*!< 0x04000000 */
5701 #define RCC_CSR_PINRSTF                RCC_CSR_PINRSTF_Msk
5702 #define RCC_CSR_PWRRSTF_Pos            (27U)
5703 #define RCC_CSR_PWRRSTF_Msk            (0x1UL << RCC_CSR_PWRRSTF_Pos)          /*!< 0x08000000 */
5704 #define RCC_CSR_PWRRSTF                RCC_CSR_PWRRSTF_Msk
5705 #define RCC_CSR_SFTRSTF_Pos            (28U)
5706 #define RCC_CSR_SFTRSTF_Msk            (0x1UL << RCC_CSR_SFTRSTF_Pos)          /*!< 0x10000000 */
5707 #define RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF_Msk
5708 #define RCC_CSR_IWDGRSTF_Pos           (29U)
5709 #define RCC_CSR_IWDGRSTF_Msk           (0x1UL << RCC_CSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
5710 #define RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF_Msk
5711 #define RCC_CSR_WWDGRSTF_Pos           (30U)
5712 #define RCC_CSR_WWDGRSTF_Msk           (0x1UL << RCC_CSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
5713 #define RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF_Msk
5714 #define RCC_CSR_LPWRRSTF_Pos           (31U)
5715 #define RCC_CSR_LPWRRSTF_Msk           (0x1UL << RCC_CSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
5716 #define RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF_Msk
5717 /******************************************************************************/
5718 /*                                                                            */
5719 /*                                    RNG                                     */
5720 /*                                                                            */
5721 /******************************************************************************/
5722 /********************  Bits definition for RNG_CR register  *******************/
5723 #define RNG_CR_RNGEN_Pos                    (2U)
5724 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
5725 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
5726 #define RNG_CR_IE_Pos                       (3U)
5727 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
5728 #define RNG_CR_IE                           RNG_CR_IE_Msk
5729 #define RNG_CR_CED_Pos                      (5U)
5730 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
5731 #define RNG_CR_CED                          RNG_CR_CED_Msk
5732 #define RNG_CR_ARDIS_Pos                    (7U)
5733 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
5734 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
5735 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
5736 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
5737 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
5738 #define RNG_CR_NISTC_Pos                    (12U)
5739 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
5740 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
5741 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
5742 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
5743 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
5744 #define RNG_CR_CLKDIV_Pos                   (16U)
5745 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
5746 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
5747 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
5748 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
5749 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
5750 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
5751 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
5752 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
5753 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
5754 #define RNG_CR_CONDRST_Pos                  (30U)
5755 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
5756 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
5757 #define RNG_CR_CONFIGLOCK_Pos               (31U)
5758 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
5759 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
5760 
5761 /********************  Bits definition for RNG_SR register  *******************/
5762 #define RNG_SR_DRDY_Pos     (0U)
5763 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
5764 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
5765 #define RNG_SR_CECS_Pos     (1U)
5766 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
5767 #define RNG_SR_CECS         RNG_SR_CECS_Msk
5768 #define RNG_SR_SECS_Pos     (2U)
5769 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
5770 #define RNG_SR_SECS         RNG_SR_SECS_Msk
5771 #define RNG_SR_CEIS_Pos     (5U)
5772 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
5773 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
5774 #define RNG_SR_SEIS_Pos     (6U)
5775 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
5776 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
5777 
5778 /********************  Bits definition for RNG_HTCR register  *******************/
5779 #define RNG_HTCR_HTCFG_Pos                  (0U)
5780 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
5781 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
5782 
5783 /******************************************************************************/
5784 /*                                                                            */
5785 /*                           Real-Time Clock (RTC)                            */
5786 /*                                                                            */
5787 /******************************************************************************/
5788 /********************  Bits definition for RTC_TR register  *******************/
5789 #define RTC_TR_SU_Pos                       (0U)
5790 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
5791 #define RTC_TR_SU                           RTC_TR_SU_Msk
5792 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
5793 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
5794 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
5795 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
5796 #define RTC_TR_ST_Pos                       (4U)
5797 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
5798 #define RTC_TR_ST                           RTC_TR_ST_Msk
5799 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
5800 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
5801 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
5802 #define RTC_TR_MNU_Pos                      (8U)
5803 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
5804 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
5805 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
5806 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
5807 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
5808 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
5809 #define RTC_TR_MNT_Pos                      (12U)
5810 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
5811 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
5812 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
5813 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
5814 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
5815 #define RTC_TR_HU_Pos                       (16U)
5816 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
5817 #define RTC_TR_HU                           RTC_TR_HU_Msk
5818 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
5819 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
5820 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
5821 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
5822 #define RTC_TR_HT_Pos                       (20U)
5823 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
5824 #define RTC_TR_HT                           RTC_TR_HT_Msk
5825 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
5826 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
5827 #define RTC_TR_PM_Pos                       (22U)
5828 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
5829 #define RTC_TR_PM                           RTC_TR_PM_Msk
5830 
5831 /********************  Bits definition for RTC_DR register  *******************/
5832 #define RTC_DR_DU_Pos                       (0U)
5833 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
5834 #define RTC_DR_DU                           RTC_DR_DU_Msk
5835 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
5836 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
5837 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
5838 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
5839 #define RTC_DR_DT_Pos                       (4U)
5840 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
5841 #define RTC_DR_DT                           RTC_DR_DT_Msk
5842 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
5843 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
5844 #define RTC_DR_MU_Pos                       (8U)
5845 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
5846 #define RTC_DR_MU                           RTC_DR_MU_Msk
5847 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
5848 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
5849 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
5850 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
5851 #define RTC_DR_MT_Pos                       (12U)
5852 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
5853 #define RTC_DR_MT                           RTC_DR_MT_Msk
5854 #define RTC_DR_WDU_Pos                      (13U)
5855 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
5856 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
5857 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
5858 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
5859 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
5860 #define RTC_DR_YU_Pos                       (16U)
5861 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
5862 #define RTC_DR_YU                           RTC_DR_YU_Msk
5863 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
5864 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
5865 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
5866 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
5867 #define RTC_DR_YT_Pos                       (20U)
5868 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
5869 #define RTC_DR_YT                           RTC_DR_YT_Msk
5870 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
5871 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
5872 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
5873 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
5874 
5875 /********************  Bits definition for RTC_SSR register  ******************/
5876 #define RTC_SSR_SS_Pos                      (0U)
5877 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
5878 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
5879 
5880 /********************  Bits definition for RTC_ICSR register  ******************/
5881 #define RTC_ICSR_WUTWF_Pos                  (2U)
5882 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
5883 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
5884 #define RTC_ICSR_SHPF_Pos                   (3U)
5885 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
5886 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
5887 #define RTC_ICSR_INITS_Pos                  (4U)
5888 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
5889 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
5890 #define RTC_ICSR_RSF_Pos                    (5U)
5891 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
5892 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
5893 #define RTC_ICSR_INITF_Pos                  (6U)
5894 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
5895 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
5896 #define RTC_ICSR_INIT_Pos                   (7U)
5897 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
5898 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
5899 #define RTC_ICSR_BIN_Pos                    (8U)
5900 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
5901 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
5902 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
5903 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
5904 #define RTC_ICSR_BCDU_Pos                   (10U)
5905 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
5906 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
5907 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
5908 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
5909 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
5910 #define RTC_ICSR_RECALPF_Pos                (16U)
5911 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
5912 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
5913 
5914 /********************  Bits definition for RTC_PRER register  *****************/
5915 #define RTC_PRER_PREDIV_S_Pos               (0U)
5916 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
5917 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
5918 #define RTC_PRER_PREDIV_A_Pos               (16U)
5919 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
5920 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
5921 
5922 /********************  Bits definition for RTC_WUTR register  *****************/
5923 #define RTC_WUTR_WUT_Pos                    (0U)
5924 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
5925 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
5926 #define RTC_WUTR_WUTOCLR_Pos                (16U)
5927 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
5928 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
5929 
5930 /********************  Bits definition for RTC_CR register  *******************/
5931 #define RTC_CR_WUCKSEL_Pos                  (0U)
5932 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
5933 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
5934 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
5935 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
5936 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
5937 #define RTC_CR_TSEDGE_Pos                   (3U)
5938 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
5939 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
5940 #define RTC_CR_REFCKON_Pos                  (4U)
5941 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
5942 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
5943 #define RTC_CR_BYPSHAD_Pos                  (5U)
5944 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
5945 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
5946 #define RTC_CR_FMT_Pos                      (6U)
5947 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
5948 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
5949 #define RTC_CR_SSRUIE_Pos                   (7U)
5950 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
5951 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
5952 #define RTC_CR_ALRAE_Pos                    (8U)
5953 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
5954 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
5955 #define RTC_CR_ALRBE_Pos                    (9U)
5956 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
5957 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
5958 #define RTC_CR_WUTE_Pos                     (10U)
5959 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
5960 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
5961 #define RTC_CR_TSE_Pos                      (11U)
5962 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
5963 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
5964 #define RTC_CR_ALRAIE_Pos                   (12U)
5965 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
5966 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
5967 #define RTC_CR_ALRBIE_Pos                   (13U)
5968 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
5969 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
5970 #define RTC_CR_WUTIE_Pos                    (14U)
5971 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
5972 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
5973 #define RTC_CR_TSIE_Pos                     (15U)
5974 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
5975 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
5976 #define RTC_CR_ADD1H_Pos                    (16U)
5977 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
5978 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
5979 #define RTC_CR_SUB1H_Pos                    (17U)
5980 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
5981 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
5982 #define RTC_CR_BKP_Pos                      (18U)
5983 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
5984 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
5985 #define RTC_CR_COSEL_Pos                    (19U)
5986 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
5987 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
5988 #define RTC_CR_POL_Pos                      (20U)
5989 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
5990 #define RTC_CR_POL                          RTC_CR_POL_Msk
5991 #define RTC_CR_OSEL_Pos                     (21U)
5992 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
5993 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
5994 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
5995 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
5996 #define RTC_CR_COE_Pos                      (23U)
5997 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
5998 #define RTC_CR_COE                          RTC_CR_COE_Msk
5999 #define RTC_CR_ITSE_Pos                     (24U)
6000 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
6001 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
6002 #define RTC_CR_TAMPTS_Pos                   (25U)
6003 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
6004 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
6005 #define RTC_CR_TAMPOE_Pos                   (26U)
6006 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
6007 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
6008 #define RTC_CR_ALRAFCLR_Pos                 (27U)
6009 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
6010 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
6011 #define RTC_CR_ALRBFCLR_Pos                 (28U)
6012 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
6013 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
6014 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
6015 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
6016 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
6017 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
6018 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
6019 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
6020 #define RTC_CR_OUT2EN_Pos                   (31U)
6021 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
6022 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
6023 
6024 /********************  Bits definition for RTC_WPR register  ******************/
6025 #define RTC_WPR_KEY_Pos                     (0U)
6026 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
6027 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
6028 
6029 /********************  Bits definition for RTC_CALR register  *****************/
6030 #define RTC_CALR_CALM_Pos                   (0U)
6031 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
6032 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
6033 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
6034 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
6035 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
6036 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
6037 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
6038 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
6039 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
6040 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
6041 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
6042 #define RTC_CALR_LPCAL_Pos                  (12U)
6043 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
6044 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
6045 #define RTC_CALR_CALW16_Pos                 (13U)
6046 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
6047 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
6048 #define RTC_CALR_CALW8_Pos                  (14U)
6049 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
6050 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
6051 #define RTC_CALR_CALP_Pos                   (15U)
6052 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
6053 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
6054 
6055 /********************  Bits definition for RTC_SHIFTR register  ***************/
6056 #define RTC_SHIFTR_SUBFS_Pos                (0U)
6057 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
6058 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
6059 #define RTC_SHIFTR_ADD1S_Pos                (31U)
6060 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
6061 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
6062 
6063 /********************  Bits definition for RTC_TSTR register  *****************/
6064 #define RTC_TSTR_SU_Pos                     (0U)
6065 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
6066 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
6067 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
6068 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
6069 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
6070 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
6071 #define RTC_TSTR_ST_Pos                     (4U)
6072 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
6073 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
6074 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
6075 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
6076 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
6077 #define RTC_TSTR_MNU_Pos                    (8U)
6078 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
6079 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
6080 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
6081 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
6082 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
6083 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
6084 #define RTC_TSTR_MNT_Pos                    (12U)
6085 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
6086 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
6087 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
6088 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
6089 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
6090 #define RTC_TSTR_HU_Pos                     (16U)
6091 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
6092 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
6093 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
6094 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
6095 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
6096 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
6097 #define RTC_TSTR_HT_Pos                     (20U)
6098 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
6099 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
6100 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
6101 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
6102 #define RTC_TSTR_PM_Pos                     (22U)
6103 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
6104 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
6105 
6106 /********************  Bits definition for RTC_TSDR register  *****************/
6107 #define RTC_TSDR_DU_Pos                     (0U)
6108 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
6109 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
6110 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
6111 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
6112 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
6113 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
6114 #define RTC_TSDR_DT_Pos                     (4U)
6115 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
6116 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
6117 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
6118 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
6119 #define RTC_TSDR_MU_Pos                     (8U)
6120 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
6121 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
6122 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
6123 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
6124 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
6125 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
6126 #define RTC_TSDR_MT_Pos                     (12U)
6127 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
6128 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
6129 #define RTC_TSDR_WDU_Pos                    (13U)
6130 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
6131 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
6132 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
6133 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
6134 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
6135 
6136 /********************  Bits definition for RTC_TSSSR register  ****************/
6137 #define RTC_TSSSR_SS_Pos                    (0U)
6138 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
6139 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
6140 
6141 /********************  Bits definition for RTC_ALRMAR register  ***************/
6142 #define RTC_ALRMAR_SU_Pos                   (0U)
6143 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
6144 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
6145 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
6146 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
6147 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
6148 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
6149 #define RTC_ALRMAR_ST_Pos                   (4U)
6150 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
6151 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
6152 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
6153 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
6154 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
6155 #define RTC_ALRMAR_MSK1_Pos                 (7U)
6156 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
6157 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
6158 #define RTC_ALRMAR_MNU_Pos                  (8U)
6159 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
6160 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
6161 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
6162 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
6163 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
6164 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
6165 #define RTC_ALRMAR_MNT_Pos                  (12U)
6166 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
6167 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
6168 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
6169 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
6170 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
6171 #define RTC_ALRMAR_MSK2_Pos                 (15U)
6172 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
6173 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
6174 #define RTC_ALRMAR_HU_Pos                   (16U)
6175 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
6176 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
6177 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
6178 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
6179 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
6180 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
6181 #define RTC_ALRMAR_HT_Pos                   (20U)
6182 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
6183 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
6184 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
6185 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
6186 #define RTC_ALRMAR_PM_Pos                   (22U)
6187 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
6188 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
6189 #define RTC_ALRMAR_MSK3_Pos                 (23U)
6190 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
6191 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
6192 #define RTC_ALRMAR_DU_Pos                   (24U)
6193 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
6194 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
6195 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
6196 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
6197 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
6198 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
6199 #define RTC_ALRMAR_DT_Pos                   (28U)
6200 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
6201 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
6202 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
6203 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
6204 #define RTC_ALRMAR_WDSEL_Pos                (30U)
6205 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
6206 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
6207 #define RTC_ALRMAR_MSK4_Pos                 (31U)
6208 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
6209 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
6210 
6211 /********************  Bits definition for RTC_ALRMASSR register  *************/
6212 #define RTC_ALRMASSR_SS_Pos                 (0U)
6213 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
6214 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
6215 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
6216 #define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
6217 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
6218 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
6219 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
6220 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
6221 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
6222 #define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
6223 #define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
6224 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
6225 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
6226 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
6227 
6228 /********************  Bits definition for RTC_ALRMBR register  ***************/
6229 #define RTC_ALRMBR_SU_Pos                   (0U)
6230 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
6231 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
6232 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
6233 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
6234 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
6235 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
6236 #define RTC_ALRMBR_ST_Pos                   (4U)
6237 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
6238 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
6239 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
6240 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
6241 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
6242 #define RTC_ALRMBR_MSK1_Pos                 (7U)
6243 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
6244 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
6245 #define RTC_ALRMBR_MNU_Pos                  (8U)
6246 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
6247 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
6248 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
6249 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
6250 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
6251 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
6252 #define RTC_ALRMBR_MNT_Pos                  (12U)
6253 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
6254 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
6255 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
6256 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
6257 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
6258 #define RTC_ALRMBR_MSK2_Pos                 (15U)
6259 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
6260 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
6261 #define RTC_ALRMBR_HU_Pos                   (16U)
6262 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
6263 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
6264 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
6265 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
6266 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
6267 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
6268 #define RTC_ALRMBR_HT_Pos                   (20U)
6269 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
6270 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
6271 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
6272 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
6273 #define RTC_ALRMBR_PM_Pos                   (22U)
6274 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
6275 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
6276 #define RTC_ALRMBR_MSK3_Pos                 (23U)
6277 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
6278 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
6279 #define RTC_ALRMBR_DU_Pos                   (24U)
6280 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
6281 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
6282 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
6283 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
6284 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
6285 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
6286 #define RTC_ALRMBR_DT_Pos                   (28U)
6287 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
6288 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
6289 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
6290 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
6291 #define RTC_ALRMBR_WDSEL_Pos                (30U)
6292 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
6293 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
6294 #define RTC_ALRMBR_MSK4_Pos                 (31U)
6295 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
6296 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
6297 
6298 /********************  Bits definition for RTC_ALRMBSSR register  *************/
6299 #define RTC_ALRMBSSR_SS_Pos                 (0U)
6300 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
6301 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
6302 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
6303 #define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
6304 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
6305 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
6306 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
6307 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
6308 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
6309 #define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
6310 #define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
6311 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
6312 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
6313 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
6314 
6315 /********************  Bits definition for RTC_SR register  *******************/
6316 #define RTC_SR_ALRAF_Pos                    (0U)
6317 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
6318 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
6319 #define RTC_SR_ALRBF_Pos                    (1U)
6320 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
6321 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
6322 #define RTC_SR_WUTF_Pos                     (2U)
6323 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
6324 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
6325 #define RTC_SR_TSF_Pos                      (3U)
6326 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
6327 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
6328 #define RTC_SR_TSOVF_Pos                    (4U)
6329 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
6330 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
6331 #define RTC_SR_ITSF_Pos                     (5U)
6332 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
6333 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
6334 #define RTC_SR_SSRUF_Pos                    (6U)
6335 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
6336 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
6337 
6338 /********************  Bits definition for RTC_MISR register  *****************/
6339 #define RTC_MISR_ALRAMF_Pos                 (0U)
6340 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
6341 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
6342 #define RTC_MISR_ALRBMF_Pos                 (1U)
6343 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
6344 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
6345 #define RTC_MISR_WUTMF_Pos                  (2U)
6346 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
6347 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
6348 #define RTC_MISR_TSMF_Pos                   (3U)
6349 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
6350 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
6351 #define RTC_MISR_TSOVMF_Pos                 (4U)
6352 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
6353 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
6354 #define RTC_MISR_ITSMF_Pos                  (5U)
6355 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
6356 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
6357 #define RTC_MISR_SSRUMF_Pos                 (6U)
6358 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
6359 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
6360 
6361 /********************  Bits definition for RTC_SCR register  ******************/
6362 #define RTC_SCR_CALRAF_Pos                  (0U)
6363 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
6364 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
6365 #define RTC_SCR_CALRBF_Pos                  (1U)
6366 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
6367 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
6368 #define RTC_SCR_CWUTF_Pos                   (2U)
6369 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
6370 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
6371 #define RTC_SCR_CTSF_Pos                    (3U)
6372 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
6373 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
6374 #define RTC_SCR_CTSOVF_Pos                  (4U)
6375 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
6376 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
6377 #define RTC_SCR_CITSF_Pos                   (5U)
6378 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
6379 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
6380 #define RTC_SCR_CSSRUF_Pos                  (6U)
6381 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
6382 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
6383 
6384 /********************  Bits definition for RTC_ALRABINR register  ******************/
6385 #define RTC_ALRABINR_SS_Pos                 (0U)
6386 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
6387 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
6388 
6389 /********************  Bits definition for RTC_ALRBBINR register  ******************/
6390 #define RTC_ALRBBINR_SS_Pos                 (0U)
6391 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
6392 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
6393 
6394 /******************************************************************************/
6395 /*                                                                            */
6396 /*                     Tamper and backup register (TAMP)                      */
6397 /*                                                                            */
6398 /******************************************************************************/
6399 /********************  Bits definition for TAMP_CR1 register  *****************/
6400 #define TAMP_CR1_TAMP1E_Pos          (0U)
6401 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
6402 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
6403 #define TAMP_CR1_TAMP2E_Pos          (1U)
6404 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
6405 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
6406 #define TAMP_CR1_TAMP3E_Pos          (2U)
6407 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
6408 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
6409 #define TAMP_CR1_TAMP4E_Pos          (3U)
6410 #define TAMP_CR1_TAMP4E_Msk          (0x1UL << TAMP_CR1_TAMP4E_Pos)            /*!< 0x00000008 */
6411 #define TAMP_CR1_TAMP4E              TAMP_CR1_TAMP4E_Msk
6412 #define TAMP_CR1_TAMP5E_Pos          (4U)
6413 #define TAMP_CR1_TAMP5E_Msk          (0x1UL << TAMP_CR1_TAMP5E_Pos)            /*!< 0x00000010 */
6414 #define TAMP_CR1_TAMP5E              TAMP_CR1_TAMP5E_Msk
6415 #define TAMP_CR1_ITAMP3E_Pos         (18U)
6416 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
6417 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
6418 #define TAMP_CR1_ITAMP4E_Pos         (19U)
6419 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
6420 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
6421 #define TAMP_CR1_ITAMP5E_Pos         (20U)
6422 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
6423 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
6424 #define TAMP_CR1_ITAMP6E_Pos         (21U)
6425 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
6426 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
6427 
6428 /********************  Bits definition for TAMP_CR2 register  *****************/
6429 #define TAMP_CR2_TAMP1POM_Pos        (0U)
6430 #define TAMP_CR2_TAMP1POM_Msk        (0x1UL << TAMP_CR2_TAMP1POM_Pos)      /*!< 0x00000001 */
6431 #define TAMP_CR2_TAMP1POM            TAMP_CR2_TAMP1POM_Msk
6432 #define TAMP_CR2_TAMP2POM_Pos        (1U)
6433 #define TAMP_CR2_TAMP2POM_Msk        (0x1UL << TAMP_CR2_TAMP2POM_Pos)      /*!< 0x00000002 */
6434 #define TAMP_CR2_TAMP2POM            TAMP_CR2_TAMP2POM_Msk
6435 #define TAMP_CR2_TAMP3POM_Pos        (2U)
6436 #define TAMP_CR2_TAMP3POM_Msk        (0x1UL << TAMP_CR2_TAMP3POM_Pos)      /*!< 0x00000004 */
6437 #define TAMP_CR2_TAMP3POM            TAMP_CR2_TAMP3POM_Msk
6438 #define TAMP_CR2_TAMP4POM_Pos        (3U)
6439 #define TAMP_CR2_TAMP4POM_Msk        (0x1UL << TAMP_CR2_TAMP4POM_Pos)      /*!< 0x00000004 */
6440 #define TAMP_CR2_TAMP4POM            TAMP_CR2_TAMP4POM_Msk
6441 #define TAMP_CR2_TAMP5POM_Pos        (4U)
6442 #define TAMP_CR2_TAMP5POM_Msk        (0x1UL << TAMP_CR2_TAMP5POM_Pos)      /*!< 0x00000004 */
6443 #define TAMP_CR2_TAMP5POM            TAMP_CR2_TAMP5POM_Msk
6444 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
6445 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
6446 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
6447 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
6448 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
6449 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
6450 #define TAMP_CR2_TAMP3MSK_Pos        (18U)
6451 #define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
6452 #define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
6453 #define TAMP_CR2_BKBLOCK_Pos         (22U)
6454 #define TAMP_CR2_BKBLOCK_Msk         (0x1UL << TAMP_CR2_BKBLOCK_Pos)           /*!< 0x00400000 */
6455 #define TAMP_CR2_BKBLOCK             TAMP_CR2_BKBLOCK_Msk
6456 #define TAMP_CR2_BKERASE_Pos         (23U)
6457 #define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)           /*!< 0x00800000 */
6458 #define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
6459 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
6460 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
6461 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
6462 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
6463 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
6464 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
6465 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
6466 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
6467 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
6468 #define TAMP_CR2_TAMP4TRG_Pos        (27U)
6469 #define TAMP_CR2_TAMP4TRG_Msk        (0x1UL << TAMP_CR2_TAMP4TRG_Pos)          /*!< 0x04000000 */
6470 #define TAMP_CR2_TAMP4TRG            TAMP_CR2_TAMP4TRG_Msk
6471 #define TAMP_CR2_TAMP5TRG_Pos        (28U)
6472 #define TAMP_CR2_TAMP5TRG_Msk        (0x1UL << TAMP_CR2_TAMP5TRG_Pos)          /*!< 0x04000000 */
6473 #define TAMP_CR2_TAMP5TRG            TAMP_CR2_TAMP5TRG_Msk
6474 
6475 /********************  Bits definition for TAMP_CR3 register  *****************/
6476 #define TAMP_CR3_ITAMP3POM_Pos             (2U)
6477 #define TAMP_CR3_ITAMP3POM_Msk             (0x1UL << TAMP_CR3_ITAMP3POM_Pos)      /*!< 0x00000004 */
6478 #define TAMP_CR3_ITAMP3POM                 TAMP_CR3_ITAMP3POM_Msk
6479 #define TAMP_CR3_ITAMP4POM_Pos             (3U)
6480 #define TAMP_CR3_ITAMP4POM_Msk             (0x1UL << TAMP_CR3_ITAMP4POM_Pos)      /*!< 0x00000008 */
6481 #define TAMP_CR3_ITAMP4POM                 TAMP_CR3_ITAMP4POM_Msk
6482 #define TAMP_CR3_ITAMP5POM_Pos             (4U)
6483 #define TAMP_CR3_ITAMP5POM_Msk             (0x1UL << TAMP_CR3_ITAMP5POM_Pos)      /*!< 0x00000010 */
6484 #define TAMP_CR3_ITAMP5POM                 TAMP_CR3_ITAMP5NOER_Msk
6485 #define TAMP_CR3_ITAMP6POM_Pos             (5U)
6486 #define TAMP_CR3_ITAMP6POM_Msk             (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos)      /*!< 0x00000020 */
6487 #define TAMP_CR3_ITAMP6POM                 TAMP_CR3_ITAMP6POM_Msk
6488 
6489 /********************  Bits definition for TAMP_FLTCR register  ***************/
6490 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
6491 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
6492 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
6493 #define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */
6494 #define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */
6495 #define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */
6496 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
6497 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
6498 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
6499 #define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */
6500 #define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */
6501 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
6502 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
6503 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
6504 #define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */
6505 #define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */
6506 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
6507 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
6508 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
6509 
6510 /********************  Bits definition for TAMP_IER register  *****************/
6511 #define TAMP_IER_TAMP1IE_Pos         (0U)
6512 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
6513 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
6514 #define TAMP_IER_TAMP2IE_Pos         (1U)
6515 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
6516 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
6517 #define TAMP_IER_TAMP3IE_Pos         (2U)
6518 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
6519 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
6520 #define TAMP_IER_TAMP4IE_Pos         (3U)
6521 #define TAMP_IER_TAMP4IE_Msk         (0x1UL << TAMP_IER_TAMP4IE_Pos)           /*!< 0x00000004 */
6522 #define TAMP_IER_TAMP4IE             TAMP_IER_TAMP4IE_Msk
6523 #define TAMP_IER_TAMP5IE_Pos         (4U)
6524 #define TAMP_IER_TAMP5IE_Msk         (0x1UL << TAMP_IER_TAMP5IE_Pos)           /*!< 0x00000004 */
6525 #define TAMP_IER_TAMP5IE             TAMP_IER_TAMP5IE_Msk
6526 #define TAMP_IER_ITAMP3IE_Pos        (18U)
6527 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
6528 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
6529 #define TAMP_IER_ITAMP4IE_Pos        (19U)
6530 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
6531 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
6532 #define TAMP_IER_ITAMP5IE_Pos        (20U)
6533 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
6534 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
6535 #define TAMP_IER_ITAMP6IE_Pos        (21U)
6536 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
6537 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
6538 
6539 /********************  Bits definition for TAMP_SR register  *****************/
6540 #define TAMP_SR_TAMP1F_Pos           (0U)
6541 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
6542 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
6543 #define TAMP_SR_TAMP2F_Pos           (1U)
6544 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */
6545 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
6546 #define TAMP_SR_TAMP3F_Pos           (2U)
6547 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
6548 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
6549 #define TAMP_SR_TAMP4F_Pos           (3U)
6550 #define TAMP_SR_TAMP4F_Msk           (0x1UL << TAMP_SR_TAMP4F_Pos)             /*!< 0x00000004 */
6551 #define TAMP_SR_TAMP4F               TAMP_SR_TAMP4F_Msk
6552 #define TAMP_SR_TAMP5F_Pos           (4U)
6553 #define TAMP_SR_TAMP5F_Msk           (0x1UL << TAMP_SR_TAMP5F_Pos)             /*!< 0x00000004 */
6554 #define TAMP_SR_TAMP5F               TAMP_SR_TAMP5F_Msk
6555 #define TAMP_SR_ITAMP3F_Pos          (18U)
6556 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */
6557 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
6558 #define TAMP_SR_ITAMP4F_Pos          (19U)
6559 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */
6560 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
6561 #define TAMP_SR_ITAMP5F_Pos          (20U)
6562 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */
6563 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
6564 #define TAMP_SR_ITAMP6F_Pos          (21U)
6565 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */
6566 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
6567 
6568 /********************  Bits definition for TAMP_MISR register  ************ *****/
6569 #define TAMP_MISR_TAMP1MF_Pos        (0U)
6570 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
6571 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
6572 #define TAMP_MISR_TAMP2MF_Pos        (1U)
6573 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
6574 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
6575 #define TAMP_MISR_TAMP3MF_Pos        (2U)
6576 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
6577 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
6578 #define TAMP_MISR_TAMP4MF_Pos        (3U)
6579 #define TAMP_MISR_TAMP4MF_Msk        (0x1UL << TAMP_MISR_TAMP4MF_Pos)          /*!< 0x00000004 */
6580 #define TAMP_MISR_TAMP4MF            TAMP_MISR_TAMP4MF_Msk
6581 #define TAMP_MISR_TAMP5MF_Pos        (4U)
6582 #define TAMP_MISR_TAMP5MF_Msk        (0x1UL << TAMP_MISR_TAMP5MF_Pos)          /*!< 0x00000004 */
6583 #define TAMP_MISR_TAMP5MF            TAMP_MISR_TAMP5MF_Msk
6584 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
6585 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */
6586 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
6587 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
6588 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */
6589 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
6590 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
6591 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */
6592 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
6593 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
6594 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */
6595 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
6596 
6597 /********************  Bits definition for TAMP_SCR register  *****************/
6598 #define TAMP_SCR_CTAMP1F_Pos         (0U)
6599 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
6600 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
6601 #define TAMP_SCR_CTAMP2F_Pos         (1U)
6602 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
6603 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
6604 #define TAMP_SCR_CTAMP3F_Pos         (2U)
6605 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
6606 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
6607 #define TAMP_SCR_CTAMP4F_Pos         (3U)
6608 #define TAMP_SCR_CTAMP4F_Msk         (0x1UL << TAMP_SCR_CTAMP4F_Pos)           /*!< 0x00000004 */
6609 #define TAMP_SCR_CTAMP4F             TAMP_SCR_CTAMP4F_Msk
6610 #define TAMP_SCR_CTAMP5F_Pos         (4U)
6611 #define TAMP_SCR_CTAMP5F_Msk         (0x1UL << TAMP_SCR_CTAMP5F_Pos)           /*!< 0x00000004 */
6612 #define TAMP_SCR_CTAMP5F             TAMP_SCR_CTAMP5F_Msk
6613 #define TAMP_SCR_CITAMP3F_Pos        (18U)
6614 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
6615 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
6616 #define TAMP_SCR_CITAMP4F_Pos        (19U)
6617 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */
6618 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
6619 #define TAMP_SCR_CITAMP5F_Pos        (20U)
6620 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
6621 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
6622 #define TAMP_SCR_CITAMP6F_Pos        (21U)
6623 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */
6624 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
6625 
6626 /********************  Bits definition for TAMP_BKP0R register  ***************/
6627 #define TAMP_BKP0R_Pos               (0U)
6628 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
6629 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
6630 
6631 /********************  Bits definition for TAMP_BKP1R register  ****************/
6632 #define TAMP_BKP1R_Pos               (0U)
6633 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
6634 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
6635 
6636 /********************  Bits definition for TAMP_BKP2R register  ****************/
6637 #define TAMP_BKP2R_Pos               (0U)
6638 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
6639 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
6640 
6641 /********************  Bits definition for TAMP_BKP3R register  ****************/
6642 #define TAMP_BKP3R_Pos               (0U)
6643 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
6644 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
6645 
6646 /********************  Bits definition for TAMP_BKP4R register  ****************/
6647 #define TAMP_BKP4R_Pos               (0U)
6648 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
6649 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
6650 
6651 /********************  Bits definition for TAMP_BKP5R register  ****************/
6652 #define TAMP_BKP5R_Pos               (0U)
6653 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
6654 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
6655 
6656 /********************  Bits definition for TAMP_BKP6R register  ****************/
6657 #define TAMP_BKP6R_Pos               (0U)
6658 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
6659 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
6660 
6661 /********************  Bits definition for TAMP_BKP7R register  ****************/
6662 #define TAMP_BKP7R_Pos               (0U)
6663 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
6664 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
6665 
6666 /********************  Bits definition for TAMP_BKP8R register  ****************/
6667 #define TAMP_BKP8R_Pos               (0U)
6668 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
6669 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
6670 
6671 /******************** Number of backup registers ******************************/
6672 #define TAMP_BKP_NUMBER_Pos             (4U)
6673 #define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */
6674 #define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 9 BKPREG  */
6675 
6676 /******************************************************************************/
6677 /*                                                                            */
6678 /*                   Serial Peripheral Interface (SPI)                        */
6679 /*                                                                            */
6680 /******************************************************************************/
6681 /*
6682  * @brief Specific device feature definitions
6683  */
6684 
6685 /*******************  Bit definition for SPI_CR1 register  ********************/
6686 #define SPI_CR1_CPHA_Pos            (0U)
6687 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
6688 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
6689 #define SPI_CR1_CPOL_Pos            (1U)
6690 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
6691 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
6692 #define SPI_CR1_MSTR_Pos            (2U)
6693 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
6694 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
6695 
6696 #define SPI_CR1_BR_Pos              (3U)
6697 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
6698 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
6699 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
6700 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
6701 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
6702 
6703 #define SPI_CR1_SPE_Pos             (6U)
6704 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
6705 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
6706 #define SPI_CR1_LSBFIRST_Pos        (7U)
6707 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
6708 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
6709 #define SPI_CR1_SSI_Pos             (8U)
6710 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
6711 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
6712 #define SPI_CR1_SSM_Pos             (9U)
6713 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
6714 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
6715 #define SPI_CR1_RXONLY_Pos          (10U)
6716 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
6717 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
6718 #define SPI_CR1_CRCL_Pos            (11U)
6719 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
6720 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
6721 #define SPI_CR1_CRCNEXT_Pos         (12U)
6722 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
6723 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
6724 #define SPI_CR1_CRCEN_Pos           (13U)
6725 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
6726 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
6727 #define SPI_CR1_BIDIOE_Pos          (14U)
6728 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
6729 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
6730 #define SPI_CR1_BIDIMODE_Pos        (15U)
6731 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
6732 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
6733 
6734 /*******************  Bit definition for SPI_CR2 register  ********************/
6735 #define SPI_CR2_RXDMAEN_Pos         (0U)
6736 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
6737 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
6738 #define SPI_CR2_TXDMAEN_Pos         (1U)
6739 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
6740 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
6741 #define SPI_CR2_SSOE_Pos            (2U)
6742 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
6743 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
6744 #define SPI_CR2_NSSP_Pos            (3U)
6745 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
6746 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
6747 #define SPI_CR2_FRF_Pos             (4U)
6748 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
6749 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
6750 #define SPI_CR2_ERRIE_Pos           (5U)
6751 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
6752 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
6753 #define SPI_CR2_RXNEIE_Pos          (6U)
6754 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
6755 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
6756 #define SPI_CR2_TXEIE_Pos           (7U)
6757 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
6758 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
6759 #define SPI_CR2_DS_Pos              (8U)
6760 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
6761 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
6762 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
6763 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
6764 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
6765 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
6766 #define SPI_CR2_FRXTH_Pos           (12U)
6767 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
6768 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
6769 #define SPI_CR2_LDMARX_Pos          (13U)
6770 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
6771 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
6772 #define SPI_CR2_LDMATX_Pos          (14U)
6773 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
6774 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
6775 
6776 /********************  Bit definition for SPI_SR register  ********************/
6777 #define SPI_SR_RXNE_Pos             (0U)
6778 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
6779 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
6780 #define SPI_SR_TXE_Pos              (1U)
6781 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
6782 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
6783 #define SPI_SR_CHSIDE_Pos           (2U)
6784 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
6785 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
6786 #define SPI_SR_UDR_Pos              (3U)
6787 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
6788 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
6789 #define SPI_SR_CRCERR_Pos           (4U)
6790 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
6791 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
6792 #define SPI_SR_MODF_Pos             (5U)
6793 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
6794 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
6795 #define SPI_SR_OVR_Pos              (6U)
6796 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
6797 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
6798 #define SPI_SR_BSY_Pos              (7U)
6799 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
6800 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
6801 #define SPI_SR_FRE_Pos              (8U)
6802 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
6803 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
6804 #define SPI_SR_FRLVL_Pos            (9U)
6805 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
6806 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
6807 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
6808 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
6809 #define SPI_SR_FTLVL_Pos            (11U)
6810 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
6811 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
6812 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
6813 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
6814 
6815 /********************  Bit definition for SPI_DR register  ********************/
6816 #define SPI_DR_DR_Pos               (0U)
6817 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
6818 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
6819 
6820 /*******************  Bit definition for SPI_CRCPR register  ******************/
6821 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
6822 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
6823 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
6824 
6825 /******************  Bit definition for SPI_RXCRCR register  ******************/
6826 #define SPI_RXCRCR_RXCRC_Pos        (0U)
6827 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
6828 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
6829 
6830 /******************  Bit definition for SPI_TXCRCR register  ******************/
6831 #define SPI_TXCRCR_TXCRC_Pos        (0U)
6832 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
6833 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
6834 
6835 /******************************************************************************/
6836 /*                                                                            */
6837 /*                                 SYSCFG                                     */
6838 /*                                                                            */
6839 /******************************************************************************/
6840 
6841 /******************  Bit definition for SYSCFG_CFGR1 register  ******************/
6842 #define SYSCFG_CFGR1_MEM_MODE_Pos       (0U)
6843 #define SYSCFG_CFGR1_MEM_MODE_Msk       (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)     /*!< 0x00000003 */
6844 #define SYSCFG_CFGR1_MEM_MODE           SYSCFG_CFGR1_MEM_MODE_Msk                /*!< SYSCFG_Memory Remap Config */
6845 #define SYSCFG_CFGR1_MEM_MODE_0         (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)     /*!< 0x00000001 */
6846 #define SYSCFG_CFGR1_MEM_MODE_1         (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)     /*!< 0x00000002 */
6847 #define SYSCFG_CFGR1_PA11_RMP_Pos       (3U)
6848 #define SYSCFG_CFGR1_PA11_RMP_Msk       (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos)     /*!< 0x00000008 */
6849 #define SYSCFG_CFGR1_PA11_RMP           SYSCFG_CFGR1_PA11_RMP_Msk                /*!< PA11 Remap */
6850 #define SYSCFG_CFGR1_PA12_RMP_Pos       (4U)
6851 #define SYSCFG_CFGR1_PA12_RMP_Msk       (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos)     /*!< 0x00000010 */
6852 #define SYSCFG_CFGR1_PA12_RMP           SYSCFG_CFGR1_PA12_RMP_Msk                /*!< PA12 Remap */
6853 #define SYSCFG_CFGR1_IR_POL_Pos         (5U)
6854 #define SYSCFG_CFGR1_IR_POL_Msk         (0x1UL << SYSCFG_CFGR1_IR_POL_Pos)       /*!< 0x00000020 */
6855 #define SYSCFG_CFGR1_IR_POL             SYSCFG_CFGR1_IR_POL_Msk                  /*!< IROut Polarity Selection */
6856 #define SYSCFG_CFGR1_IR_MOD_Pos         (6U)
6857 #define SYSCFG_CFGR1_IR_MOD_Msk         (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos)       /*!< 0x000000C0 */
6858 #define SYSCFG_CFGR1_IR_MOD             SYSCFG_CFGR1_IR_MOD_Msk                  /*!< IRDA Modulation Envelope signal source selection */
6859 #define SYSCFG_CFGR1_IR_MOD_0           (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos)       /*!< 0x00000040 */
6860 #define SYSCFG_CFGR1_IR_MOD_1           (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos)       /*!< 0x00000080 */
6861 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
6862 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)      /*!< 0x00000100 */
6863 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk                 /*!< I/O analog switch voltage booster enable */
6864 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
6865 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)  /*!< 0x00010000 */
6866 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk             /*!< I2C PB6 Fast mode plus */
6867 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
6868 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)  /*!< 0x00020000 */
6869 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk             /*!< I2C PB7 Fast mode plus */
6870 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
6871 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)  /*!< 0x00040000 */
6872 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk             /*!< I2C PB8 Fast mode plus */
6873 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
6874 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)  /*!< 0x00080000 */
6875 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk             /*!< I2C PB9 Fast mode plus */
6876 #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos    (22U)
6877 #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)  /*!< 0x00400000 */
6878 #define SYSCFG_CFGR1_I2C_PA9_FMP        SYSCFG_CFGR1_I2C_PA9_FMP_Msk             /*!< Enable Fast Mode Plus on PA9  */
6879 #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos   (23U)
6880 #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk   (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
6881 #define SYSCFG_CFGR1_I2C_PA10_FMP       SYSCFG_CFGR1_I2C_PA10_FMP_Msk            /*!< Enable Fast Mode Plus on PA10 */
6882 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (24U)
6883 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)     /*!< 0x01000000 */
6884 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk                /*!< Enable Fast Mode Plus for I2C3 */
6885 
6886 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
6887 #define SYSCFG_CFGR2_CCL_Pos            (0U)
6888 #define SYSCFG_CFGR2_CCL_Msk            (0x1UL << SYSCFG_CFGR2_CCL_Pos)         /*!< 0x00000001 */
6889 #define SYSCFG_CFGR2_CCL                SYSCFG_CFGR2_CCL_Msk                    /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input */
6890 #define SYSCFG_CFGR2_SPL_Pos            (1U)
6891 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
6892 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                    /*!< Enables and locks the SRAM Parity error signal with TIMERs Break Input */
6893 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
6894 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
6895 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                   /*!< Enables and locks the PVD connection with TIMERs Break Input */
6896 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
6897 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
6898 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                   /*!< Enables and locks the FLASH ECC error with TIMERs Break Input */
6899 #define SYSCFG_CFGR2_BKPL_Pos           (4U)
6900 #define SYSCFG_CFGR2_BKPL_Msk           (0x1UL << SYSCFG_CFGR2_BKPL_Pos)        /*!< 0x00000010 */
6901 #define SYSCFG_CFGR2_BKPL               SYSCFG_CFGR2_BKPL_Msk                   /*!< Enables and locks the BackUp SRAM Parity error signal with TIMERs Break Input */
6902 #define SYSCFG_CFGR2_BKPF_Pos           (7U)
6903 #define SYSCFG_CFGR2_BKPF_Msk           (0x1UL << SYSCFG_CFGR2_BKPF_Pos)        /*!< 0x00000080 */
6904 #define SYSCFG_CFGR2_BKPF               SYSCFG_CFGR2_BKPF_Msk                   /*!< Saves the occurrence of the BackUpSRAM Parity Error */
6905 #define SYSCFG_CFGR2_SPF_Pos            (8U)
6906 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
6907 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                    /*!< Saves the occurrence of the SRAM Parity Error */
6908 
6909 /******************  Bit definition for SYSCFG_SCSR register  ****************/
6910 #define SYSCFG_SCSR_SRAM2ER_Pos         (0U)
6911 #define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)       /*!< 0x00000001 */
6912 #define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                  /*!< Starts a hardware BackUpSRAM erase operation */
6913 #define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)
6914 #define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)      /*!< 0x00000002 */
6915 #define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk                 /*!< BackUpSRAM Erase Ongoing Status Flag*/
6916 
6917 /******************  Bit definition for SYSCFG_SER register  ****************/
6918 #define SYSCFG_SKR_KEY_Pos              (0U)
6919 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)           /*!< 0x000000FF */
6920 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                       /*!< Write BackUpSRAM Key for software erase */
6921 
6922 /******************  Bit definition for SYSCFG_TSCCR register  ****************/
6923 #define SYSCFG_TSCCR_G2IO1_Pos          (0U)
6924 #define SYSCFG_TSCCR_G2IO1_Msk          (0x1UL << SYSCFG_TSCCR_G2IO1_Pos)         /*!< 0x00000001 */
6925 #define SYSCFG_TSCCR_G2IO1              SYSCFG_TSCCR_G2IO1_Msk                    /*!< Enable the comparator mode with the IO1 of Group2 (PB4 on INPLUS of COMP2) */
6926 #define SYSCFG_TSCCR_G2IO3_Pos          (1U)
6927 #define SYSCFG_TSCCR_G2IO3_Msk          (0x1UL << SYSCFG_TSCCR_G2IO3_Pos)         /*!< 0x00000002 */
6928 #define SYSCFG_TSCCR_G2IO3              SYSCFG_TSCCR_G2IO3_Msk                    /*!< Enable the comparator mode with the IO3 of Group2 (PB6 on INPLUS of COMP2) */
6929 #define SYSCFG_TSCCR_G4IO1_Pos          (2U)
6930 #define SYSCFG_TSCCR_G4IO1_Msk          (0x1UL << SYSCFG_TSCCR_G4IO1_Pos)         /*!< 0x00000004 */
6931 #define SYSCFG_TSCCR_G4IO1              SYSCFG_TSCCR_G4IO1_Msk                    /*!< Enable the comparator mode with the IO1 of Group4 (PC6 on INPLUS of COMP1) */
6932 #define SYSCFG_TSCCR_G6IO1_Pos          (3U)
6933 #define SYSCFG_TSCCR_G6IO1_Msk          (0x1UL << SYSCFG_TSCCR_G6IO1_Pos)         /*!< 0x00000008 */
6934 #define SYSCFG_TSCCR_G6IO1              SYSCFG_TSCCR_G6IO1_Msk                    /*!< Enable the comparator mode with the IO1 of Group6 (PD10 on INPLUS of COMP2) */
6935 #define SYSCFG_TSCCR_G7IO2_Pos          (4U)
6936 #define SYSCFG_TSCCR_G7IO2_Msk          (0x1UL << SYSCFG_TSCCR_G7IO2_Pos)         /*!< 0x00000010 */
6937 #define SYSCFG_TSCCR_G7IO2              SYSCFG_TSCCR_G7IO2_Msk                    /*!< Enable the comparator mode with the IO2 of Group7 (PA9 on INPLUS of COMP1) */
6938 #define SYSCFG_TSCCR_TSCIOCTRL_Pos      (5U)
6939 #define SYSCFG_TSCCR_TSCIOCTRL_Msk      (0x1UL << SYSCFG_TSCCR_TSCIOCTRL_Pos)     /*!< 0x00000020 */
6940 #define SYSCFG_TSCCR_TSCIOCTRL          SYSCFG_TSCCR_TSCIOCTRL_Msk                /*!< Program Comparator mode (programmed via alternate function) */
6941 
6942 /*****************  Bit definition for SYSCFG_ITLINEx ISR Wrapper register  ****************/
6943 #define SYSCFG_ITLINE0_SR_WWDG_Pos         (0U)
6944 #define SYSCFG_ITLINE0_SR_WWDG_Msk         (0x1UL << SYSCFG_ITLINE0_SR_WWDG_Pos)       /*!< 0x00000001 */
6945 #define SYSCFG_ITLINE0_SR_WWDG             SYSCFG_ITLINE0_SR_WWDG_Msk                  /*!< WWDG interrupt */
6946 
6947 #define SYSCFG_ITLINE1_SR_PVDOUT_Pos       (0U)
6948 #define SYSCFG_ITLINE1_SR_PVDOUT_Msk       (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos)     /*!< 0x00000001 */
6949 #define SYSCFG_ITLINE1_SR_PVDOUT           SYSCFG_ITLINE1_SR_PVDOUT_Msk                /*!< PVDOUT interrupt */
6950 #define SYSCFG_ITLINE1_SR_PVMOUT3_Pos      (2U)
6951 #define SYSCFG_ITLINE1_SR_PVMOUT3_Msk      (0x1UL << SYSCFG_ITLINE1_SR_PVMOUT3_Pos)    /*!< 0x00000004 */
6952 #define SYSCFG_ITLINE1_SR_PVMOUT3          SYSCFG_ITLINE1_SR_PVMOUT3_Msk               /*!< VDDADC interrupt */
6953 #define SYSCFG_ITLINE1_SR_PVMOUT4_Pos      (3)
6954 #define SYSCFG_ITLINE1_SR_PVMOUT4_Msk      (0x1UL << SYSCFG_ITLINE1_SR_PVMOUT4_Pos)    /*!< 0x00000008 */
6955 #define SYSCFG_ITLINE1_SR_PVMOUT4          SYSCFG_ITLINE1_SR_PVMOUT4_Msk               /*!< VDDADC interrupt */
6956 
6957 #define SYSCFG_ITLINE2_SR_TAMPER_Pos       (0U)
6958 #define SYSCFG_ITLINE2_SR_TAMPER_Msk       (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos)     /*!< 0x00000001 */
6959 #define SYSCFG_ITLINE2_SR_TAMPER           SYSCFG_ITLINE2_SR_TAMPER_Msk                /*!< TAMPER interrupt */
6960 #define SYSCFG_ITLINE2_SR_RTC_Pos          (1U)
6961 #define SYSCFG_ITLINE2_SR_RTC_Msk          (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos)        /*!< 0x00000001 */
6962 #define SYSCFG_ITLINE2_SR_RTC              SYSCFG_ITLINE2_SR_RTC_Msk                   /*!< RTC interrupt */
6963 
6964 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos    (0U)
6965 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk    (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos)  /*!< 0x00000001 */
6966 #define SYSCFG_ITLINE3_SR_FLASH_ECC        SYSCFG_ITLINE3_SR_FLASH_ECC_Msk             /*!< FLASH ECC interrupt */
6967 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos    (1U)
6968 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk    (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos)  /*!< 0x00000002 */
6969 #define SYSCFG_ITLINE3_SR_FLASH_ITF        SYSCFG_ITLINE3_SR_FLASH_ITF_Msk             /*!< FLASH ITF interrupt */
6970 
6971 #define SYSCFG_ITLINE4_SR_RCC_Pos          (0U)
6972 #define SYSCFG_ITLINE4_SR_RCC_Msk          (0x1UL << SYSCFG_ITLINE4_SR_RCC_Pos)        /*!< 0x00000001 */
6973 #define SYSCFG_ITLINE4_SR_RCC              SYSCFG_ITLINE4_SR_RCC_Msk                   /*!< RCC interrupt */
6974 #define SYSCFG_ITLINE5_SR_EXTI0_Pos        (0U)
6975 #define SYSCFG_ITLINE5_SR_EXTI0_Msk        (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos)      /*!< 0x00000001 */
6976 #define SYSCFG_ITLINE5_SR_EXTI0            SYSCFG_ITLINE5_SR_EXTI0_Msk                 /*!< External Interrupt 0 */
6977 #define SYSCFG_ITLINE5_SR_EXTI1_Pos        (1U)
6978 #define SYSCFG_ITLINE5_SR_EXTI1_Msk        (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos)      /*!< 0x00000002 */
6979 #define SYSCFG_ITLINE5_SR_EXTI1            SYSCFG_ITLINE5_SR_EXTI1_Msk                 /*!< External Interrupt 1 */
6980 
6981 #define SYSCFG_ITLINE6_SR_EXTI2_Pos        (0U)
6982 #define SYSCFG_ITLINE6_SR_EXTI2_Msk        (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos)      /*!< 0x00000001 */
6983 #define SYSCFG_ITLINE6_SR_EXTI2            SYSCFG_ITLINE6_SR_EXTI2_Msk                 /*!< External Interrupt 2 */
6984 #define SYSCFG_ITLINE6_SR_EXTI3_Pos        (1U)
6985 #define SYSCFG_ITLINE6_SR_EXTI3_Msk        (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos)      /*!< 0x00000002 */
6986 #define SYSCFG_ITLINE6_SR_EXTI3            SYSCFG_ITLINE6_SR_EXTI3_Msk                 /*!< External Interrupt 3 */
6987 
6988 #define SYSCFG_ITLINE7_SR_EXTI4_Pos        (0U)
6989 #define SYSCFG_ITLINE7_SR_EXTI4_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos)      /*!< 0x00000001 */
6990 #define SYSCFG_ITLINE7_SR_EXTI4            SYSCFG_ITLINE7_SR_EXTI4_Msk                 /*!< External Interrupt 4 */
6991 #define SYSCFG_ITLINE7_SR_EXTI5_Pos        (1U)
6992 #define SYSCFG_ITLINE7_SR_EXTI5_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos)      /*!< 0x00000002 */
6993 #define SYSCFG_ITLINE7_SR_EXTI5            SYSCFG_ITLINE7_SR_EXTI5_Msk                 /*!< External Interrupt 5 */
6994 #define SYSCFG_ITLINE7_SR_EXTI6_Pos        (2U)
6995 #define SYSCFG_ITLINE7_SR_EXTI6_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos)      /*!< 0x00000004 */
6996 #define SYSCFG_ITLINE7_SR_EXTI6            SYSCFG_ITLINE7_SR_EXTI6_Msk                 /*!< External Interrupt 6 */
6997 #define SYSCFG_ITLINE7_SR_EXTI7_Pos        (3U)
6998 #define SYSCFG_ITLINE7_SR_EXTI7_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos)      /*!< 0x00000008 */
6999 #define SYSCFG_ITLINE7_SR_EXTI7            SYSCFG_ITLINE7_SR_EXTI7_Msk                 /*!< External Interrupt 7 */
7000 #define SYSCFG_ITLINE7_SR_EXTI8_Pos        (4U)
7001 #define SYSCFG_ITLINE7_SR_EXTI8_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos)      /*!< 0x00000010 */
7002 #define SYSCFG_ITLINE7_SR_EXTI8            SYSCFG_ITLINE7_SR_EXTI8_Msk                 /*!< External Interrupt 8 */
7003 #define SYSCFG_ITLINE7_SR_EXTI9_Pos        (5U)
7004 #define SYSCFG_ITLINE7_SR_EXTI9_Msk        (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos)      /*!< 0x00000020 */
7005 #define SYSCFG_ITLINE7_SR_EXTI9            SYSCFG_ITLINE7_SR_EXTI9_Msk                 /*!< External Interrupt 9 */
7006 #define SYSCFG_ITLINE7_SR_EXTI10_Pos       (6U)
7007 #define SYSCFG_ITLINE7_SR_EXTI10_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos)     /*!< 0x00000040 */
7008 #define SYSCFG_ITLINE7_SR_EXTI10           SYSCFG_ITLINE7_SR_EXTI10_Msk                /*!< External Interrupt 10 */
7009 #define SYSCFG_ITLINE7_SR_EXTI11_Pos       (7U)
7010 #define SYSCFG_ITLINE7_SR_EXTI11_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos)     /*!< 0x00000080 */
7011 #define SYSCFG_ITLINE7_SR_EXTI11           SYSCFG_ITLINE7_SR_EXTI11_Msk                /*!< External Interrupt 11 */
7012 #define SYSCFG_ITLINE7_SR_EXTI12_Pos       (8U)
7013 #define SYSCFG_ITLINE7_SR_EXTI12_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos)     /*!< 0x00000100 */
7014 #define SYSCFG_ITLINE7_SR_EXTI12           SYSCFG_ITLINE7_SR_EXTI12_Msk                /*!< External Interrupt 12 */
7015 #define SYSCFG_ITLINE7_SR_EXTI13_Pos       (9U)
7016 #define SYSCFG_ITLINE7_SR_EXTI13_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos)     /*!< 0x00000200 */
7017 #define SYSCFG_ITLINE7_SR_EXTI13           SYSCFG_ITLINE7_SR_EXTI13_Msk                /*!< External Interrupt 13 */
7018 #define SYSCFG_ITLINE7_SR_EXTI14_Pos       (10U)
7019 #define SYSCFG_ITLINE7_SR_EXTI14_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos)     /*!< 0x00000400 */
7020 #define SYSCFG_ITLINE7_SR_EXTI14           SYSCFG_ITLINE7_SR_EXTI14_Msk                /*!< External Interrupt 14 */
7021 #define SYSCFG_ITLINE7_SR_EXTI15_Pos       (11U)
7022 #define SYSCFG_ITLINE7_SR_EXTI15_Msk       (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos)     /*!< 0x00000800 */
7023 #define SYSCFG_ITLINE7_SR_EXTI15           SYSCFG_ITLINE7_SR_EXTI15_Msk                /*!< External Interrupt 15 */
7024 
7025 
7026 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos     (0U)
7027 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk     (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos)   /*!< 0x00000001 */
7028 #define SYSCFG_ITLINE9_SR_DMA1_CH1         SYSCFG_ITLINE9_SR_DMA1_CH1_Msk              /*!< DMA1 Channel 1 Interrupt */
7029 
7030 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos    (0U)
7031 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk    (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos)  /*!< 0x00000001 */
7032 #define SYSCFG_ITLINE10_SR_DMA1_CH2        SYSCFG_ITLINE10_SR_DMA1_CH2_Msk             /*!< DMA1 Channel 2 Interrupt */
7033 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos    (1U)
7034 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk    (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos)  /*!< 0x00000002 */
7035 #define SYSCFG_ITLINE10_SR_DMA1_CH3        SYSCFG_ITLINE10_SR_DMA1_CH3_Msk             /*!< DMA1 Channel 3 Interrupt */
7036 
7037 #define SYSCFG_ITLINE11_SR_DMAMUX_Pos      (0U)
7038 #define SYSCFG_ITLINE11_SR_DMAMUX_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX_Pos)    /*!< 0x00000001 */
7039 #define SYSCFG_ITLINE11_SR_DMAMUX          SYSCFG_ITLINE11_SR_DMAMUX_Msk               /*!< DMAMUX Interrupt */
7040 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos    (1U)
7041 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos)  /*!< 0x00000002 */
7042 #define SYSCFG_ITLINE11_SR_DMA1_CH4        SYSCFG_ITLINE11_SR_DMA1_CH4_Msk             /*!< DMA1 Channel 4 Interrupt */
7043 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos    (2U)
7044 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos)  /*!< 0x00000004 */
7045 #define SYSCFG_ITLINE11_SR_DMA1_CH5        SYSCFG_ITLINE11_SR_DMA1_CH5_Msk             /*!< DMA1 Channel 5 Interrupt */
7046 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos    (3U)
7047 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos)  /*!< 0x00000008 */
7048 #define SYSCFG_ITLINE11_SR_DMA1_CH6        SYSCFG_ITLINE11_SR_DMA1_CH6_Msk             /*!< DMA1 Channel 6 Interrupt */
7049 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos    (4U)
7050 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk    (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos)  /*!< 0x00000010 */
7051 #define SYSCFG_ITLINE11_SR_DMA1_CH7        SYSCFG_ITLINE11_SR_DMA1_CH7_Msk             /*!< DMA1 Channel 7 Interrupt */
7052 
7053 #define SYSCFG_ITLINE12_SR_ADC_Pos         (0U)
7054 #define SYSCFG_ITLINE12_SR_ADC_Msk         (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos)       /*!< 0x00000001 */
7055 #define SYSCFG_ITLINE12_SR_ADC             SYSCFG_ITLINE12_SR_ADC_Msk                  /*!< ADC Interrupt */
7056 #define SYSCFG_ITLINE12_SR_COMP1_Pos       (1U)
7057 #define SYSCFG_ITLINE12_SR_COMP1_Msk       (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos)     /*!< 0x00000002 */
7058 #define SYSCFG_ITLINE12_SR_COMP1           SYSCFG_ITLINE12_SR_COMP1_Msk                /*!< COMP1 Interrupt -> exti[17] */
7059 
7060 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos    (0U)
7061 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos)  /*!< 0x00000001 */
7062 #define SYSCFG_ITLINE13_SR_TIM1_CCU        SYSCFG_ITLINE13_SR_TIM1_CCU_Msk             /*!< TIM1 CCU Interrupt */
7063 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos    (1U)
7064 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos)  /*!< 0x00000002 */
7065 #define SYSCFG_ITLINE13_SR_TIM1_TRG        SYSCFG_ITLINE13_SR_TIM1_TRG_Msk             /*!< TIM1 TRG Interrupt */
7066 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos    (2U)
7067 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos)  /*!< 0x00000004 */
7068 #define SYSCFG_ITLINE13_SR_TIM1_UPD        SYSCFG_ITLINE13_SR_TIM1_UPD_Msk             /*!< TIM1 UPD Interrupt */
7069 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos    (3U)
7070 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk    (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos)  /*!< 0x00000008 */
7071 #define SYSCFG_ITLINE13_SR_TIM1_BRK        SYSCFG_ITLINE13_SR_TIM1_BRK_Msk             /*!< TIM1 BRK Interrupt */
7072 
7073 #define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos    (0U)
7074 #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos)  /*!< 0x00000001 */
7075 #define SYSCFG_ITLINE14_SR_TIM1_CC1        SYSCFG_ITLINE14_SR_TIM1_CC1_Msk             /*!< TIM1 CC1 Interrupt */
7076 #define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos    (1U)
7077 #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos)  /*!< 0x00000002 */
7078 #define SYSCFG_ITLINE14_SR_TIM1_CC2        SYSCFG_ITLINE14_SR_TIM1_CC2_Msk             /*!< TIM1 CC2 Interrupt */
7079 #define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos    (2U)
7080 #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos)  /*!< 0x00000004 */
7081 #define SYSCFG_ITLINE14_SR_TIM1_CC3        SYSCFG_ITLINE14_SR_TIM1_CC3_Msk             /*!< TIM1 CC3 Interrupt */
7082 #define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos    (3U)
7083 #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk    (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos)  /*!< 0x00000008 */
7084 #define SYSCFG_ITLINE14_SR_TIM1_CC4        SYSCFG_ITLINE14_SR_TIM1_CC4_Msk             /*!< TIM1 CC4 Interrupt */
7085 
7086 #define SYSCFG_ITLINE15_SR_TIM2_Pos        (0U)
7087 #define SYSCFG_ITLINE15_SR_TIM2_Msk        (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos)      /*!< 0x00000001 */
7088 #define SYSCFG_ITLINE15_SR_TIM2            SYSCFG_ITLINE15_SR_TIM2_Msk                 /*!< TIM2 GLB Interrupt */
7089 
7090 #define SYSCFG_ITLINE16_SR_TIM3_Pos        (0U)
7091 #define SYSCFG_ITLINE16_SR_TIM3_Msk        (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos)      /*!< 0x00000001 */
7092 #define SYSCFG_ITLINE16_SR_TIM3            SYSCFG_ITLINE16_SR_TIM3_Msk                 /*!< TIM3 GLB Interrupt */
7093 
7094 #define SYSCFG_ITLINE17_SR_TIM6_Pos        (0U)
7095 #define SYSCFG_ITLINE17_SR_TIM6_Msk        (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos)      /*!< 0x00000001 */
7096 #define SYSCFG_ITLINE17_SR_TIM6            SYSCFG_ITLINE17_SR_TIM6_Msk                 /*!< TIM6 GLB Interrupt */
7097 #define SYSCFG_ITLINE17_SR_DAC_Pos         (1U)
7098 #define SYSCFG_ITLINE17_SR_DAC_Msk         (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos)       /*!< 0x00000002 */
7099 #define SYSCFG_ITLINE17_SR_DAC             SYSCFG_ITLINE17_SR_DAC_Msk                  /*!< DAC Interrupt */
7100 #define SYSCFG_ITLINE17_SR_LPTIM1_Pos      (2U)
7101 #define SYSCFG_ITLINE17_SR_LPTIM1_Msk      (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos)    /*!< 0x00000004 */
7102 #define SYSCFG_ITLINE17_SR_LPTIM1          SYSCFG_ITLINE17_SR_LPTIM1_Msk               /*!< LPTIM1 -> exti[24] Interrupt */
7103 
7104 #define SYSCFG_ITLINE18_SR_TIM7_Pos        (0U)
7105 #define SYSCFG_ITLINE18_SR_TIM7_Msk        (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos)      /*!< 0x00000001 */
7106 #define SYSCFG_ITLINE18_SR_TIM7            SYSCFG_ITLINE18_SR_TIM7_Msk                 /*!< TIM7 GLB Interrupt */
7107 #define SYSCFG_ITLINE18_SR_LPTIM2_Pos      (1U)
7108 #define SYSCFG_ITLINE18_SR_LPTIM2_Msk      (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos)    /*!< 0x00000002 */
7109 #define SYSCFG_ITLINE18_SR_LPTIM2          SYSCFG_ITLINE18_SR_LPTIM2_Msk               /*!< LPTIM2 -> exti[25] Interrupt */
7110 
7111 #define SYSCFG_ITLINE19_SR_TIM15_Pos       (0U)
7112 #define SYSCFG_ITLINE19_SR_TIM15_Msk       (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos)     /*!< 0x00000001 */
7113 #define SYSCFG_ITLINE19_SR_TIM15           SYSCFG_ITLINE19_SR_TIM15_Msk                /*!< TIM15 GLB Interrupt */
7114 
7115 #define SYSCFG_ITLINE20_SR_TIM16_Pos       (0U)
7116 #define SYSCFG_ITLINE20_SR_TIM16_Msk       (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos)     /*!< 0x00000001 */
7117 #define SYSCFG_ITLINE20_SR_TIM16           SYSCFG_ITLINE20_SR_TIM16_Msk                /*!< TIM16 GLB Interrupt */
7118 
7119 #define SYSCFG_ITLINE21_SR_TSC_MCE_Pos     (0U)
7120 #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk     (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos)   /*!< 0x00000001 */
7121 #define SYSCFG_ITLINE21_SR_TSC_MCE         SYSCFG_ITLINE21_SR_TSC_MCE_Msk              /*!< TSC_MCE Interrupt */
7122 #define SYSCFG_ITLINE21_SR_TSC_EOA_Pos     (1U)
7123 #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk     (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos)   /*!< 0x00000001 */
7124 #define SYSCFG_ITLINE21_SR_TSC_EOA         SYSCFG_ITLINE21_SR_TSC_EOA_Msk              /*!< TSC_MCE Interrupt */
7125 
7126 
7127 #define SYSCFG_ITLINE23_SR_I2C1_Pos        (0U)
7128 #define SYSCFG_ITLINE23_SR_I2C1_Msk        (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos)      /*!< 0x00000001 */
7129 #define SYSCFG_ITLINE23_SR_I2C1            SYSCFG_ITLINE23_SR_I2C1_Msk                 /*!< I2C1 GLB Interrupt */
7130 
7131 #define SYSCFG_ITLINE24_SR_I2C2_Pos        (0U)
7132 #define SYSCFG_ITLINE24_SR_I2C2_Msk        (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos)      /*!< 0x00000001 */
7133 #define SYSCFG_ITLINE24_SR_I2C2            SYSCFG_ITLINE24_SR_I2C2_Msk                 /*!< I2C2 GLB Interrupt */
7134 #define SYSCFG_ITLINE24_SR_I2C4_Pos        (1U)
7135 #define SYSCFG_ITLINE24_SR_I2C4_Msk        (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos)      /*!< 0x00000002 */
7136 #define SYSCFG_ITLINE24_SR_I2C4            SYSCFG_ITLINE24_SR_I2C4_Msk                 /*!< I2C3 GLB Interrupt */
7137 #define SYSCFG_ITLINE24_SR_I2C3_Pos        (2U)
7138 #define SYSCFG_ITLINE24_SR_I2C3_Msk        (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos)      /*!< 0x00000004 */
7139 #define SYSCFG_ITLINE24_SR_I2C3            SYSCFG_ITLINE24_SR_I2C3_Msk                 /*!< I2C3 GLB Interrupt  -> exti[23]*/
7140 
7141 #define SYSCFG_ITLINE25_SR_SPI1_Pos        (0U)
7142 #define SYSCFG_ITLINE25_SR_SPI1_Msk        (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos)      /*!< 0x00000001 */
7143 #define SYSCFG_ITLINE25_SR_SPI1            SYSCFG_ITLINE25_SR_SPI1_Msk                 /*!< SPI1 Interrupt */
7144 
7145 #define SYSCFG_ITLINE26_SR_SPI2_Pos        (0U)
7146 #define SYSCFG_ITLINE26_SR_SPI2_Msk        (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos)      /*!< 0x00000001 */
7147 #define SYSCFG_ITLINE26_SR_SPI2            SYSCFG_ITLINE26_SR_SPI2_Msk                 /*!< SPI2  Interrupt */
7148 
7149 #define SYSCFG_ITLINE27_SR_USART1_Pos      (0U)
7150 #define SYSCFG_ITLINE27_SR_USART1_Msk      (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos)    /*!< 0x00000001 */
7151 #define SYSCFG_ITLINE27_SR_USART1          SYSCFG_ITLINE27_SR_USART1_Msk               /*!< USART1 GLB Interrupt */
7152 
7153 #define SYSCFG_ITLINE28_SR_USART2_Pos      (0U)
7154 #define SYSCFG_ITLINE28_SR_USART2_Msk      (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos)    /*!< 0x00000001 */
7155 #define SYSCFG_ITLINE28_SR_USART2          SYSCFG_ITLINE28_SR_USART2_Msk               /*!< USART2 GLB Interrupt */
7156 #define SYSCFG_ITLINE28_SR_LPUART2_Pos     (1U)
7157 #define SYSCFG_ITLINE28_SR_LPUART2_Msk     (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos)   /*!< 0x00000002 */
7158 #define SYSCFG_ITLINE28_SR_LPUART2         SYSCFG_ITLINE28_SR_LPUART2_Msk              /*!< LPUART2 GLB Interrupt -> exti[31] */
7159 
7160 #define SYSCFG_ITLINE29_SR_USART3_Pos      (0U)
7161 #define SYSCFG_ITLINE29_SR_USART3_Msk      (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos)    /*!< 0x00000001 */
7162 #define SYSCFG_ITLINE29_SR_USART3          SYSCFG_ITLINE29_SR_USART3_Msk               /*!< USART3 GLB Interrupt */
7163 #define SYSCFG_ITLINE29_SR_LPUART1_Pos     (1U)
7164 #define SYSCFG_ITLINE29_SR_LPUART1_Msk     (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos)   /*!< 0x00000002 */
7165 #define SYSCFG_ITLINE29_SR_LPUART1         SYSCFG_ITLINE29_SR_LPUART1_Msk              /*!< LPUART1 GLB Interrupt -> exti[30] */
7166 
7167 #define SYSCFG_ITLINE30_SR_USART4_Pos      (0U)
7168 #define SYSCFG_ITLINE30_SR_USART4_Msk      (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos)    /*!< 0x00000001 */
7169 #define SYSCFG_ITLINE30_SR_USART4          SYSCFG_ITLINE30_SR_USART4_Msk               /*!< USART4 GLB Interrupt */
7170 
7171 #define SYSCFG_ITLINE31_SR_RNG_Pos         (0U)
7172 #define SYSCFG_ITLINE31_SR_RNG_Msk         (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos)       /*!< 0x00000001 */
7173 #define SYSCFG_ITLINE31_SR_RNG             SYSCFG_ITLINE31_SR_RNG_Msk                  /*!< RNG Interrupt */
7174 
7175 /******************************************************************************/
7176 /*                                                                            */
7177 /*                                    TIM                                     */
7178 /*                                                                            */
7179 /******************************************************************************/
7180 /*******************  Bit definition for TIM_CR1 register  ********************/
7181 #define TIM_CR1_CEN_Pos           (0U)
7182 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
7183 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
7184 #define TIM_CR1_UDIS_Pos          (1U)
7185 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
7186 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
7187 #define TIM_CR1_URS_Pos           (2U)
7188 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
7189 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
7190 #define TIM_CR1_OPM_Pos           (3U)
7191 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
7192 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
7193 #define TIM_CR1_DIR_Pos           (4U)
7194 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
7195 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
7196 
7197 #define TIM_CR1_CMS_Pos           (5U)
7198 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
7199 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
7200 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
7201 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
7202 
7203 #define TIM_CR1_ARPE_Pos          (7U)
7204 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
7205 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
7206 
7207 #define TIM_CR1_CKD_Pos           (8U)
7208 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
7209 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
7210 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
7211 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
7212 
7213 #define TIM_CR1_UIFREMAP_Pos      (11U)
7214 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
7215 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
7216 
7217 /*******************  Bit definition for TIM_CR2 register  ********************/
7218 #define TIM_CR2_CCPC_Pos          (0U)
7219 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
7220 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
7221 #define TIM_CR2_CCUS_Pos          (2U)
7222 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
7223 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
7224 #define TIM_CR2_CCDS_Pos          (3U)
7225 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
7226 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
7227 
7228 #define TIM_CR2_MMS_Pos           (4U)
7229 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
7230 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
7231 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
7232 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
7233 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
7234 
7235 #define TIM_CR2_TI1S_Pos          (7U)
7236 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
7237 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
7238 #define TIM_CR2_OIS1_Pos          (8U)
7239 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
7240 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
7241 #define TIM_CR2_OIS1N_Pos         (9U)
7242 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
7243 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
7244 #define TIM_CR2_OIS2_Pos          (10U)
7245 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
7246 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
7247 #define TIM_CR2_OIS2N_Pos         (11U)
7248 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
7249 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
7250 #define TIM_CR2_OIS3_Pos          (12U)
7251 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
7252 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
7253 #define TIM_CR2_OIS3N_Pos         (13U)
7254 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
7255 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
7256 #define TIM_CR2_OIS4_Pos          (14U)
7257 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
7258 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
7259 #define TIM_CR2_OIS5_Pos          (16U)
7260 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
7261 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
7262 #define TIM_CR2_OIS6_Pos          (18U)
7263 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
7264 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
7265 
7266 #define TIM_CR2_MMS2_Pos          (20U)
7267 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
7268 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
7269 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
7270 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
7271 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
7272 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
7273 
7274 /*******************  Bit definition for TIM_SMCR register  *******************/
7275 #define TIM_SMCR_SMS_Pos          (0U)
7276 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
7277 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
7278 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
7279 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
7280 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
7281 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
7282 
7283 #define TIM_SMCR_OCCS_Pos         (3U)
7284 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
7285 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
7286 
7287 #define TIM_SMCR_TS_Pos           (4U)
7288 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
7289 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
7290 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
7291 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
7292 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
7293 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
7294 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
7295 
7296 #define TIM_SMCR_MSM_Pos          (7U)
7297 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
7298 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
7299 
7300 #define TIM_SMCR_ETF_Pos          (8U)
7301 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
7302 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
7303 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
7304 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
7305 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
7306 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
7307 
7308 #define TIM_SMCR_ETPS_Pos         (12U)
7309 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
7310 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
7311 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
7312 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
7313 
7314 #define TIM_SMCR_ECE_Pos          (14U)
7315 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
7316 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
7317 #define TIM_SMCR_ETP_Pos          (15U)
7318 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
7319 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
7320 
7321 /*******************  Bit definition for TIM_DIER register  *******************/
7322 #define TIM_DIER_UIE_Pos          (0U)
7323 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
7324 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
7325 #define TIM_DIER_CC1IE_Pos        (1U)
7326 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
7327 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
7328 #define TIM_DIER_CC2IE_Pos        (2U)
7329 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
7330 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
7331 #define TIM_DIER_CC3IE_Pos        (3U)
7332 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
7333 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
7334 #define TIM_DIER_CC4IE_Pos        (4U)
7335 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
7336 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
7337 #define TIM_DIER_COMIE_Pos        (5U)
7338 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
7339 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
7340 #define TIM_DIER_TIE_Pos          (6U)
7341 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
7342 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
7343 #define TIM_DIER_BIE_Pos          (7U)
7344 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
7345 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
7346 #define TIM_DIER_UDE_Pos          (8U)
7347 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
7348 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
7349 #define TIM_DIER_CC1DE_Pos        (9U)
7350 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
7351 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
7352 #define TIM_DIER_CC2DE_Pos        (10U)
7353 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
7354 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
7355 #define TIM_DIER_CC3DE_Pos        (11U)
7356 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
7357 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
7358 #define TIM_DIER_CC4DE_Pos        (12U)
7359 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
7360 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
7361 #define TIM_DIER_COMDE_Pos        (13U)
7362 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
7363 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
7364 #define TIM_DIER_TDE_Pos          (14U)
7365 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
7366 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
7367 
7368 /********************  Bit definition for TIM_SR register  ********************/
7369 #define TIM_SR_UIF_Pos            (0U)
7370 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
7371 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
7372 #define TIM_SR_CC1IF_Pos          (1U)
7373 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
7374 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
7375 #define TIM_SR_CC2IF_Pos          (2U)
7376 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
7377 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
7378 #define TIM_SR_CC3IF_Pos          (3U)
7379 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
7380 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
7381 #define TIM_SR_CC4IF_Pos          (4U)
7382 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
7383 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
7384 #define TIM_SR_COMIF_Pos          (5U)
7385 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
7386 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
7387 #define TIM_SR_TIF_Pos            (6U)
7388 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
7389 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
7390 #define TIM_SR_BIF_Pos            (7U)
7391 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
7392 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
7393 #define TIM_SR_B2IF_Pos           (8U)
7394 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
7395 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
7396 #define TIM_SR_CC1OF_Pos          (9U)
7397 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
7398 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
7399 #define TIM_SR_CC2OF_Pos          (10U)
7400 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
7401 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
7402 #define TIM_SR_CC3OF_Pos          (11U)
7403 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
7404 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
7405 #define TIM_SR_CC4OF_Pos          (12U)
7406 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
7407 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
7408 #define TIM_SR_SBIF_Pos           (13U)
7409 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
7410 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
7411 #define TIM_SR_CC5IF_Pos          (16U)
7412 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
7413 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
7414 #define TIM_SR_CC6IF_Pos          (17U)
7415 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
7416 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
7417 
7418 
7419 /*******************  Bit definition for TIM_EGR register  ********************/
7420 #define TIM_EGR_UG_Pos            (0U)
7421 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
7422 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
7423 #define TIM_EGR_CC1G_Pos          (1U)
7424 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
7425 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
7426 #define TIM_EGR_CC2G_Pos          (2U)
7427 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
7428 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
7429 #define TIM_EGR_CC3G_Pos          (3U)
7430 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
7431 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
7432 #define TIM_EGR_CC4G_Pos          (4U)
7433 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
7434 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
7435 #define TIM_EGR_COMG_Pos          (5U)
7436 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
7437 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
7438 #define TIM_EGR_TG_Pos            (6U)
7439 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
7440 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
7441 #define TIM_EGR_BG_Pos            (7U)
7442 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
7443 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
7444 #define TIM_EGR_B2G_Pos           (8U)
7445 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
7446 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
7447 
7448 
7449 /******************  Bit definition for TIM_CCMR1 register  *******************/
7450 #define TIM_CCMR1_CC1S_Pos        (0U)
7451 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
7452 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7453 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
7454 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
7455 
7456 #define TIM_CCMR1_OC1FE_Pos       (2U)
7457 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
7458 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
7459 #define TIM_CCMR1_OC1PE_Pos       (3U)
7460 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
7461 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
7462 
7463 #define TIM_CCMR1_OC1M_Pos        (4U)
7464 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
7465 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7466 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
7467 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
7468 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
7469 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
7470 
7471 #define TIM_CCMR1_OC1CE_Pos       (7U)
7472 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
7473 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
7474 
7475 #define TIM_CCMR1_CC2S_Pos        (8U)
7476 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
7477 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7478 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
7479 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
7480 
7481 #define TIM_CCMR1_OC2FE_Pos       (10U)
7482 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
7483 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
7484 #define TIM_CCMR1_OC2PE_Pos       (11U)
7485 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
7486 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
7487 
7488 #define TIM_CCMR1_OC2M_Pos        (12U)
7489 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
7490 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7491 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
7492 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
7493 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
7494 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
7495 
7496 #define TIM_CCMR1_OC2CE_Pos       (15U)
7497 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
7498 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
7499 
7500 /*----------------------------------------------------------------------------*/
7501 #define TIM_CCMR1_IC1PSC_Pos      (2U)
7502 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
7503 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7504 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
7505 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
7506 
7507 #define TIM_CCMR1_IC1F_Pos        (4U)
7508 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
7509 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7510 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
7511 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
7512 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
7513 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
7514 
7515 #define TIM_CCMR1_IC2PSC_Pos      (10U)
7516 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
7517 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7518 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
7519 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
7520 
7521 #define TIM_CCMR1_IC2F_Pos        (12U)
7522 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
7523 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7524 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
7525 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
7526 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
7527 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
7528 
7529 /******************  Bit definition for TIM_CCMR2 register  *******************/
7530 #define TIM_CCMR2_CC3S_Pos        (0U)
7531 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
7532 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7533 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
7534 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
7535 
7536 #define TIM_CCMR2_OC3FE_Pos       (2U)
7537 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
7538 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
7539 #define TIM_CCMR2_OC3PE_Pos       (3U)
7540 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
7541 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
7542 
7543 #define TIM_CCMR2_OC3M_Pos        (4U)
7544 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
7545 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7546 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
7547 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
7548 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
7549 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
7550 
7551 #define TIM_CCMR2_OC3CE_Pos       (7U)
7552 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
7553 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
7554 
7555 #define TIM_CCMR2_CC4S_Pos        (8U)
7556 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
7557 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7558 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
7559 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
7560 
7561 #define TIM_CCMR2_OC4FE_Pos       (10U)
7562 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
7563 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
7564 #define TIM_CCMR2_OC4PE_Pos       (11U)
7565 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
7566 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
7567 
7568 #define TIM_CCMR2_OC4M_Pos        (12U)
7569 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
7570 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7571 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
7572 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
7573 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
7574 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
7575 
7576 #define TIM_CCMR2_OC4CE_Pos       (15U)
7577 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
7578 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
7579 
7580 /*----------------------------------------------------------------------------*/
7581 #define TIM_CCMR2_IC3PSC_Pos      (2U)
7582 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
7583 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7584 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
7585 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
7586 
7587 #define TIM_CCMR2_IC3F_Pos        (4U)
7588 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
7589 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7590 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
7591 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
7592 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
7593 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
7594 
7595 #define TIM_CCMR2_IC4PSC_Pos      (10U)
7596 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
7597 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7598 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
7599 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
7600 
7601 #define TIM_CCMR2_IC4F_Pos        (12U)
7602 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
7603 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7604 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
7605 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
7606 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
7607 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
7608 
7609 /******************  Bit definition for TIM_CCMR3 register  *******************/
7610 #define TIM_CCMR3_OC5FE_Pos       (2U)
7611 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
7612 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
7613 #define TIM_CCMR3_OC5PE_Pos       (3U)
7614 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
7615 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
7616 
7617 #define TIM_CCMR3_OC5M_Pos        (4U)
7618 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
7619 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7620 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
7621 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
7622 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
7623 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
7624 
7625 #define TIM_CCMR3_OC5CE_Pos       (7U)
7626 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
7627 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
7628 
7629 #define TIM_CCMR3_OC6FE_Pos       (10U)
7630 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
7631 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
7632 #define TIM_CCMR3_OC6PE_Pos       (11U)
7633 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
7634 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
7635 
7636 #define TIM_CCMR3_OC6M_Pos        (12U)
7637 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
7638 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
7639 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
7640 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
7641 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
7642 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
7643 
7644 #define TIM_CCMR3_OC6CE_Pos       (15U)
7645 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
7646 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
7647 
7648 /*******************  Bit definition for TIM_CCER register  *******************/
7649 #define TIM_CCER_CC1E_Pos         (0U)
7650 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
7651 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
7652 #define TIM_CCER_CC1P_Pos         (1U)
7653 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
7654 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
7655 #define TIM_CCER_CC1NE_Pos        (2U)
7656 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
7657 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
7658 #define TIM_CCER_CC1NP_Pos        (3U)
7659 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
7660 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
7661 #define TIM_CCER_CC2E_Pos         (4U)
7662 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
7663 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
7664 #define TIM_CCER_CC2P_Pos         (5U)
7665 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
7666 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
7667 #define TIM_CCER_CC2NE_Pos        (6U)
7668 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
7669 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
7670 #define TIM_CCER_CC2NP_Pos        (7U)
7671 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
7672 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
7673 #define TIM_CCER_CC3E_Pos         (8U)
7674 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
7675 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
7676 #define TIM_CCER_CC3P_Pos         (9U)
7677 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
7678 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
7679 #define TIM_CCER_CC3NE_Pos        (10U)
7680 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
7681 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
7682 #define TIM_CCER_CC3NP_Pos        (11U)
7683 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
7684 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
7685 #define TIM_CCER_CC4E_Pos         (12U)
7686 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
7687 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
7688 #define TIM_CCER_CC4P_Pos         (13U)
7689 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
7690 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
7691 #define TIM_CCER_CC4NP_Pos        (15U)
7692 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
7693 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
7694 #define TIM_CCER_CC5E_Pos         (16U)
7695 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
7696 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
7697 #define TIM_CCER_CC5P_Pos         (17U)
7698 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
7699 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
7700 #define TIM_CCER_CC6E_Pos         (20U)
7701 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
7702 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
7703 #define TIM_CCER_CC6P_Pos         (21U)
7704 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
7705 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
7706 
7707 /*******************  Bit definition for TIM_CNT register  ********************/
7708 #define TIM_CNT_CNT_Pos           (0U)
7709 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
7710 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
7711 #define TIM_CNT_UIFCPY_Pos        (31U)
7712 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
7713 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
7714 
7715 /*******************  Bit definition for TIM_PSC register  ********************/
7716 #define TIM_PSC_PSC_Pos           (0U)
7717 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
7718 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
7719 
7720 /*******************  Bit definition for TIM_ARR register  ********************/
7721 #define TIM_ARR_ARR_Pos           (0U)
7722 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
7723 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
7724 
7725 /*******************  Bit definition for TIM_RCR register  ********************/
7726 #define TIM_RCR_REP_Pos           (0U)
7727 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
7728 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
7729 
7730 /*******************  Bit definition for TIM_CCR1 register  *******************/
7731 #define TIM_CCR1_CCR1_Pos         (0U)
7732 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
7733 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
7734 
7735 /*******************  Bit definition for TIM_CCR2 register  *******************/
7736 #define TIM_CCR2_CCR2_Pos         (0U)
7737 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
7738 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
7739 
7740 /*******************  Bit definition for TIM_CCR3 register  *******************/
7741 #define TIM_CCR3_CCR3_Pos         (0U)
7742 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
7743 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
7744 
7745 /*******************  Bit definition for TIM_CCR4 register  *******************/
7746 #define TIM_CCR4_CCR4_Pos         (0U)
7747 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
7748 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
7749 
7750 /*******************  Bit definition for TIM_CCR5 register  *******************/
7751 #define TIM_CCR5_CCR5_Pos         (0U)
7752 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
7753 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
7754 #define TIM_CCR5_GC5C1_Pos        (29U)
7755 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
7756 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
7757 #define TIM_CCR5_GC5C2_Pos        (30U)
7758 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
7759 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
7760 #define TIM_CCR5_GC5C3_Pos        (31U)
7761 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
7762 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
7763 
7764 /*******************  Bit definition for TIM_CCR6 register  *******************/
7765 #define TIM_CCR6_CCR6_Pos         (0U)
7766 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
7767 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
7768 
7769 /*******************  Bit definition for TIM_BDTR register  *******************/
7770 #define TIM_BDTR_DTG_Pos          (0U)
7771 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
7772 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7773 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
7774 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
7775 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
7776 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
7777 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
7778 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
7779 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
7780 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
7781 
7782 #define TIM_BDTR_LOCK_Pos         (8U)
7783 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
7784 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
7785 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
7786 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
7787 
7788 #define TIM_BDTR_OSSI_Pos         (10U)
7789 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
7790 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
7791 #define TIM_BDTR_OSSR_Pos         (11U)
7792 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
7793 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
7794 #define TIM_BDTR_BKE_Pos          (12U)
7795 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
7796 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
7797 #define TIM_BDTR_BKP_Pos          (13U)
7798 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
7799 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
7800 #define TIM_BDTR_AOE_Pos          (14U)
7801 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
7802 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
7803 #define TIM_BDTR_MOE_Pos          (15U)
7804 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
7805 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
7806 
7807 #define TIM_BDTR_BKF_Pos          (16U)
7808 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
7809 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
7810 #define TIM_BDTR_BK2F_Pos         (20U)
7811 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
7812 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
7813 
7814 #define TIM_BDTR_BK2E_Pos         (24U)
7815 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
7816 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
7817 #define TIM_BDTR_BK2P_Pos         (25U)
7818 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
7819 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
7820 
7821 #define TIM_BDTR_BKDSRM_Pos       (26U)
7822 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
7823 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
7824 #define TIM_BDTR_BK2DSRM_Pos      (27U)
7825 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
7826 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
7827 
7828 #define TIM_BDTR_BKBID_Pos        (28U)
7829 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
7830 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
7831 #define TIM_BDTR_BK2BID_Pos       (29U)
7832 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
7833 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
7834 
7835 /*******************  Bit definition for TIM_DCR register  ********************/
7836 #define TIM_DCR_DBA_Pos           (0U)
7837 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
7838 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
7839 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
7840 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
7841 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
7842 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
7843 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
7844 
7845 #define TIM_DCR_DBL_Pos           (8U)
7846 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
7847 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
7848 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
7849 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
7850 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
7851 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
7852 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
7853 
7854 /*******************  Bit definition for TIM_DMAR register  *******************/
7855 #define TIM_DMAR_DMAB_Pos         (0U)
7856 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
7857 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
7858 
7859 /*******************  Bit definition for TIM1_OR register  ********************/
7860 #define TIM_OR1_OCREF_CLR_Pos     (0U)
7861 #define TIM_OR1_OCREF_CLR_Msk     (0x1UL << TIM_OR1_OCREF_CLR_Pos)            /*!< 0x00000001 */
7862 #define TIM_OR1_OCREF_CLR         TIM_OR1_OCREF_CLR_Msk                       /*!<OCREF clear input selection */
7863 
7864 /*******************  Bit definition for TIM_AF1 register  *******************/
7865 #define TIM_AF1_BKINE_Pos        (0U)
7866 #define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                /*!< 0x00000001 */
7867 #define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7868 #define TIM_AF1_BKCMP1E_Pos      (1U)
7869 #define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7870 #define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7871 #define TIM_AF1_BKCMP2E_Pos      (2U)
7872 #define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7873 #define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7874 #define TIM_AF1_BKINP_Pos        (9U)
7875 #define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                /*!< 0x00000200 */
7876 #define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7877 #define TIM_AF1_BKCMP1P_Pos      (10U)
7878 #define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7879 #define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7880 #define TIM_AF1_BKCMP2P_Pos      (11U)
7881 #define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7882 #define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7883 
7884 #define TIM_AF1_ETRSEL_Pos       (14U)
7885 #define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7886 #define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
7887 #define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7888 #define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7889 #define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7890 #define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7891 
7892 /*******************  Bit definition for TIM_AF2 register  *******************/
7893 #define TIM_AF2_BK2INE_Pos       (0U)
7894 #define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)               /*!< 0x00000001 */
7895 #define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
7896 #define TIM_AF2_BK2CMP1E_Pos     (1U)
7897 #define TIM_AF2_BK2CMP1E_Msk     (0x1UL << TIM_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
7898 #define TIM_AF2_BK2CMP1E         TIM_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
7899 #define TIM_AF2_BK2CMP2E_Pos     (2U)
7900 #define TIM_AF2_BK2CMP2E_Msk     (0x1UL << TIM_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
7901 #define TIM_AF2_BK2CMP2E         TIM_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
7902 #define TIM_AF2_BK2INP_Pos       (9U)
7903 #define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)               /*!< 0x00000200 */
7904 #define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
7905 #define TIM_AF2_BK2CMP1P_Pos     (10U)
7906 #define TIM_AF2_BK2CMP1P_Msk     (0x1UL << TIM_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
7907 #define TIM_AF2_BK2CMP1P         TIM_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
7908 #define TIM_AF2_BK2CMP2P_Pos     (11U)
7909 #define TIM_AF2_BK2CMP2P_Msk     (0x1UL << TIM_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
7910 #define TIM_AF2_BK2CMP2P         TIM_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
7911 
7912 /*******************  Bit definition for TIM_TISEL register  *********************/
7913 #define TIM_TISEL_TI1SEL_Pos      (0U)
7914 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
7915 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
7916 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
7917 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
7918 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
7919 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
7920 
7921 #define TIM_TISEL_TI2SEL_Pos      (8U)
7922 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
7923 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
7924 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
7925 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
7926 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
7927 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
7928 
7929 #define TIM_TISEL_TI3SEL_Pos      (16U)
7930 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
7931 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
7932 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
7933 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
7934 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
7935 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
7936 
7937 #define TIM_TISEL_TI4SEL_Pos      (24U)
7938 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
7939 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
7940 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
7941 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
7942 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
7943 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
7944 
7945 /******************************************************************************/
7946 /*                                                                            */
7947 /*                         Low Power Timer (LPTIM)                            */
7948 /*                                                                            */
7949 /******************************************************************************/
7950 /******************  Bit definition for LPTIM_ISR register  *******************/
7951 #define LPTIM_ISR_CC1IF_Pos         (0U)
7952 #define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
7953 #define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
7954 #define LPTIM_ISR_ARRM_Pos          (1U)
7955 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
7956 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
7957 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
7958 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
7959 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
7960 #define LPTIM_ISR_CMP1OK_Pos        (3U)
7961 #define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
7962 #define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
7963 #define LPTIM_ISR_ARROK_Pos         (4U)
7964 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
7965 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
7966 #define LPTIM_ISR_UP_Pos            (5U)
7967 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
7968 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
7969 #define LPTIM_ISR_DOWN_Pos          (6U)
7970 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
7971 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
7972 #define LPTIM_ISR_UE_Pos            (7U)
7973 #define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
7974 #define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event */
7975 #define LPTIM_ISR_REPOK_Pos         (8U)
7976 #define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
7977 #define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
7978 #define LPTIM_ISR_CC2IF_Pos         (9U)
7979 #define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
7980 #define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
7981 #define LPTIM_ISR_CC3IF_Pos         (10U)
7982 #define LPTIM_ISR_CC3IF_Msk         (0x1UL << LPTIM_ISR_CC3IF_Pos)             /*!< 0x00000400 */
7983 #define LPTIM_ISR_CC3IF             LPTIM_ISR_CC3IF_Msk                        /*!< Capture/Compare 3 interrupt flag */
7984 #define LPTIM_ISR_CC4IF_Pos         (11U)
7985 #define LPTIM_ISR_CC4IF_Msk         (0x1UL << LPTIM_ISR_CC4IF_Pos)             /*!< 0x00000800 */
7986 #define LPTIM_ISR_CC4IF             LPTIM_ISR_CC4IF_Msk                        /*!< Capture/Compare 4 interrupt flag */
7987 #define LPTIM_ISR_CC1OF_Pos         (12U)
7988 #define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)            /*!< 0x00001000 */
7989 #define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                       /*!< Capture/Compare 1 over-capture flag */
7990 #define LPTIM_ISR_CC2OF_Pos         (13U)
7991 #define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)            /*!< 0x00002000 */
7992 #define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                       /*!< Capture/Compare 2 over-capture flag */
7993 #define LPTIM_ISR_CC3OF_Pos         (14U)
7994 #define LPTIM_ISR_CC3OF_Msk         (0x1UL << LPTIM_ISR_CC3OF_Pos)            /*!< 0x00004000 */
7995 #define LPTIM_ISR_CC3OF             LPTIM_ISR_CC3OF_Msk                       /*!< Capture/Compare 3 over-capture flag */
7996 #define LPTIM_ISR_CC4OF_Pos         (15U)
7997 #define LPTIM_ISR_CC4OF_Msk         (0x1UL << LPTIM_ISR_CC4OF_Pos)            /*!< 0x00008000 */
7998 #define LPTIM_ISR_CC4OF             LPTIM_ISR_CC4OF_Msk                       /*!< Capture/Compare 4 over-capture flag */
7999 #define LPTIM_ISR_CMP2OK_Pos        (19U)
8000 #define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)          /*!< 0x00080000 */
8001 #define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                     /*!< Compare register 2 update OK */
8002 #define LPTIM_ISR_CMP3OK_Pos        (20U)
8003 #define LPTIM_ISR_CMP3OK_Msk        (0x1UL << LPTIM_ISR_CMP3OK_Pos)          /*!< 0x00100000 */
8004 #define LPTIM_ISR_CMP3OK            LPTIM_ISR_CMP3OK_Msk                     /*!< Compare register 3 update OK */
8005 #define LPTIM_ISR_CMP4OK_Pos        (21U)
8006 #define LPTIM_ISR_CMP4OK_Msk        (0x1UL << LPTIM_ISR_CMP4OK_Pos)          /*!< 0x00200000 */
8007 #define LPTIM_ISR_CMP4OK            LPTIM_ISR_CMP4OK_Msk                     /*!< Compare register 4 update OK */
8008 #define LPTIM_ISR_DIEROK_Pos        (24U)
8009 #define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)          /*!< 0x01000000 */
8010 #define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                     /*!< DMA & interrupt enable update OK */
8011 
8012 /******************  Bit definition for LPTIM_ICR register  *******************/
8013 #define LPTIM_ICR_CC1CF_Pos         (0U)
8014 #define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
8015 #define LPTIM_ICR_CC1CF             LPTIM_ICR_CC1CF_Msk                        /*!< Capture/Compare 1 clear flag  */
8016 #define LPTIM_ICR_ARRMCF_Pos        (1U)
8017 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
8018 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match clear flag */
8019 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
8020 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
8021 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event clear flag */
8022 #define LPTIM_ICR_CMP1OKCF_Pos      (3U)
8023 #define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
8024 #define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
8025 #define LPTIM_ICR_ARROKCF_Pos       (4U)
8026 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
8027 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK clear flag */
8028 #define LPTIM_ICR_UPCF_Pos          (5U)
8029 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
8030 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up clear flag */
8031 #define LPTIM_ICR_DOWNCF_Pos        (6U)
8032 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
8033 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down clear flag */
8034 #define LPTIM_ICR_UECF_Pos          (7U)
8035 #define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
8036 #define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event clear flag */
8037 #define LPTIM_ICR_REPOKCF_Pos       (8U)
8038 #define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
8039 #define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK clear flag */
8040 #define LPTIM_ICR_CC2CF_Pos         (9U)
8041 #define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
8042 #define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
8043 #define LPTIM_ICR_CC3CF_Pos         (10U)
8044 #define LPTIM_ICR_CC3CF_Msk         (0x1UL << LPTIM_ICR_CC3CF_Pos)             /*!< 0x00000400 */
8045 #define LPTIM_ICR_CC3CF             LPTIM_ICR_CC3CF_Msk                        /*!< Capture/Compare 3 clear flag  */
8046 #define LPTIM_ICR_CC4CF_Pos         (11U)
8047 #define LPTIM_ICR_CC4CF_Msk         (0x1UL << LPTIM_ICR_CC4CF_Pos)             /*!< 0x00000800 */
8048 #define LPTIM_ICR_CC4CF             LPTIM_ICR_CC4CF_Msk                        /*!< Capture/Compare 4 clear flag  */
8049 #define LPTIM_ICR_CC1OCF_Pos        (12U)
8050 #define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
8051 #define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
8052 #define LPTIM_ICR_CC2OCF_Pos        (13U)
8053 #define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
8054 #define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
8055 #define LPTIM_ICR_CC3OCF_Pos        (14U)
8056 #define LPTIM_ICR_CC3OCF_Msk        (0x1UL << LPTIM_ICR_CC3OCF_Pos)            /*!< 0x00004000 */
8057 #define LPTIM_ICR_CC3OCF            LPTIM_ICR_CC3OCF_Msk                       /*!< Capture/Compare 3 over-capture clear flag */
8058 #define LPTIM_ICR_CC4OCF_Pos        (15U)
8059 #define LPTIM_ICR_CC4OCF_Msk        (0x1UL << LPTIM_ICR_CC4OCF_Pos)            /*!< 0x00008000 */
8060 #define LPTIM_ICR_CC4OCF            LPTIM_ICR_CC4OCF_Msk                       /*!< Capture/Compare 4 over-capture clear flag */
8061 #define LPTIM_ICR_CMP2OKCF_Pos      (19U)
8062 #define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
8063 #define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
8064 #define LPTIM_ICR_CMP3OKCF_Pos      (20U)
8065 #define LPTIM_ICR_CMP3OKCF_Msk      (0x1UL << LPTIM_ICR_CMP3OKCF_Pos)          /*!< 0x00100000 */
8066 #define LPTIM_ICR_CMP3OKCF          LPTIM_ICR_CMP3OKCF_Msk                     /*!< Compare register 3 update OK clear flag */
8067 #define LPTIM_ICR_CMP4OKCF_Pos      (21U)
8068 #define LPTIM_ICR_CMP4OKCF_Msk      (0x1UL << LPTIM_ICR_CMP4OKCF_Pos)          /*!< 0x00200000 */
8069 #define LPTIM_ICR_CMP4OKCF          LPTIM_ICR_CMP4OKCF_Msk                     /*!< Compare register 4 update OK clear flag */
8070 #define LPTIM_ICR_DIEROKCF_Pos      (24U)
8071 #define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
8072 #define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< DMA & interrupt enable update OK clear flag */
8073 
8074 /******************  Bit definition for LPTIM_DIER register *******************/
8075 #define LPTIM_DIER_CC1IE_Pos         (0U)
8076 #define LPTIM_DIER_CC1IE_Msk         (0x1UL << LPTIM_DIER_CC1IE_Pos)           /*!< 0x00000001 */
8077 #define LPTIM_DIER_CC1IE             LPTIM_DIER_CC1IE_Msk                      /*!< Compare/Compare 1 interrupt enable */
8078 #define LPTIM_DIER_ARRMIE_Pos        (1U)
8079 #define LPTIM_DIER_ARRMIE_Msk        (0x1UL << LPTIM_DIER_ARRMIE_Pos)          /*!< 0x00000002 */
8080 #define LPTIM_DIER_ARRMIE            LPTIM_DIER_ARRMIE_Msk                     /*!< Autoreload match interrupt enable */
8081 #define LPTIM_DIER_EXTTRIGIE_Pos     (2U)
8082 #define LPTIM_DIER_EXTTRIGIE_Msk     (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)       /*!< 0x00000004 */
8083 #define LPTIM_DIER_EXTTRIGIE         LPTIM_DIER_EXTTRIGIE_Msk                  /*!< External trigger edge event interrupt enable */
8084 #define LPTIM_DIER_CMP1OKIE_Pos      (3U)
8085 #define LPTIM_DIER_CMP1OKIE_Msk      (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)        /*!< 0x00000008 */
8086 #define LPTIM_DIER_CMP1OKIE          LPTIM_DIER_CMP1OKIE_Msk                   /*!< Compare register 1 update OK interrupt enable */
8087 #define LPTIM_DIER_ARROKIE_Pos       (4U)
8088 #define LPTIM_DIER_ARROKIE_Msk       (0x1UL << LPTIM_DIER_ARROKIE_Pos)         /*!< 0x00000010 */
8089 #define LPTIM_DIER_ARROKIE           LPTIM_DIER_ARROKIE_Msk                    /*!< Autoreload register update OK interrupt enable */
8090 #define LPTIM_DIER_UPIE_Pos          (5U)
8091 #define LPTIM_DIER_UPIE_Msk          (0x1UL << LPTIM_DIER_UPIE_Pos)            /*!< 0x00000020 */
8092 #define LPTIM_DIER_UPIE              LPTIM_DIER_UPIE_Msk                       /*!< Counter direction change down to up interrupt enable */
8093 #define LPTIM_DIER_DOWNIE_Pos        (6U)
8094 #define LPTIM_DIER_DOWNIE_Msk        (0x1UL << LPTIM_DIER_DOWNIE_Pos)          /*!< 0x00000040 */
8095 #define LPTIM_DIER_DOWNIE            LPTIM_DIER_DOWNIE_Msk                     /*!< Counter direction change up to down interrupt enable */
8096 #define LPTIM_DIER_UEIE_Pos          (7U)
8097 #define LPTIM_DIER_UEIE_Msk          (0x1UL << LPTIM_DIER_UEIE_Pos)            /*!< 0x00000080 */
8098 #define LPTIM_DIER_UEIE              LPTIM_DIER_UEIE_Msk                       /*!< Update event interrupt enable */
8099 #define LPTIM_DIER_REPOKIE_Pos       (8U)
8100 #define LPTIM_DIER_REPOKIE_Msk       (0x1UL << LPTIM_DIER_REPOKIE_Pos)         /*!< 0x00000100 */
8101 #define LPTIM_DIER_REPOKIE           LPTIM_DIER_REPOKIE_Msk                    /*!< Repetition register update OK interrupt enable */
8102 #define LPTIM_DIER_CC2IE_Pos         (9U)
8103 #define LPTIM_DIER_CC2IE_Msk         (0x1UL << LPTIM_DIER_CC2IE_Pos)           /*!< 0x00000200 */
8104 #define LPTIM_DIER_CC2IE             LPTIM_DIER_CC2IE_Msk                      /*!< Capture/Compare 2 interrupt interrupt enable */
8105 #define LPTIM_DIER_CC3IE_Pos         (10U)
8106 #define LPTIM_DIER_CC3IE_Msk         (0x1UL << LPTIM_DIER_CC3IE_Pos)           /*!< 0x00000400 */
8107 #define LPTIM_DIER_CC3IE             LPTIM_DIER_CC3IE_Msk                      /*!< Capture/Compare 3 interrupt interrupt enable */
8108 #define LPTIM_DIER_CC4IE_Pos         (11U)
8109 #define LPTIM_DIER_CC4IE_Msk         (0x1UL << LPTIM_DIER_CC4IE_Pos)           /*!< 0x00000800 */
8110 #define LPTIM_DIER_CC4IE             LPTIM_DIER_CC4IE_Msk                      /*!< Capture/Compare 4 interrupt interrupt enable */
8111 #define LPTIM_DIER_CC1OIE_Pos        (12U)
8112 #define LPTIM_DIER_CC1OIE_Msk        (0x1UL << LPTIM_DIER_CC1OIE_Pos)          /*!< 0x00001000 */
8113 #define LPTIM_DIER_CC1OIE            LPTIM_DIER_CC1OIE_Msk                     /*!< Capture/Compare 1 over-capture interrupt enable */
8114 #define LPTIM_DIER_CC2OIE_Pos        (13U)
8115 #define LPTIM_DIER_CC2OIE_Msk        (0x1UL << LPTIM_DIER_CC2OIE_Pos)          /*!< 0x00002000 */
8116 #define LPTIM_DIER_CC2OIE            LPTIM_DIER_CC2OIE_Msk                     /*!< Capture/Compare 2 over-capture interrupt enable */
8117 #define LPTIM_DIER_CC3OIE_Pos        (14U)
8118 #define LPTIM_DIER_CC3OIE_Msk        (0x1UL << LPTIM_DIER_CC3OIE_Pos)          /*!< 0x00004000 */
8119 #define LPTIM_DIER_CC3OIE            LPTIM_DIER_CC3OIE_Msk                     /*!< Capture/Compare 3 over-capture interrupt enable */
8120 #define LPTIM_DIER_CC4OIE_Pos        (15U)
8121 #define LPTIM_DIER_CC4OIE_Msk        (0x1UL << LPTIM_DIER_CC4OIE_Pos)          /*!< 0x00008000 */
8122 #define LPTIM_DIER_CC4OIE            LPTIM_DIER_CC4OIE_Msk                     /*!< Capture/Compare 4 over-capture interrupt enable */
8123 #define LPTIM_DIER_CC1DE_Pos         (16U)
8124 #define LPTIM_DIER_CC1DE_Msk         (0x1UL << LPTIM_DIER_CC1DE_Pos)           /*!< 0x00010000 */
8125 #define LPTIM_DIER_CC1DE             LPTIM_DIER_CC1DE_Msk                      /*!< Capture/Compare 1 DMA request enable */
8126 #define LPTIM_DIER_CMP2OKIE_Pos      (19U)
8127 #define LPTIM_DIER_CMP2OKIE_Msk      (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)        /*!< 0x00080000 */
8128 #define LPTIM_DIER_CMP2OKIE          LPTIM_DIER_CMP2OKIE_Msk                   /*!< Compare register 2 update OK interrupt enable */
8129 #define LPTIM_DIER_CMP3OKIE_Pos      (20U)
8130 #define LPTIM_DIER_CMP3OKIE_Msk      (0x1UL << LPTIM_DIER_CMP3OKIE_Pos)        /*!< 0x00100000 */
8131 #define LPTIM_DIER_CMP3OKIE          LPTIM_DIER_CMP3OKIE_Msk                   /*!< Compare register 3 update OK interrupt enable */
8132 #define LPTIM_DIER_CMP4OKIE_Pos      (21U)
8133 #define LPTIM_DIER_CMP4OKIE_Msk      (0x1UL << LPTIM_DIER_CMP4OKIE_Pos)        /*!< 0x00200000 */
8134 #define LPTIM_DIER_CMP4OKIE          LPTIM_DIER_CMP4OKIE_Msk                   /*!< Compare register 4 update OK interrupt enable */
8135 #define LPTIM_DIER_UEDE_Pos          (23U)
8136 #define LPTIM_DIER_UEDE_Msk          (0x1UL << LPTIM_DIER_UEDE_Pos)            /*!< 0x00800000 */
8137 #define LPTIM_DIER_UEDE              LPTIM_DIER_UEDE_Msk                       /*!< Update event DMA request enable */
8138 #define LPTIM_DIER_CC2DE_Pos         (25U)
8139 #define LPTIM_DIER_CC2DE_Msk         (0x1UL << LPTIM_DIER_CC2DE_Pos)           /*!< 0x02000000 */
8140 #define LPTIM_DIER_CC2DE             LPTIM_DIER_CC2DE_Msk                      /*!< Capture/Compare 2 DMA request enable */
8141 #define LPTIM_DIER_CC3DE_Pos         (26U)
8142 #define LPTIM_DIER_CC3DE_Msk         (0x1UL << LPTIM_DIER_CC3DE_Pos)           /*!< 0x04000000 */
8143 #define LPTIM_DIER_CC3DE             LPTIM_DIER_CC3DE_Msk                      /*!< Capture/Compare 3 DMA request enable */
8144 #define LPTIM_DIER_CC4DE_Pos         (27U)
8145 #define LPTIM_DIER_CC4DE_Msk         (0x1UL << LPTIM_DIER_CC4DE_Pos)           /*!< 0x08000000 */
8146 #define LPTIM_DIER_CC4DE             LPTIM_DIER_CC4DE_Msk                      /*!< Capture/Compare 4 DMA request enable */
8147 
8148 /******************  Bit definition for LPTIM_CFGR register *******************/
8149 #define LPTIM_CFGR_CKSEL_Pos        (0U)
8150 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
8151 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
8152 #define LPTIM_CFGR_CKPOL_Pos        (1U)
8153 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
8154 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
8155 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
8156 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
8157 #define LPTIM_CFGR_CKFLT_Pos        (3U)
8158 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
8159 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
8160 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
8161 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
8162 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
8163 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
8164 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
8165 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
8166 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
8167 #define LPTIM_CFGR_PRESC_Pos        (9U)
8168 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
8169 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
8170 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
8171 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
8172 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
8173 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
8174 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
8175 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
8176 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
8177 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
8178 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
8179 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
8180 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
8181 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
8182 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
8183 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
8184 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
8185 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
8186 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
8187 #define LPTIM_CFGR_WAVE_Pos         (20U)
8188 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
8189 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
8190 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
8191 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
8192 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape */
8193 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
8194 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
8195 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
8196 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
8197 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
8198 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
8199 #define LPTIM_CFGR_ENC_Pos          (24U)
8200 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
8201 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
8202 
8203 /******************  Bit definition for LPTIM_CR register  ********************/
8204 #define LPTIM_CR_ENABLE_Pos         (0U)
8205 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
8206 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
8207 #define LPTIM_CR_SNGSTRT_Pos        (1U)
8208 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
8209 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
8210 #define LPTIM_CR_CNTSTRT_Pos        (2U)
8211 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
8212 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
8213 #define LPTIM_CR_COUNTRST_Pos       (3U)
8214 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
8215 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
8216 #define LPTIM_CR_RSTARE_Pos         (4U)
8217 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
8218 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
8219 
8220 /******************  Bit definition for LPTIM_CCR1 register  ******************/
8221 #define LPTIM_CCR1_CCR1_Pos         (0U)
8222 #define LPTIM_CCR1_CCR1_Msk         (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)          /*!< 0x0000FFFF */
8223 #define LPTIM_CCR1_CCR1             LPTIM_CCR1_CCR1_Msk                        /*!< Compare register 1 */
8224 
8225 /******************  Bit definition for LPTIM_ARR register  *******************/
8226 #define LPTIM_ARR_ARR_Pos           (0U)
8227 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
8228 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
8229 
8230 /******************  Bit definition for LPTIM_CNT register  *******************/
8231 #define LPTIM_CNT_CNT_Pos           (0U)
8232 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
8233 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
8234 
8235 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
8236 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
8237 #define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
8238 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
8239 #define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
8240 #define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
8241 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
8242 #define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
8243 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
8244 #define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
8245 #define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
8246 #define LPTIM_CFGR2_IC1SEL_Pos      (16U)
8247 #define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00030000 */
8248 #define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
8249 #define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
8250 #define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
8251 #define LPTIM_CFGR2_IC2SEL_Pos      (20U)
8252 #define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00300000 */
8253 #define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
8254 #define LPTIM_CFGR2_IC2SEL_0        (0x1U << LPTIM_CFGR2_IC2SEL_Pos)           /*!< 0x00100000 */
8255 #define LPTIM_CFGR2_IC2SEL_1        (0x2U << LPTIM_CFGR2_IC2SEL_Pos)           /*!< 0x00200000 */
8256 #define LPTIM_CFGR2_IC3SEL_Pos      (24U)
8257 #define LPTIM_CFGR2_IC3SEL_Msk      (0x3UL << LPTIM_CFGR2_IC3SEL_Pos)          /*!< 0x03000000 */
8258 #define LPTIM_CFGR2_IC3SEL          LPTIM_CFGR2_IC3SEL_Msk                     /*!< IC3SEL[25:24] bits */
8259 #define LPTIM_CFGR2_IC3SEL_0        (0x1U << LPTIM_CFGR2_IC3SEL_Pos)           /*!< 0x01000000 */
8260 #define LPTIM_CFGR2_IC3SEL_1        (0x2U << LPTIM_CFGR2_IC3SEL_Pos)           /*!< 0x02000000 */
8261 #define LPTIM_CFGR2_IC4SEL_Pos      (28U)
8262 #define LPTIM_CFGR2_IC4SEL_Msk      (0x3UL << LPTIM_CFGR2_IC4SEL_Pos)          /*!< 0x30000000 */
8263 #define LPTIM_CFGR2_IC4SEL          LPTIM_CFGR2_IC4SEL_Msk                     /*!< IC4SEL[29:28] bits */
8264 #define LPTIM_CFGR2_IC4SEL_0        (0x1U << LPTIM_CFGR2_IC4SEL_Pos)           /*!< 0x10000000 */
8265 #define LPTIM_CFGR2_IC4SEL_1        (0x2U << LPTIM_CFGR2_IC4SEL_Pos)           /*!< 0x20000000 */
8266 
8267 /******************  Bit definition for LPTIM_RCR register  *******************/
8268 #define LPTIM_RCR_REP_Pos           (0U)
8269 #define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
8270 #define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition register value */
8271 
8272 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
8273 #define LPTIM_CCMR1_CC1SEL_Pos      (0U)
8274 #define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)           /*!< 0x00000001 */
8275 #define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                      /*!< Capture/Compare 1 selection */
8276 #define LPTIM_CCMR1_CC1E_Pos        (1U)
8277 #define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)             /*!< 0x00000002 */
8278 #define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                        /*!< Capture/Compare 1 output enable */
8279 #define LPTIM_CCMR1_CC1P_Pos        (2U)
8280 #define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)             /*!< 0x0000000C */
8281 #define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                        /*!< Capture/Compare 1 output polarity */
8282 #define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)             /*!< 0x00000004 */
8283 #define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)             /*!< 0x00000008 */
8284 #define LPTIM_CCMR1_IC1PSC_Pos      (8U)
8285 #define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)           /*!< 0x00000300 */
8286 #define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                      /*!< Input capture 1 prescaler */
8287 #define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)           /*!< 0x00000100 */
8288 #define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)           /*!< 0x00000200 */
8289 #define LPTIM_CCMR1_IC1F_Pos        (12U)
8290 #define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)             /*!< 0x00003000 */
8291 #define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                        /*!< Input capture 1 filter */
8292 #define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)             /*!< 0x00001000 */
8293 #define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)             /*!< 0x00002000 */
8294 #define LPTIM_CCMR1_CC2SEL_Pos      (16U)
8295 #define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)           /*!< 0x00010000 */
8296 #define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                      /*!< Capture/Compare 2 selection */
8297 #define LPTIM_CCMR1_CC2E_Pos        (17U)
8298 #define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)             /*!< 0x00020000 */
8299 #define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                        /*!< Capture/Compare 2 output enable */
8300 #define LPTIM_CCMR1_CC2P_Pos        (18U)
8301 #define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)             /*!< 0x000C0000 */
8302 #define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                        /*!< Capture/Compare 2 output polarity */
8303 #define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)             /*!< 0x00040000 */
8304 #define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)             /*!< 0x00080000 */
8305 #define LPTIM_CCMR1_IC2PSC_Pos      (24U)
8306 #define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)           /*!< 0x03000000 */
8307 #define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                      /*!< Input capture 2 prescaler */
8308 #define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)           /*!< 0x01000000 */
8309 #define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)           /*!< 0x02000000 */
8310 #define LPTIM_CCMR1_IC2F_Pos        (28U)
8311 #define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)             /*!< 0x30000000 */
8312 #define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                        /*!< Input capture 2 filter */
8313 #define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)             /*!< 0x10000000 */
8314 #define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)             /*!< 0x20000000 */
8315 
8316 /*****************  Bit definition for LPTIM_CCMR2 register  ******************/
8317 #define LPTIM_CCMR2_CC3SEL_Pos      (0U)
8318 #define LPTIM_CCMR2_CC3SEL_Msk      (0x1UL << LPTIM_CCMR2_CC3SEL_Pos)           /*!< 0x00000001 */
8319 #define LPTIM_CCMR2_CC3SEL          LPTIM_CCMR2_CC3SEL_Msk                      /*!< Capture/Compare 3 selection */
8320 #define LPTIM_CCMR2_CC3E_Pos        (1U)
8321 #define LPTIM_CCMR2_CC3E_Msk        (0x1UL << LPTIM_CCMR2_CC3E_Pos)             /*!< 0x00000002 */
8322 #define LPTIM_CCMR2_CC3E            LPTIM_CCMR2_CC3E_Msk                        /*!< Capture/Compare 3 output enable */
8323 #define LPTIM_CCMR2_CC3P_Pos        (2U)
8324 #define LPTIM_CCMR2_CC3P_Msk        (0x3UL << LPTIM_CCMR2_CC3P_Pos)             /*!< 0x0000000C */
8325 #define LPTIM_CCMR2_CC3P            LPTIM_CCMR2_CC3P_Msk                        /*!< Capture/Compare 3 output polarity */
8326 #define LPTIM_CCMR2_CC3P_0          (0x1UL << LPTIM_CCMR2_CC3P_Pos)             /*!< 0x00000004 */
8327 #define LPTIM_CCMR2_CC3P_1          (0x2UL << LPTIM_CCMR2_CC3P_Pos)             /*!< 0x00000008 */
8328 #define LPTIM_CCMR2_IC3PSC_Pos      (8U)
8329 #define LPTIM_CCMR2_IC3PSC_Msk      (0x3UL << LPTIM_CCMR2_IC3PSC_Pos)           /*!< 0x00000300 */
8330 #define LPTIM_CCMR2_IC3PSC          LPTIM_CCMR2_IC3PSC_Msk                      /*!< Input capture 3 prescaler */
8331 #define LPTIM_CCMR2_IC3PSC_0        (0x1UL << LPTIM_CCMR2_IC3PSC_Pos)           /*!< 0x00000100 */
8332 #define LPTIM_CCMR2_IC3PSC_1        (0x2UL << LPTIM_CCMR2_IC3PSC_Pos)           /*!< 0x00000200 */
8333 #define LPTIM_CCMR2_IC3F_Pos        (12U)
8334 #define LPTIM_CCMR2_IC3F_Msk        (0x3UL << LPTIM_CCMR2_IC3F_Pos)             /*!< 0x00003000 */
8335 #define LPTIM_CCMR2_IC3F            LPTIM_CCMR2_IC3F_Msk                        /*!< Input capture 3 filter */
8336 #define LPTIM_CCMR2_IC3F_0          (0x1UL << LPTIM_CCMR2_IC3F_Pos)             /*!< 0x00001000 */
8337 #define LPTIM_CCMR2_IC3F_1          (0x2UL << LPTIM_CCMR2_IC3F_Pos)             /*!< 0x00002000 */
8338 #define LPTIM_CCMR2_CC4SEL_Pos      (16U)
8339 #define LPTIM_CCMR2_CC4SEL_Msk      (0x1UL << LPTIM_CCMR2_CC4SEL_Pos)           /*!< 0x00010000 */
8340 #define LPTIM_CCMR2_CC4SEL          LPTIM_CCMR2_CC4SEL_Msk                      /*!< Capture/Compare 4 selection */
8341 #define LPTIM_CCMR2_CC4E_Pos        (17U)
8342 #define LPTIM_CCMR2_CC4E_Msk        (0x1UL << LPTIM_CCMR2_CC4E_Pos)             /*!< 0x00020000 */
8343 #define LPTIM_CCMR2_CC4E            LPTIM_CCMR2_CC4E_Msk                        /*!< Capture/Compare 4 output enable */
8344 #define LPTIM_CCMR2_CC4P_Pos        (18U)
8345 #define LPTIM_CCMR2_CC4P_Msk        (0x3UL << LPTIM_CCMR2_CC4P_Pos)             /*!< 0x000C0000 */
8346 #define LPTIM_CCMR2_CC4P            LPTIM_CCMR2_CC4P_Msk                        /*!< Capture/Compare 4 output polarity */
8347 #define LPTIM_CCMR2_CC4P_0          (0x1UL << LPTIM_CCMR2_CC4P_Pos)             /*!< 0x00040000 */
8348 #define LPTIM_CCMR2_CC4P_1          (0x2UL << LPTIM_CCMR2_CC4P_Pos)             /*!< 0x00080000 */
8349 #define LPTIM_CCMR2_IC4PSC_Pos      (24U)
8350 #define LPTIM_CCMR2_IC4PSC_Msk      (0x3UL << LPTIM_CCMR2_IC4PSC_Pos)           /*!< 0x03000000 */
8351 #define LPTIM_CCMR2_IC4PSC          LPTIM_CCMR2_IC4PSC_Msk                      /*!< Input capture 4 prescaler */
8352 #define LPTIM_CCMR2_IC4PSC_0        (0x1UL << LPTIM_CCMR2_IC4PSC_Pos)           /*!< 0x01000000 */
8353 #define LPTIM_CCMR2_IC4PSC_1        (0x2UL << LPTIM_CCMR2_IC4PSC_Pos)           /*!< 0x02000000 */
8354 #define LPTIM_CCMR2_IC4F_Pos        (28U)
8355 #define LPTIM_CCMR2_IC4F_Msk        (0x3UL << LPTIM_CCMR2_IC4F_Pos)             /*!< 0x30000000 */
8356 #define LPTIM_CCMR2_IC4F            LPTIM_CCMR2_IC4F_Msk                        /*!< Input capture 4 filter */
8357 #define LPTIM_CCMR2_IC4F_0          (0x1UL << LPTIM_CCMR2_IC4F_Pos)             /*!< 0x10000000 */
8358 #define LPTIM_CCMR2_IC4F_1          (0x2UL << LPTIM_CCMR2_IC4F_Pos)             /*!< 0x20000000 */
8359 
8360 /******************  Bit definition for LPTIM_CCR2 register  ******************/
8361 #define LPTIM_CCR2_CCR2_Pos         (0U)
8362 #define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)          /*!< 0x0000FFFF */
8363 #define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                        /*!< Compare register 2 */
8364 
8365 /******************  Bit definition for LPTIM_CCR3 register  ******************/
8366 #define LPTIM_CCR3_CCR3_Pos         (0U)
8367 #define LPTIM_CCR3_CCR3_Msk         (0xFFFFUL << LPTIM_CCR3_CCR3_Pos)          /*!< 0x0000FFFF */
8368 #define LPTIM_CCR3_CCR3             LPTIM_CCR3_CCR3_Msk                        /*!< Compare register 3 */
8369 
8370 /******************  Bit definition for LPTIM_CCR4 register  ******************/
8371 #define LPTIM_CCR4_CCR4_Pos         (0U)
8372 #define LPTIM_CCR4_CCR4_Msk         (0xFFFFUL << LPTIM_CCR4_CCR4_Pos)          /*!< 0x0000FFFF */
8373 #define LPTIM_CCR4_CCR4             LPTIM_CCR4_CCR4_Msk                        /*!< Compare register 4 */
8374 
8375 /******************************************************************************/
8376 /*                                                                            */
8377 /*                      Analog Comparators (COMP)                             */
8378 /*                                                                            */
8379 /******************************************************************************/
8380 
8381 /******************  Bit definition for COMPx_CSR register  *******************/
8382 #define COMP_CSR_EN_Pos                (0U)
8383 #define COMP_CSR_EN_Msk                (0x1UL << COMP_CSR_EN_Pos)              /*!< 0x00000001 */
8384 #define COMP_CSR_EN                    COMP_CSR_EN_Msk                         /*!< COMPx enable bit */
8385 #define COMP_CSR_INMSEL_Pos            (4U)
8386 #define COMP_CSR_INMSEL_Msk            (0xFUL << COMP_CSR_INMSEL_Pos)          /*!< 0x000000F0 */
8387 #define COMP_CSR_INMSEL                COMP_CSR_INMSEL_Msk                     /*!< COMPx input minus selection bit  */
8388 #define COMP_CSR_INMSEL_0              (0x1UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000010 */
8389 #define COMP_CSR_INMSEL_1              (0x2UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000020 */
8390 #define COMP_CSR_INMSEL_2              (0x4UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000040 */
8391 #define COMP_CSR_INMSEL_3              (0x8UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000080 */
8392 #define COMP_CSR_INPSEL_Pos            (8U)
8393 #define COMP_CSR_INPSEL_Msk            (0x7UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000700 */
8394 #define COMP_CSR_INPSEL                COMP_CSR_INPSEL_Msk                     /*!< COMPx input plus selection bit */
8395 #define COMP_CSR_INPSEL_0              (0x1UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000100 */
8396 #define COMP_CSR_INPSEL_1              (0x2UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000200 */
8397 #define COMP_CSR_INPSEL_2              (0x4UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000400 */
8398 #define COMP_CSR_WINMODE_Pos           (11U)
8399 #define COMP_CSR_WINMODE_Msk           (0x1UL << COMP_CSR_WINMODE_Pos)         /*!< 0x00000800 */
8400 #define COMP_CSR_WINMODE               COMP_CSR_WINMODE_Msk                    /*!< COMPx Windows mode selection bit */
8401 #define COMP_CSR_WINOUT_Pos            (14U)
8402 #define COMP_CSR_WINOUT_Msk            (0x1UL << COMP_CSR_WINOUT_Pos)          /*!< 0x00004000 */
8403 #define COMP_CSR_WINOUT                COMP_CSR_WINOUT_Msk                     /*!< COMPx polarity selection bit */
8404 #define COMP_CSR_POLARITY_Pos          (15U)
8405 #define COMP_CSR_POLARITY_Msk          (0x1UL << COMP_CSR_POLARITY_Pos)        /*!< 0x00008000 */
8406 #define COMP_CSR_POLARITY              COMP_CSR_POLARITY_Msk                   /*!< COMPx polarity selection bit */
8407 #define COMP_CSR_HYST_Pos              (16U)
8408 #define COMP_CSR_HYST_Msk              (0x3UL << COMP_CSR_HYST_Pos)            /*!< 0x00030000 */
8409 #define COMP_CSR_HYST                  COMP_CSR_HYST_Msk                       /*!< COMPx hysteresis selection bits */
8410 #define COMP_CSR_HYST_0                (0x1UL << COMP_CSR_HYST_Pos)            /*!< 0x00010000 */
8411 #define COMP_CSR_HYST_1                (0x2UL << COMP_CSR_HYST_Pos)            /*!< 0x00020000 */
8412 #define COMP_CSR_PWRMODE_Pos           (18U)
8413 #define COMP_CSR_PWRMODE_Msk           (0x3UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x000C0000 */
8414 #define COMP_CSR_PWRMODE               COMP_CSR_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator */
8415 #define COMP_CSR_PWRMODE_0             (0x1UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00010000 */
8416 #define COMP_CSR_PWRMODE_1             (0x2UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00020000 */
8417 #define COMP_CSR_BLANKSEL_Pos          (20U)
8418 #define COMP_CSR_BLANKSEL_Msk          (0x1FUL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01F00000 */
8419 #define COMP_CSR_BLANKSEL              COMP_CSR_BLANKSEL_Msk                   /*!< COMPx blanking source selection bits */
8420 #define COMP_CSR_BLANKSEL_0            (0x1UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00100000 */
8421 #define COMP_CSR_BLANKSEL_1            (0x2UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00200000 */
8422 #define COMP_CSR_BLANKSEL_2            (0x4UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00400000 */
8423 #define COMP_CSR_BLANKSEL_3            (0x8UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x00800000 */
8424 #define COMP_CSR_BLANKSEL_4            (0x10UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01000000 */
8425 #define COMP_CSR_VALUE_Pos             (30U)
8426 #define COMP_CSR_VALUE_Msk             (0x1UL << COMP_CSR_VALUE_Pos)           /*!< 0x04000000 */
8427 #define COMP_CSR_VALUE                 COMP_CSR_VALUE_Msk                      /*!< Comparator output level */
8428 #define COMP_CSR_LOCK_Pos              (31U)
8429 #define COMP_CSR_LOCK_Msk              (0x1UL << COMP_CSR_LOCK_Pos)            /*!< 0x80000000 */
8430 #define COMP_CSR_LOCK                  COMP_CSR_LOCK_Msk                       /*!< COMPx Lock Bit */
8431 
8432 /******************************************************************************/
8433 /*                                                                            */
8434 /*                          Touch Sensing Controller (TSC)                    */
8435 /*                                                                            */
8436 /******************************************************************************/
8437 /*******************  Bit definition for TSC_CR register  *********************/
8438 #define TSC_CR_TSCE_Pos          (0U)
8439 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
8440 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
8441 #define TSC_CR_START_Pos         (1U)
8442 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
8443 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
8444 #define TSC_CR_AM_Pos            (2U)
8445 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
8446 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
8447 #define TSC_CR_SYNCPOL_Pos       (3U)
8448 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
8449 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
8450 #define TSC_CR_IODEF_Pos         (4U)
8451 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
8452 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
8453 
8454 #define TSC_CR_MCV_Pos           (5U)
8455 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
8456 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
8457 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
8458 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
8459 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */
8460 
8461 #define TSC_CR_PGPSC_Pos         (12U)
8462 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
8463 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
8464 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
8465 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
8466 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */
8467 
8468 #define TSC_CR_SSPSC_Pos         (15U)
8469 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
8470 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
8471 #define TSC_CR_SSE_Pos           (16U)
8472 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
8473 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
8474 
8475 #define TSC_CR_SSD_Pos           (17U)
8476 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
8477 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
8478 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
8479 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
8480 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
8481 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
8482 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
8483 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
8484 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */
8485 
8486 #define TSC_CR_CTPL_Pos          (24U)
8487 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
8488 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
8489 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
8490 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
8491 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
8492 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */
8493 
8494 #define TSC_CR_CTPH_Pos          (28U)
8495 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
8496 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
8497 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
8498 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
8499 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
8500 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */
8501 
8502 /*******************  Bit definition for TSC_IER register  ********************/
8503 #define TSC_IER_EOAIE_Pos        (0U)
8504 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
8505 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
8506 #define TSC_IER_MCEIE_Pos        (1U)
8507 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
8508 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
8509 
8510 /*******************  Bit definition for TSC_ICR register  ********************/
8511 #define TSC_ICR_EOAIC_Pos        (0U)
8512 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
8513 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
8514 #define TSC_ICR_MCEIC_Pos        (1U)
8515 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
8516 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
8517 
8518 /*******************  Bit definition for TSC_ISR register  ********************/
8519 #define TSC_ISR_EOAF_Pos         (0U)
8520 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
8521 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
8522 #define TSC_ISR_MCEF_Pos         (1U)
8523 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
8524 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
8525 
8526 /*******************  Bit definition for TSC_IOHCR register  ******************/
8527 #define TSC_IOHCR_G1_IO1_Pos     (0U)
8528 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
8529 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
8530 #define TSC_IOHCR_G1_IO2_Pos     (1U)
8531 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
8532 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
8533 #define TSC_IOHCR_G1_IO3_Pos     (2U)
8534 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
8535 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
8536 #define TSC_IOHCR_G1_IO4_Pos     (3U)
8537 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
8538 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
8539 #define TSC_IOHCR_G2_IO1_Pos     (4U)
8540 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
8541 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
8542 #define TSC_IOHCR_G2_IO2_Pos     (5U)
8543 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
8544 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
8545 #define TSC_IOHCR_G2_IO3_Pos     (6U)
8546 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
8547 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
8548 #define TSC_IOHCR_G2_IO4_Pos     (7U)
8549 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
8550 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
8551 #define TSC_IOHCR_G3_IO1_Pos     (8U)
8552 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
8553 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
8554 #define TSC_IOHCR_G3_IO2_Pos     (9U)
8555 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
8556 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
8557 #define TSC_IOHCR_G3_IO3_Pos     (10U)
8558 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
8559 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
8560 #define TSC_IOHCR_G3_IO4_Pos     (11U)
8561 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
8562 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
8563 #define TSC_IOHCR_G4_IO1_Pos     (12U)
8564 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
8565 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
8566 #define TSC_IOHCR_G4_IO2_Pos     (13U)
8567 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
8568 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
8569 #define TSC_IOHCR_G4_IO3_Pos     (14U)
8570 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
8571 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
8572 #define TSC_IOHCR_G4_IO4_Pos     (15U)
8573 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
8574 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
8575 #define TSC_IOHCR_G5_IO1_Pos     (16U)
8576 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */
8577 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
8578 #define TSC_IOHCR_G5_IO2_Pos     (17U)
8579 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */
8580 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
8581 #define TSC_IOHCR_G5_IO3_Pos     (18U)
8582 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */
8583 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
8584 #define TSC_IOHCR_G5_IO4_Pos     (19U)
8585 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */
8586 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
8587 #define TSC_IOHCR_G6_IO1_Pos     (20U)
8588 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */
8589 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
8590 #define TSC_IOHCR_G6_IO2_Pos     (21U)
8591 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */
8592 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
8593 #define TSC_IOHCR_G6_IO3_Pos     (22U)
8594 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */
8595 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
8596 #define TSC_IOHCR_G6_IO4_Pos     (23U)
8597 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */
8598 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
8599 #define TSC_IOHCR_G7_IO1_Pos     (24U)
8600 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */
8601 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
8602 #define TSC_IOHCR_G7_IO2_Pos     (25U)
8603 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */
8604 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
8605 #define TSC_IOHCR_G7_IO3_Pos     (26U)
8606 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */
8607 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
8608 #define TSC_IOHCR_G7_IO4_Pos     (27U)
8609 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */
8610 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
8611 
8612 /*******************  Bit definition for TSC_IOASCR register  *****************/
8613 #define TSC_IOASCR_G1_IO1_Pos    (0U)
8614 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
8615 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
8616 #define TSC_IOASCR_G1_IO2_Pos    (1U)
8617 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
8618 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
8619 #define TSC_IOASCR_G1_IO3_Pos    (2U)
8620 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
8621 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
8622 #define TSC_IOASCR_G1_IO4_Pos    (3U)
8623 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
8624 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
8625 #define TSC_IOASCR_G2_IO1_Pos    (4U)
8626 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
8627 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
8628 #define TSC_IOASCR_G2_IO2_Pos    (5U)
8629 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
8630 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
8631 #define TSC_IOASCR_G2_IO3_Pos    (6U)
8632 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
8633 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
8634 #define TSC_IOASCR_G2_IO4_Pos    (7U)
8635 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
8636 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
8637 #define TSC_IOASCR_G3_IO1_Pos    (8U)
8638 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
8639 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
8640 #define TSC_IOASCR_G3_IO2_Pos    (9U)
8641 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
8642 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
8643 #define TSC_IOASCR_G3_IO3_Pos    (10U)
8644 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
8645 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
8646 #define TSC_IOASCR_G3_IO4_Pos    (11U)
8647 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
8648 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
8649 #define TSC_IOASCR_G4_IO1_Pos    (12U)
8650 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
8651 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
8652 #define TSC_IOASCR_G4_IO2_Pos    (13U)
8653 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
8654 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
8655 #define TSC_IOASCR_G4_IO3_Pos    (14U)
8656 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
8657 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
8658 #define TSC_IOASCR_G4_IO4_Pos    (15U)
8659 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
8660 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
8661 #define TSC_IOASCR_G5_IO1_Pos    (16U)
8662 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */
8663 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
8664 #define TSC_IOASCR_G5_IO2_Pos    (17U)
8665 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */
8666 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
8667 #define TSC_IOASCR_G5_IO3_Pos    (18U)
8668 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */
8669 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
8670 #define TSC_IOASCR_G5_IO4_Pos    (19U)
8671 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */
8672 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
8673 #define TSC_IOASCR_G6_IO1_Pos    (20U)
8674 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */
8675 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
8676 #define TSC_IOASCR_G6_IO2_Pos    (21U)
8677 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */
8678 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
8679 #define TSC_IOASCR_G6_IO3_Pos    (22U)
8680 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */
8681 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
8682 #define TSC_IOASCR_G6_IO4_Pos    (23U)
8683 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */
8684 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
8685 #define TSC_IOASCR_G7_IO1_Pos    (24U)
8686 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */
8687 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
8688 #define TSC_IOASCR_G7_IO2_Pos    (25U)
8689 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */
8690 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
8691 #define TSC_IOASCR_G7_IO3_Pos    (26U)
8692 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */
8693 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
8694 #define TSC_IOASCR_G7_IO4_Pos    (27U)
8695 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */
8696 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
8697 
8698 /*******************  Bit definition for TSC_IOSCR register  ******************/
8699 #define TSC_IOSCR_G1_IO1_Pos     (0U)
8700 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
8701 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
8702 #define TSC_IOSCR_G1_IO2_Pos     (1U)
8703 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
8704 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
8705 #define TSC_IOSCR_G1_IO3_Pos     (2U)
8706 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
8707 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
8708 #define TSC_IOSCR_G1_IO4_Pos     (3U)
8709 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
8710 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
8711 #define TSC_IOSCR_G2_IO1_Pos     (4U)
8712 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
8713 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
8714 #define TSC_IOSCR_G2_IO2_Pos     (5U)
8715 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
8716 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
8717 #define TSC_IOSCR_G2_IO3_Pos     (6U)
8718 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
8719 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
8720 #define TSC_IOSCR_G2_IO4_Pos     (7U)
8721 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
8722 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
8723 #define TSC_IOSCR_G3_IO1_Pos     (8U)
8724 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
8725 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
8726 #define TSC_IOSCR_G3_IO2_Pos     (9U)
8727 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
8728 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
8729 #define TSC_IOSCR_G3_IO3_Pos     (10U)
8730 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
8731 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
8732 #define TSC_IOSCR_G3_IO4_Pos     (11U)
8733 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
8734 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
8735 #define TSC_IOSCR_G4_IO1_Pos     (12U)
8736 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
8737 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
8738 #define TSC_IOSCR_G4_IO2_Pos     (13U)
8739 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
8740 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
8741 #define TSC_IOSCR_G4_IO3_Pos     (14U)
8742 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
8743 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
8744 #define TSC_IOSCR_G4_IO4_Pos     (15U)
8745 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
8746 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
8747 #define TSC_IOSCR_G5_IO1_Pos     (16U)
8748 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */
8749 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
8750 #define TSC_IOSCR_G5_IO2_Pos     (17U)
8751 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */
8752 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
8753 #define TSC_IOSCR_G5_IO3_Pos     (18U)
8754 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */
8755 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
8756 #define TSC_IOSCR_G5_IO4_Pos     (19U)
8757 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */
8758 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
8759 #define TSC_IOSCR_G6_IO1_Pos     (20U)
8760 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */
8761 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
8762 #define TSC_IOSCR_G6_IO2_Pos     (21U)
8763 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */
8764 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
8765 #define TSC_IOSCR_G6_IO3_Pos     (22U)
8766 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */
8767 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
8768 #define TSC_IOSCR_G6_IO4_Pos     (23U)
8769 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */
8770 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
8771 #define TSC_IOSCR_G7_IO1_Pos     (24U)
8772 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */
8773 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
8774 #define TSC_IOSCR_G7_IO2_Pos     (25U)
8775 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */
8776 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
8777 #define TSC_IOSCR_G7_IO3_Pos     (26U)
8778 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */
8779 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
8780 #define TSC_IOSCR_G7_IO4_Pos     (27U)
8781 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */
8782 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
8783 
8784 /*******************  Bit definition for TSC_IOCCR register  ******************/
8785 #define TSC_IOCCR_G1_IO1_Pos     (0U)
8786 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
8787 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
8788 #define TSC_IOCCR_G1_IO2_Pos     (1U)
8789 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
8790 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
8791 #define TSC_IOCCR_G1_IO3_Pos     (2U)
8792 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
8793 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
8794 #define TSC_IOCCR_G1_IO4_Pos     (3U)
8795 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
8796 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
8797 #define TSC_IOCCR_G2_IO1_Pos     (4U)
8798 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
8799 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
8800 #define TSC_IOCCR_G2_IO2_Pos     (5U)
8801 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
8802 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
8803 #define TSC_IOCCR_G2_IO3_Pos     (6U)
8804 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
8805 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
8806 #define TSC_IOCCR_G2_IO4_Pos     (7U)
8807 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
8808 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
8809 #define TSC_IOCCR_G3_IO1_Pos     (8U)
8810 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
8811 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
8812 #define TSC_IOCCR_G3_IO2_Pos     (9U)
8813 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
8814 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
8815 #define TSC_IOCCR_G3_IO3_Pos     (10U)
8816 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
8817 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
8818 #define TSC_IOCCR_G3_IO4_Pos     (11U)
8819 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
8820 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
8821 #define TSC_IOCCR_G4_IO1_Pos     (12U)
8822 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
8823 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
8824 #define TSC_IOCCR_G4_IO2_Pos     (13U)
8825 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
8826 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
8827 #define TSC_IOCCR_G4_IO3_Pos     (14U)
8828 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
8829 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
8830 #define TSC_IOCCR_G4_IO4_Pos     (15U)
8831 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
8832 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
8833 #define TSC_IOCCR_G5_IO1_Pos     (16U)
8834 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */
8835 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
8836 #define TSC_IOCCR_G5_IO2_Pos     (17U)
8837 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */
8838 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
8839 #define TSC_IOCCR_G5_IO3_Pos     (18U)
8840 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */
8841 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
8842 #define TSC_IOCCR_G5_IO4_Pos     (19U)
8843 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */
8844 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
8845 #define TSC_IOCCR_G6_IO1_Pos     (20U)
8846 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */
8847 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
8848 #define TSC_IOCCR_G6_IO2_Pos     (21U)
8849 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */
8850 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
8851 #define TSC_IOCCR_G6_IO3_Pos     (22U)
8852 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */
8853 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
8854 #define TSC_IOCCR_G6_IO4_Pos     (23U)
8855 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */
8856 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
8857 #define TSC_IOCCR_G7_IO1_Pos     (24U)
8858 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */
8859 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
8860 #define TSC_IOCCR_G7_IO2_Pos     (25U)
8861 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */
8862 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
8863 #define TSC_IOCCR_G7_IO3_Pos     (26U)
8864 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */
8865 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
8866 #define TSC_IOCCR_G7_IO4_Pos     (27U)
8867 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */
8868 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
8869 
8870 /*******************  Bit definition for TSC_IOGCSR register  *****************/
8871 #define TSC_IOGCSR_G1E_Pos       (0U)
8872 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
8873 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
8874 #define TSC_IOGCSR_G2E_Pos       (1U)
8875 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
8876 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
8877 #define TSC_IOGCSR_G3E_Pos       (2U)
8878 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
8879 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
8880 #define TSC_IOGCSR_G4E_Pos       (3U)
8881 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
8882 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
8883 #define TSC_IOGCSR_G5E_Pos       (4U)
8884 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */
8885 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
8886 #define TSC_IOGCSR_G6E_Pos       (5U)
8887 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */
8888 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
8889 #define TSC_IOGCSR_G7E_Pos       (6U)
8890 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */
8891 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
8892 #define TSC_IOGCSR_G1S_Pos       (16U)
8893 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
8894 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
8895 #define TSC_IOGCSR_G2S_Pos       (17U)
8896 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
8897 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
8898 #define TSC_IOGCSR_G3S_Pos       (18U)
8899 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
8900 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
8901 #define TSC_IOGCSR_G4S_Pos       (19U)
8902 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
8903 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
8904 #define TSC_IOGCSR_G5S_Pos       (20U)
8905 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */
8906 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
8907 #define TSC_IOGCSR_G6S_Pos       (21U)
8908 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */
8909 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
8910 #define TSC_IOGCSR_G7S_Pos       (22U)
8911 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */
8912 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
8913 
8914 /*******************  Bit definition for TSC_IOGXCR register  *****************/
8915 #define TSC_IOGXCR_CNT_Pos       (0U)
8916 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
8917 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
8918 
8919 /******************************************************************************/
8920 /*                                                                            */
8921 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
8922 /*                                                                            */
8923 /******************************************************************************/
8924 /******************  Bit definition for USART_CR1 register  *******************/
8925 #define USART_CR1_UE_Pos                (0U)
8926 #define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
8927 #define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
8928 #define USART_CR1_UESM_Pos              (1U)
8929 #define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
8930 #define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
8931 #define USART_CR1_RE_Pos                (2U)
8932 #define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
8933 #define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
8934 #define USART_CR1_TE_Pos                (3U)
8935 #define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
8936 #define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
8937 #define USART_CR1_IDLEIE_Pos            (4U)
8938 #define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
8939 #define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
8940 #define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
8941 #define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
8942 #define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
8943 #define USART_CR1_TCIE_Pos              (6U)
8944 #define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
8945 #define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
8946 #define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
8947 #define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
8948 #define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
8949 #define USART_CR1_PEIE_Pos              (8U)
8950 #define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
8951 #define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
8952 #define USART_CR1_PS_Pos                (9U)
8953 #define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
8954 #define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
8955 #define USART_CR1_PCE_Pos               (10U)
8956 #define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
8957 #define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
8958 #define USART_CR1_WAKE_Pos              (11U)
8959 #define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
8960 #define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
8961 #define USART_CR1_M_Pos                 (12U)
8962 #define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
8963 #define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
8964 #define USART_CR1_M0_Pos                (12U)
8965 #define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
8966 #define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
8967 #define USART_CR1_MME_Pos               (13U)
8968 #define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
8969 #define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
8970 #define USART_CR1_CMIE_Pos              (14U)
8971 #define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
8972 #define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
8973 #define USART_CR1_OVER8_Pos             (15U)
8974 #define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
8975 #define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
8976 #define USART_CR1_DEDT_Pos              (16U)
8977 #define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
8978 #define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
8979 #define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
8980 #define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
8981 #define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
8982 #define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
8983 #define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
8984 #define USART_CR1_DEAT_Pos              (21U)
8985 #define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
8986 #define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
8987 #define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
8988 #define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
8989 #define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
8990 #define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
8991 #define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
8992 #define USART_CR1_RTOIE_Pos             (26U)
8993 #define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
8994 #define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
8995 #define USART_CR1_EOBIE_Pos             (27U)
8996 #define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
8997 #define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
8998 #define USART_CR1_M1_Pos                (28U)
8999 #define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
9000 #define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
9001 #define USART_CR1_FIFOEN_Pos            (29U)
9002 #define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
9003 #define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
9004 #define USART_CR1_TXFEIE_Pos            (30U)
9005 #define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
9006 #define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
9007 #define USART_CR1_RXFFIE_Pos            (31U)
9008 #define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
9009 #define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
9010 
9011 /* Legacy define */
9012 #define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
9013 #define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
9014 
9015 /******************  Bit definition for USART_CR2 register  *******************/
9016 #define USART_CR2_SLVEN_Pos             (0U)
9017 #define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
9018 #define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
9019 #define USART_CR2_DIS_NSS_Pos           (3U)
9020 #define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
9021 #define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
9022 #define USART_CR2_ADDM7_Pos             (4U)
9023 #define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
9024 #define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
9025 #define USART_CR2_LBDL_Pos              (5U)
9026 #define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
9027 #define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
9028 #define USART_CR2_LBDIE_Pos             (6U)
9029 #define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
9030 #define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
9031 #define USART_CR2_LBCL_Pos              (8U)
9032 #define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
9033 #define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
9034 #define USART_CR2_CPHA_Pos              (9U)
9035 #define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
9036 #define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
9037 #define USART_CR2_CPOL_Pos              (10U)
9038 #define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
9039 #define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
9040 #define USART_CR2_CLKEN_Pos             (11U)
9041 #define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
9042 #define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
9043 #define USART_CR2_STOP_Pos              (12U)
9044 #define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
9045 #define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
9046 #define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
9047 #define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
9048 #define USART_CR2_LINEN_Pos             (14U)
9049 #define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
9050 #define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
9051 #define USART_CR2_SWAP_Pos              (15U)
9052 #define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
9053 #define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
9054 #define USART_CR2_RXINV_Pos             (16U)
9055 #define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
9056 #define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
9057 #define USART_CR2_TXINV_Pos             (17U)
9058 #define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
9059 #define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
9060 #define USART_CR2_DATAINV_Pos           (18U)
9061 #define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
9062 #define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
9063 #define USART_CR2_MSBFIRST_Pos          (19U)
9064 #define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
9065 #define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
9066 #define USART_CR2_ABREN_Pos             (20U)
9067 #define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
9068 #define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
9069 #define USART_CR2_ABRMODE_Pos           (21U)
9070 #define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
9071 #define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
9072 #define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
9073 #define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
9074 #define USART_CR2_RTOEN_Pos             (23U)
9075 #define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
9076 #define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
9077 #define USART_CR2_ADD_Pos               (24U)
9078 #define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
9079 #define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
9080 
9081 /******************  Bit definition for USART_CR3 register  *******************/
9082 #define USART_CR3_EIE_Pos               (0U)
9083 #define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
9084 #define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
9085 #define USART_CR3_IREN_Pos              (1U)
9086 #define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
9087 #define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
9088 #define USART_CR3_IRLP_Pos              (2U)
9089 #define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
9090 #define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
9091 #define USART_CR3_HDSEL_Pos             (3U)
9092 #define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
9093 #define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
9094 #define USART_CR3_NACK_Pos              (4U)
9095 #define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
9096 #define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
9097 #define USART_CR3_SCEN_Pos              (5U)
9098 #define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
9099 #define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
9100 #define USART_CR3_DMAR_Pos              (6U)
9101 #define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
9102 #define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
9103 #define USART_CR3_DMAT_Pos              (7U)
9104 #define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
9105 #define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
9106 #define USART_CR3_RTSE_Pos              (8U)
9107 #define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
9108 #define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
9109 #define USART_CR3_CTSE_Pos              (9U)
9110 #define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
9111 #define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
9112 #define USART_CR3_CTSIE_Pos             (10U)
9113 #define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
9114 #define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
9115 #define USART_CR3_ONEBIT_Pos            (11U)
9116 #define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
9117 #define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
9118 #define USART_CR3_OVRDIS_Pos            (12U)
9119 #define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
9120 #define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
9121 #define USART_CR3_DDRE_Pos              (13U)
9122 #define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
9123 #define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
9124 #define USART_CR3_DEM_Pos               (14U)
9125 #define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
9126 #define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
9127 #define USART_CR3_DEP_Pos               (15U)
9128 #define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
9129 #define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
9130 #define USART_CR3_SCARCNT_Pos           (17U)
9131 #define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
9132 #define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
9133 #define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
9134 #define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
9135 #define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
9136 #define USART_CR3_WUS_Pos               (20U)
9137 #define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
9138 #define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
9139 #define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
9140 #define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
9141 #define USART_CR3_WUFIE_Pos             (22U)
9142 #define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
9143 #define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
9144 #define USART_CR3_TXFTIE_Pos            (23U)
9145 #define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
9146 #define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
9147 #define USART_CR3_TCBGTIE_Pos           (24U)
9148 #define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
9149 #define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
9150 #define USART_CR3_RXFTCFG_Pos           (25U)
9151 #define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
9152 #define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
9153 #define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
9154 #define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
9155 #define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
9156 #define USART_CR3_RXFTIE_Pos            (28U)
9157 #define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
9158 #define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
9159 #define USART_CR3_TXFTCFG_Pos           (29U)
9160 #define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
9161 #define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
9162 #define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
9163 #define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
9164 #define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
9165 
9166 /******************  Bit definition for USART_BRR register  *******************/
9167 #define USART_BRR_DIV_FRACTION_Pos      (0U)
9168 #define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
9169 #define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
9170 #define USART_BRR_DIV_MANTISSA_Pos      (4U)
9171 #define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
9172 #define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
9173 
9174 /******************  Bit definition for USART_GTPR register  ******************/
9175 #define USART_GTPR_PSC_Pos              (0U)
9176 #define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
9177 #define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
9178 #define USART_GTPR_GT_Pos               (8U)
9179 #define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
9180 #define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
9181 
9182 /*******************  Bit definition for USART_RTOR register  *****************/
9183 #define USART_RTOR_RTO_Pos              (0U)
9184 #define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
9185 #define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
9186 #define USART_RTOR_BLEN_Pos             (24U)
9187 #define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
9188 #define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
9189 
9190 /*******************  Bit definition for USART_RQR register  ******************/
9191 #define USART_RQR_ABRRQ_Pos             (0U)
9192 #define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
9193 #define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
9194 #define USART_RQR_SBKRQ_Pos             (1U)
9195 #define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
9196 #define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
9197 #define USART_RQR_MMRQ_Pos              (2U)
9198 #define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
9199 #define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
9200 #define USART_RQR_RXFRQ_Pos             (3U)
9201 #define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
9202 #define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
9203 #define USART_RQR_TXFRQ_Pos             (4U)
9204 #define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
9205 #define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
9206 
9207 /*******************  Bit definition for USART_ISR register  ******************/
9208 #define USART_ISR_PE_Pos                (0U)
9209 #define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
9210 #define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
9211 #define USART_ISR_FE_Pos                (1U)
9212 #define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
9213 #define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
9214 #define USART_ISR_NE_Pos                (2U)
9215 #define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
9216 #define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
9217 #define USART_ISR_ORE_Pos               (3U)
9218 #define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
9219 #define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
9220 #define USART_ISR_IDLE_Pos              (4U)
9221 #define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
9222 #define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
9223 #define USART_ISR_RXNE_RXFNE_Pos        (5U)
9224 #define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
9225 #define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
9226 #define USART_ISR_TC_Pos                (6U)
9227 #define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
9228 #define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
9229 #define USART_ISR_TXE_TXFNF_Pos         (7U)
9230 #define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
9231 #define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
9232 #define USART_ISR_LBDF_Pos              (8U)
9233 #define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
9234 #define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
9235 #define USART_ISR_CTSIF_Pos             (9U)
9236 #define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
9237 #define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
9238 #define USART_ISR_CTS_Pos               (10U)
9239 #define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
9240 #define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
9241 #define USART_ISR_RTOF_Pos              (11U)
9242 #define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
9243 #define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
9244 #define USART_ISR_EOBF_Pos              (12U)
9245 #define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
9246 #define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
9247 #define USART_ISR_UDR_Pos               (13U)
9248 #define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
9249 #define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
9250 #define USART_ISR_ABRE_Pos              (14U)
9251 #define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
9252 #define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
9253 #define USART_ISR_ABRF_Pos              (15U)
9254 #define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
9255 #define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
9256 #define USART_ISR_BUSY_Pos              (16U)
9257 #define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
9258 #define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
9259 #define USART_ISR_CMF_Pos               (17U)
9260 #define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
9261 #define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
9262 #define USART_ISR_SBKF_Pos              (18U)
9263 #define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
9264 #define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
9265 #define USART_ISR_RWU_Pos               (19U)
9266 #define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
9267 #define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
9268 #define USART_ISR_WUF_Pos               (20U)
9269 #define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
9270 #define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
9271 #define USART_ISR_TEACK_Pos             (21U)
9272 #define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
9273 #define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
9274 #define USART_ISR_REACK_Pos             (22U)
9275 #define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
9276 #define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
9277 #define USART_ISR_TXFE_Pos              (23U)
9278 #define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
9279 #define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
9280 #define USART_ISR_RXFF_Pos              (24U)
9281 #define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
9282 #define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
9283 #define USART_ISR_TCBGT_Pos             (25U)
9284 #define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
9285 #define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
9286 #define USART_ISR_RXFT_Pos              (26U)
9287 #define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
9288 #define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
9289 #define USART_ISR_TXFT_Pos              (27U)
9290 #define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
9291 #define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
9292 
9293 /*******************  Bit definition for USART_ICR register  ******************/
9294 #define USART_ICR_PECF_Pos              (0U)
9295 #define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
9296 #define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
9297 #define USART_ICR_FECF_Pos              (1U)
9298 #define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
9299 #define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
9300 #define USART_ICR_NECF_Pos              (2U)
9301 #define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
9302 #define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
9303 #define USART_ICR_ORECF_Pos             (3U)
9304 #define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
9305 #define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
9306 #define USART_ICR_IDLECF_Pos            (4U)
9307 #define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
9308 #define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
9309 #define USART_ICR_TXFECF_Pos            (5U)
9310 #define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
9311 #define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
9312 #define USART_ICR_TCCF_Pos              (6U)
9313 #define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
9314 #define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
9315 #define USART_ICR_TCBGTCF_Pos           (7U)
9316 #define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
9317 #define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
9318 #define USART_ICR_LBDCF_Pos             (8U)
9319 #define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
9320 #define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
9321 #define USART_ICR_CTSCF_Pos             (9U)
9322 #define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
9323 #define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
9324 #define USART_ICR_RTOCF_Pos             (11U)
9325 #define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
9326 #define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
9327 #define USART_ICR_EOBCF_Pos             (12U)
9328 #define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
9329 #define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
9330 #define USART_ICR_UDRCF_Pos             (13U)
9331 #define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
9332 #define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
9333 #define USART_ICR_CMCF_Pos              (17U)
9334 #define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
9335 #define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
9336 #define USART_ICR_WUCF_Pos              (20U)
9337 #define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
9338 #define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
9339 
9340 /*******************  Bit definition for USART_RDR register  ******************/
9341 #define USART_RDR_RDR_Pos               (0U)
9342 #define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
9343 #define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
9344 
9345 /*******************  Bit definition for USART_TDR register  ******************/
9346 #define USART_TDR_TDR_Pos               (0U)
9347 #define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
9348 #define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
9349 
9350 /*******************  Bit definition for USART_PRESC register  ******************/
9351 #define USART_PRESC_PRESCALER_Pos       (0U)
9352 #define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
9353 #define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
9354 #define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
9355 #define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
9356 #define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
9357 #define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
9358 
9359 
9360 /******************************************************************************/
9361 /*                                                                            */
9362 /*           Single Wire Protocol Master Interface (SWPMI)                    */
9363 /*                                                                            */
9364 /******************************************************************************/
9365 
9366 /*******************  Bit definition for SWPMI_CR register   ********************/
9367 #define SWPMI_CR_RXDMA_Pos       (0U)
9368 #define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
9369 #define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
9370 #define SWPMI_CR_TXDMA_Pos       (1U)
9371 #define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
9372 #define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
9373 #define SWPMI_CR_RXMODE_Pos      (2U)
9374 #define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
9375 #define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
9376 #define SWPMI_CR_TXMODE_Pos      (3U)
9377 #define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
9378 #define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
9379 #define SWPMI_CR_LPBK_Pos        (4U)
9380 #define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
9381 #define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
9382 #define SWPMI_CR_SWPACT_Pos      (5U)
9383 #define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
9384 #define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
9385 #define SWPMI_CR_DEACT_Pos       (10U)
9386 #define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
9387 #define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
9388 #define SWPMI_CR_SWPEN_Pos       (11U)
9389 #define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
9390 #define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
9391 
9392 /*******************  Bit definition for SWPMI_BRR register  ********************/
9393 #define SWPMI_BRR_BR_Pos         (0U)
9394 #define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
9395 #define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
9396 
9397 /*******************  Bit definition for SWPMI_ISR register  ********************/
9398 #define SWPMI_ISR_RXBFF_Pos      (0U)
9399 #define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
9400 #define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
9401 #define SWPMI_ISR_TXBEF_Pos      (1U)
9402 #define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
9403 #define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
9404 #define SWPMI_ISR_RXBERF_Pos     (2U)
9405 #define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
9406 #define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
9407 #define SWPMI_ISR_RXOVRF_Pos     (3U)
9408 #define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
9409 #define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
9410 #define SWPMI_ISR_TXUNRF_Pos     (4U)
9411 #define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
9412 #define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
9413 #define SWPMI_ISR_RXNE_Pos       (5U)
9414 #define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
9415 #define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
9416 #define SWPMI_ISR_TXE_Pos        (6U)
9417 #define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
9418 #define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
9419 #define SWPMI_ISR_TCF_Pos        (7U)
9420 #define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
9421 #define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
9422 #define SWPMI_ISR_SRF_Pos        (8U)
9423 #define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
9424 #define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
9425 #define SWPMI_ISR_SUSP_Pos       (9U)
9426 #define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
9427 #define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
9428 #define SWPMI_ISR_DEACTF_Pos     (10U)
9429 #define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
9430 #define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
9431 #define SWPMI_ISR_RDYF_Pos       (11U)
9432 #define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
9433 #define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
9434 
9435 /*******************  Bit definition for SWPMI_ICR register  ********************/
9436 #define SWPMI_ICR_CRXBFF_Pos     (0U)
9437 #define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
9438 #define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
9439 #define SWPMI_ICR_CTXBEF_Pos     (1U)
9440 #define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
9441 #define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
9442 #define SWPMI_ICR_CRXBERF_Pos    (2U)
9443 #define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
9444 #define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
9445 #define SWPMI_ICR_CRXOVRF_Pos    (3U)
9446 #define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
9447 #define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
9448 #define SWPMI_ICR_CTXUNRF_Pos    (4U)
9449 #define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
9450 #define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
9451 #define SWPMI_ICR_CTCF_Pos       (7U)
9452 #define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
9453 #define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
9454 #define SWPMI_ICR_CSRF_Pos       (8U)
9455 #define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
9456 #define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
9457 #define SWPMI_ICR_CRDYF_Pos      (11U)
9458 #define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
9459 #define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
9460 
9461 /*******************  Bit definition for SWPMI_IER register  ********************/
9462 #define SWPMI_IER_RXBFIE_Pos     (0U)
9463 #define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
9464 #define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
9465 #define SWPMI_IER_TXBEIE_Pos     (1U)
9466 #define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
9467 #define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
9468 #define SWPMI_IER_RXBERIE_Pos    (2U)
9469 #define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
9470 #define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
9471 #define SWPMI_IER_RXOVRIE_Pos    (3U)
9472 #define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
9473 #define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
9474 #define SWPMI_IER_TXUNRIE_Pos    (4U)
9475 #define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
9476 #define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
9477 #define SWPMI_IER_RIE_Pos        (5U)
9478 #define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
9479 #define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
9480 #define SWPMI_IER_TIE_Pos        (6U)
9481 #define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
9482 #define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
9483 #define SWPMI_IER_TCIE_Pos       (7U)
9484 #define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
9485 #define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
9486 #define SWPMI_IER_SRIE_Pos       (8U)
9487 #define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
9488 #define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
9489 #define SWPMI_IER_RDYIE_Pos      (11U)
9490 #define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
9491 #define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
9492 
9493 /*******************  Bit definition for SWPMI_RFL register  ********************/
9494 #define SWPMI_RFL_RFL_Pos        (0U)
9495 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
9496 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
9497 #define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
9498 
9499 /*******************  Bit definition for SWPMI_TDR register  ********************/
9500 #define SWPMI_TDR_TD_Pos         (0U)
9501 #define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
9502 #define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
9503 
9504 /*******************  Bit definition for SWPMI_RDR register  ********************/
9505 #define SWPMI_RDR_RD_Pos         (0U)
9506 #define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
9507 #define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */
9508 
9509 
9510 /*******************  Bit definition for SWPMI_OR register  ********************/
9511 #define SWPMI_OR_TBYP_Pos        (0U)
9512 #define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
9513 #define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
9514 #define SWPMI_OR_CLASS_Pos       (1U)
9515 #define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
9516 #define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
9517 
9518 /******************************************************************************/
9519 /*                                                                            */
9520 /*                            Window WATCHDOG                                 */
9521 /*                                                                            */
9522 /******************************************************************************/
9523 /*******************  Bit definition for WWDG_CR register  ********************/
9524 #define WWDG_CR_T_Pos           (0U)
9525 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
9526 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
9527 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
9528 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
9529 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
9530 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
9531 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
9532 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
9533 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
9534 
9535 #define WWDG_CR_WDGA_Pos        (7U)
9536 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
9537 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
9538 
9539 /*******************  Bit definition for WWDG_CFR register  *******************/
9540 #define WWDG_CFR_W_Pos          (0U)
9541 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
9542 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
9543 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
9544 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
9545 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
9546 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
9547 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
9548 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
9549 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
9550 
9551 #define WWDG_CFR_EWI_Pos        (9U)
9552 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
9553 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
9554 
9555 #define WWDG_CFR_WDGTB_Pos      (11U)
9556 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
9557 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
9558 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
9559 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
9560 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
9561 
9562 /*******************  Bit definition for WWDG_SR register  ********************/
9563 #define WWDG_SR_EWIF_Pos        (0U)
9564 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
9565 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
9566 
9567 
9568 /******************************************************************************/
9569 /*                                                                            */
9570 /*                                DBG                                         */
9571 /*                                                                            */
9572 /******************************************************************************/
9573 
9574 /********************  Bit definition for DBGMCU_IDCODE register  *************/
9575 #define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
9576 #define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)  /*!< 0x00000FFF */
9577 #define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
9578 #define DBGMCU_IDCODE_REV_ID_Pos          (16U)
9579 #define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
9580 #define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
9581 
9582 /********************  Bit definition for DBGMCU_CR register  *****************/
9583 #define DBGMCU_CR_DBG_STOP_Pos           (1U)
9584 #define DBGMCU_CR_DBG_STOP_Msk           (0x1UL << DBGMCU_CR_DBG_STOP_Pos)     /*!< 0x00000002 */
9585 #define DBGMCU_CR_DBG_STOP               DBGMCU_CR_DBG_STOP_Msk
9586 #define DBGMCU_CR_DBG_STANDBY_Pos        (2U)
9587 #define DBGMCU_CR_DBG_STANDBY_Msk        (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)  /*!< 0x00000004 */
9588 #define DBGMCU_CR_DBG_STANDBY            DBGMCU_CR_DBG_STANDBY_Msk
9589 
9590 /********************  Bit definition for DBGMCU_APB1FZR register  ***********/
9591 #define DBGMCU_APBFZ1_DBG_TIM2_STOP_Pos                  (0U)
9592 #define DBGMCU_APBFZ1_DBG_TIM2_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
9593 #define DBGMCU_APBFZ1_DBG_TIM2_STOP                      DBGMCU_APBFZ1_DBG_TIM2_STOP_Msk
9594 #define DBGMCU_APBFZ1_DBG_TIM3_STOP_Pos                  (1U)
9595 #define DBGMCU_APBFZ1_DBG_TIM3_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM3_STOP_Pos)  /*!< 0x00000002 */
9596 #define DBGMCU_APBFZ1_DBG_TIM3_STOP                      DBGMCU_APBFZ1_DBG_TIM3_STOP_Msk
9597 #define DBGMCU_APBFZ1_DBG_TIM4_STOP_Pos                  (2U)
9598 #define DBGMCU_APBFZ1_DBG_TIM4_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM4_STOP_Pos)  /*!< 0x00000004 */
9599 #define DBGMCU_APBFZ1_DBG_TIM4_STOP                      DBGMCU_APBFZ1_DBG_TIM4_STOP_Msk
9600 #define DBGMCU_APBFZ1_DBG_TIM6_STOP_Pos                  (4U)
9601 #define DBGMCU_APBFZ1_DBG_TIM6_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM6_STOP_Pos)  /*!< 0x00000010 */
9602 #define DBGMCU_APBFZ1_DBG_TIM6_STOP                      DBGMCU_APBFZ1_DBG_TIM6_STOP_Msk
9603 #define DBGMCU_APBFZ1_DBG_TIM7_STOP_Pos                  (5U)
9604 #define DBGMCU_APBFZ1_DBG_TIM7_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
9605 #define DBGMCU_APBFZ1_DBG_TIM7_STOP                      DBGMCU_APBFZ1_DBG_TIM7_STOP_Msk
9606 #define DBGMCU_APBFZ1_DBG_RTC_STOP_Pos                   (10U)
9607 #define DBGMCU_APBFZ1_DBG_RTC_STOP_Msk                   (0x1UL << DBGMCU_APBFZ1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
9608 #define DBGMCU_APBFZ1_DBG_RTC_STOP                       DBGMCU_APBFZ1_DBG_RTC_STOP_Msk
9609 #define DBGMCU_APBFZ1_DBG_WWDG_STOP_Pos                  (11U)
9610 #define DBGMCU_APBFZ1_DBG_WWDG_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
9611 #define DBGMCU_APBFZ1_DBG_WWDG_STOP                      DBGMCU_APBFZ1_DBG_WWDG_STOP_Msk
9612 #define DBGMCU_APBFZ1_DBG_IWDG_STOP_Pos                  (12U)
9613 #define DBGMCU_APBFZ1_DBG_IWDG_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
9614 #define DBGMCU_APBFZ1_DBG_IWDG_STOP                      DBGMCU_APBFZ1_DBG_IWDG_STOP_Msk
9615 #define DBGMCU_APBFZ1_DBG_I2C3_STOP_Pos                  (21U)
9616 #define DBGMCU_APBFZ1_DBG_I2C3_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00200000 */
9617 #define DBGMCU_APBFZ1_DBG_I2C3_STOP                      DBGMCU_APBFZ1_DBG_I2C3_STOP_Msk
9618 #define DBGMCU_APBFZ1_DBG_I2C1_STOP_Pos                  (22U)
9619 #define DBGMCU_APBFZ1_DBG_I2C1_STOP_Msk                  (0x1UL << DBGMCU_APBFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00400000 */
9620 #define DBGMCU_APBFZ1_DBG_I2C1_STOP                      DBGMCU_APBFZ1_DBG_I2C1_STOP_Msk
9621 #define DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Pos                (30U)
9622 #define DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Msk                (0x1UL << DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x40000000 */
9623 #define DBGMCU_APBFZ1_DBG_LPTIM2_STOP                    DBGMCU_APBFZ1_DBG_LPTIM2_STOP_Msk
9624 #define DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Pos                (31U)
9625 #define DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Msk                (0x1UL << DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
9626 #define DBGMCU_APBFZ1_DBG_LPTIM1_STOP                    DBGMCU_APBFZ1_DBG_LPTIM1_STOP_Msk
9627 
9628 /********************  Bit definition for DBGMCU_APB2FZR register  ************/
9629 #define DBGMCU_APBFZ2_DBG_TIM1_STOP_Pos                  (11U)
9630 #define DBGMCU_APBFZ2_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APBFZ2_DBG_TIM1_STOP_Pos)  /*!< 0x00000800 */
9631 #define DBGMCU_APBFZ2_DBG_TIM1_STOP                      DBGMCU_APBFZ2_DBG_TIM1_STOP_Msk
9632 #define DBGMCU_APBFZ2_DBG_TIM14_STOP_Pos                 (15U)
9633 #define DBGMCU_APBFZ2_DBG_TIM14_STOP_Msk                 (0x1UL << DBGMCU_APBFZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
9634 #define DBGMCU_APBFZ2_DBG_TIM14_STOP                     DBGMCU_APBFZ2_DBG_TIM14_STOP_Msk
9635 #define DBGMCU_APBFZ2_DBG_TIM15_STOP_Pos                 (16U)
9636 #define DBGMCU_APBFZ2_DBG_TIM15_STOP_Msk                 (0x1UL << DBGMCU_APBFZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
9637 #define DBGMCU_APBFZ2_DBG_TIM15_STOP                     DBGMCU_APBFZ2_DBG_TIM15_STOP_Msk
9638 #define DBGMCU_APBFZ2_DBG_TIM16_STOP_Pos                 (17U)
9639 #define DBGMCU_APBFZ2_DBG_TIM16_STOP_Msk                 (0x1UL << DBGMCU_APBFZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
9640 #define DBGMCU_APBFZ2_DBG_TIM16_STOP                     DBGMCU_APBFZ2_DBG_TIM16_STOP_Msk
9641 #define DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Pos                (18U)
9642 #define DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Msk                (0x1UL << DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Pos) /*!< 0x00040000 */
9643 #define DBGMCU_APBFZ2_DBG_LPTIM3_STOP                    DBGMCU_APBFZ2_DBG_LPTIM3_STOP_Msk
9644 
9645 /********************  Bit definition for DBGMCU_SR register  ************/
9646 #define DBGMCU_SR_AP1_PRESENT_Pos                     (0U)
9647 #define DBGMCU_SR_AP1_PRESENT_Msk                     (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000001 */
9648 #define DBGMCU_SR_AP1_PRESENT                         DBGMCU_SR_AP1_PRESENT_Msk
9649 #define DBGMCU_SR_AP0_PRESENT_Pos                     (1U)
9650 #define DBGMCU_SR_AP0_PRESENT_Msk                     (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000002 */
9651 #define DBGMCU_SR_AP0_PRESENT                         DBGMCU_SR_AP0_PRESENT_Msk
9652 #define DBGMCU_SR_AP1_ENABLED_Pos                     (16U)
9653 #define DBGMCU_SR_AP1_ENABLED_Msk                     (0x1UL << DBGMCU_SR_AP1_ENABLED_Pos)           /*!< 0x00010000 */
9654 #define DBGMCU_SR_AP1_ENABLED                         DBGMCU_SR_AP1_ENABLED_Msk
9655 #define DBGMCU_SR_AP0_ENABLED_Pos                     (17U)
9656 #define DBGMCU_SR_AP0_ENABLED_Msk                     (0x1UL << DBGMCU_SR_AP0_ENABLED_Pos)           /*!< 0x00020000 */
9657 #define DBGMCU_SR_AP0_ENABLED                         DBGMCU_SR_AP0_ENABLED_Msk
9658 
9659 /********************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ************/
9660 #define DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Pos          (0U)
9661 #define DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Msk          (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
9662 #define DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE              DBGMCU_DBG_AUTH_HOST_AP1_MESSAGE_Msk
9663 
9664 /********************  Bit definition for DBGMCU_DBG_AUTH_DEVICE register  ************/
9665 #define DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Pos            (0U)
9666 #define DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Msk            (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
9667 #define DBGMCU_DBG_AUTH_DEVICE_MESSAGE                DBGMCU_DBG_AUTH_DEVICE_MESSAGE_Msk
9668 
9669 /********************  Bit definition for DBGMCU_PIDR4 register  ************/
9670 #define DBGMCU_PIDR4_JEP106CON_Pos                   (0U)
9671 #define DBGMCU_PIDR4_JEP106CON_Msk                   (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)                  /*!< 0x0000000F */
9672 #define DBGMCU_PIDR4_JEP106CON                       DBGMCU_PIDR4_JEP106CON_Msk
9673 #define DBGMCU_PIDR4_SIZE_Pos                        (4U)
9674 #define DBGMCU_PIDR4_SIZE_Msk                        (0xFUL << DBGMCU_PIDR4_SIZE_Pos)                       /*!< 0x0000000F */
9675 #define DBGMCU_PIDR4_SIZE                            DBGMCU_PIDR4_SIZE_Msk
9676 
9677 /********************  Bit definition for DBGMCU_PIDR0 register  ************/
9678 #define DBGMCU_PIDR0_PARTNUM_Pos                     (0U)
9679 #define DBGMCU_PIDR0_PARTNUM_Msk                     (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)                   /*!< 0x000000FF */
9680 #define DBGMCU_PIDR0_PARTNUM                         DBGMCU_PIDR0_PARTNUM_Msk
9681 
9682 /********************  Bit definition for DBGMCU_PIDR1 register  ************/
9683 #define DBGMCU_PIDR1_PARTNUM_Pos                     (0U)
9684 #define DBGMCU_PIDR1_PARTNUM_Msk                     (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)                    /*!< 0x0000000F */
9685 #define DBGMCU_PIDR1_PARTNUM                         DBGMCU_PIDR1_PARTNUM_Msk
9686 #define DBGMCU_PIDR1_JEP106ID_Pos                    (4U)
9687 #define DBGMCU_PIDR1_JEP106ID_Msk                    (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)                   /*!< 0x0000000F */
9688 #define DBGMCU_PIDR1_JEP106ID                        DBGMCU_PIDR1_JEP106ID_Msk
9689 
9690 /********************  Bit definition for DBGMCU_PIDR2 register  ************/
9691 #define DBGMCU_PIDR2_JEP106ID_Pos                     (0U)
9692 #define DBGMCU_PIDR2_JEP106ID_Msk                     (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)                    /*!< 0x00000007 */
9693 #define DBGMCU_PIDR2_JEP106ID                         DBGMCU_PIDR2_JEP106ID_Msk
9694 #define DBGMCU_PIDR2_JEDEC_Pos                        (4U)
9695 #define DBGMCU_PIDR2_JEDEC_Msk                        (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)                       /*!< 0x00000008 */
9696 #define DBGMCU_PIDR2_JEDEC                            DBGMCU_PIDR2_JEDEC_Msk
9697 #define DBGMCU_PIDR2_REVISION_Pos                     (4U)
9698 #define DBGMCU_PIDR2_REVISION_Msk                     (0xFUL << DBGMCU_PIDR2_REVISION_Pos)                    /*!< 0x000000F0 */
9699 #define DBGMCU_PIDR2_REVISION                         DBGMCU_PIDR2_REVISION_Msk
9700 
9701 /********************  Bit definition for DBGMCU_PIDR3 register  ************/
9702 #define DBGMCU_PIDR3_CMOD_Pos                         (0U)
9703 #define DBGMCU_PIDR3_CMOD_Msk                         (0xFUL << DBGMCU_PIDR3_CMOD_Pos)                            /*!< 0x0000000F */
9704 #define DBGMCU_PIDR3_CMOD                             DBGMCU_PIDR3_CMOD_Msk
9705 #define DBGMCU_PIDR3_REVAND_Pos                       (4U)
9706 #define DBGMCU_PIDR3_REVAND_Msk                       (0xFUL << DBGMCU_PIDR3_REVAND_Pos)                          /*!< 0x000000F0 */
9707 #define DBGMCU_PIDR3_REVAND                           DBGMCU_PIDR3_REVAND_Msk
9708 
9709 /********************  Bit definition for DBGMCU_CIDR0 register  ************/
9710 #define DBGMCU_CIDR0_PREAMBLE_Pos                     (0U)
9711 #define DBGMCU_CIDR0_PREAMBLE_Msk                     (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)                    /*!< 0x000000FF */
9712 #define DBGMCU_CIDR0_PREAMBLE                         DBGMCU_CIDR0_PREAMBLE_Msk
9713 
9714 /********************  Bit definition for DBGMCU_CIDR1 register  ************/
9715 #define DBGMCU_CIDR1_PREAMBLE_Pos                     (0U)
9716 #define DBGMCU_CIDR1_PREAMBLE_Msk                     (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)                    /*!< 0x0000000F */
9717 #define DBGMCU_CIDR1_PREAMBLE                         DBGMCU_CIDR1_PREAMBLE_Msk
9718 #define DBGMCU_CIDR1_CLASS_Pos                        (4U)
9719 #define DBGMCU_CIDR1_CLASS_Msk                        (0xFUL << DBGMCU_CIDR1_CLASS_Pos)                       /*!< 0x000000F0 */
9720 #define DBGMCU_CIDR1_CLASS                            DBGMCU_CIDR1_CLASS_Msk
9721 
9722 /********************  Bit definition for DBGMCU_CIDR2 register  ************/
9723 #define DBGMCU_CIDR2_PREAMBLE_Pos                     (0U)
9724 #define DBGMCU_CIDR2_PREAMBLE_Msk                     (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)                    /*!< 0x000000FF */
9725 #define DBGMCU_CIDR2_PREAMBLE                         DBGMCU_CIDR2_PREAMBLE_Msk
9726 
9727 /********************  Bit definition for DBGMCU_CIDR3 register  ************/
9728 #define DBGMCU_CIDR3_PREAMBLE_Pos                     (0U)
9729 #define DBGMCU_CIDR3_PREAMBLE_Msk                     (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)                    /*!< 0x000000FF */
9730 #define DBGMCU_CIDR3_PREAMBLE                         DBGMCU_CIDR3_PREAMBLE_Msk
9731 
9732 /**
9733   * @}
9734   */
9735 
9736 /**
9737   * @}
9738   */
9739 
9740 /** @addtogroup Exported_macros
9741   * @{
9742   */
9743 
9744 /******************************* ADC Instances ********************************/
9745 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9746 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
9747 
9748 
9749 /******************************** COMP Instances ******************************/
9750 #define IS_COMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == COMP1)
9751 
9752 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
9753 
9754 /******************************* CRC Instances ********************************/
9755 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9756 
9757 /******************************* DAC Instances ********************************/
9758 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1))
9759 
9760 /******************************** DMA Instances *******************************/
9761 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9762                                        ((INSTANCE) == DMA1_Channel2) || \
9763                                        ((INSTANCE) == DMA1_Channel3) || \
9764                                        ((INSTANCE) == DMA1_Channel4) || \
9765                                        ((INSTANCE) == DMA1_Channel5) || \
9766                                        ((INSTANCE) == DMA1_Channel6) || \
9767                                        ((INSTANCE) == DMA1_Channel7))
9768 
9769 /****************************** DMA STREAM Instances ***************************/
9770 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
9771                                           ((INSTANCE) == DMA1_Stream1)   || \
9772                                           ((INSTANCE) == DMA1_Stream2)   || \
9773                                           ((INSTANCE) == DMA1_Stream3)   || \
9774                                           ((INSTANCE) == DMA1_Stream4)   || \
9775                                           ((INSTANCE) == DMA1_Stream5)   || \
9776                                           ((INSTANCE) == DMA1_Stream6)   || \
9777                                           ((INSTANCE) == DMA1_Stream7)   || \
9778                                           ((INSTANCE) == DMA2_Stream0)   || \
9779                                           ((INSTANCE) == DMA2_Stream1)   || \
9780                                           ((INSTANCE) == DMA2_Stream2)   || \
9781                                           ((INSTANCE) == DMA2_Stream3)   || \
9782                                           ((INSTANCE) == DMA2_Stream4)   || \
9783                                           ((INSTANCE) == DMA2_Stream5)   || \
9784                                           ((INSTANCE) == DMA2_Stream6)   || \
9785                                           ((INSTANCE) == DMA2_Stream7))
9786 
9787 /******************************** DMAMUX Instances ****************************/
9788 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
9789 
9790 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX_RequestGenerator0) || \
9791                                                       ((INSTANCE) == DMAMUX_RequestGenerator1) || \
9792                                                       ((INSTANCE) == DMAMUX_RequestGenerator2) || \
9793                                                       ((INSTANCE) == DMAMUX_RequestGenerator3))
9794 
9795 /******************************* GPIO Instances *******************************/
9796 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9797                                         ((INSTANCE) == GPIOB) || \
9798                                         ((INSTANCE) == GPIOC) || \
9799                                         ((INSTANCE) == GPIOD) || \
9800                                         ((INSTANCE) == GPIOF))
9801 /******************************* GPIO AF Instances ****************************/
9802 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
9803 
9804 /**************************** GPIO Lock Instances *****************************/
9805 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9806 
9807 /******************************** I2C Instances *******************************/
9808 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9809                                        ((INSTANCE) == I2C2) || \
9810                                        ((INSTANCE) == I2C3))
9811 /************** I2C Instances : wakeup capability from stop modes *************/
9812 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9813                                                    ((INSTANCE) == I2C3))
9814 
9815 /****************************** LTDC Instances ********************************/
9816 #define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
9817 
9818 /******************************* RNG Instances ********************************/
9819 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
9820 
9821 /****************************** RTC Instances *********************************/
9822 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
9823 
9824 
9825 /******************************** SMBUS Instances *****************************/
9826 #define IS_SMBUS_INSTANCE(INSTANCE)  (((INSTANCE) == I2C1)  || \
9827                                       ((INSTANCE) == I2C3))
9828 
9829 /******************************** SPI Instances *******************************/
9830 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
9831                                        ((INSTANCE) == SPI2))
9832 
9833 /****************** LPTIM Instances : All supported instances *****************/
9834 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
9835                                          ((INSTANCE) == LPTIM2))
9836 
9837 /****************** LPTIM Instances : DMA supported instances *****************/
9838 #define IS_LPTIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
9839                                              ((INSTANCE) == LPTIM2))
9840 
9841 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
9842 #define IS_LPTIM_CC1_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
9843                                              ((INSTANCE) == LPTIM2))
9844 
9845 
9846 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
9847 #define IS_LPTIM_CC2_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
9848                                              ((INSTANCE) == LPTIM2))
9849 
9850 /************* LPTIM Instances : at least 3 capture/compare channel ***********/
9851 #define IS_LPTIM_CC3_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
9852                                              ((INSTANCE) == LPTIM2))
9853 
9854 
9855 /************* LPTIM Instances : at least 4 capture/compare channel ***********/
9856 #define IS_LPTIM_CC4_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) ||\
9857                                              ((INSTANCE) == LPTIM2))
9858 
9859 /****************** LPTIM Instances : supporting encoder interface **************/
9860 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)    ((INSTANCE) == LPTIM1)
9861 
9862 /****************** LPTIM Instances : supporting Input Capture **************/
9863 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)    (((INSTANCE) == LPTIM1) ||\
9864                                                       ((INSTANCE) == LPTIM2))
9865 
9866 /****************** TIM Instances : All supported instances *******************/
9867 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
9868                                          ((INSTANCE) == TIM2)   || \
9869                                          ((INSTANCE) == TIM3)   || \
9870                                          ((INSTANCE) == TIM6)   || \
9871                                          ((INSTANCE) == TIM7)   || \
9872                                          ((INSTANCE) == TIM15)  || \
9873                                          ((INSTANCE) == TIM16))
9874 
9875 /****************** TIM Instances : supporting 32 bits counter ****************/
9876 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
9877 
9878 /****************** TIM Instances : supporting the break function *************/
9879 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
9880                                             ((INSTANCE) == TIM15)   || \
9881                                             ((INSTANCE) == TIM16))
9882 
9883 /************** TIM Instances : supporting Break source selection *************/
9884 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
9885                                                ((INSTANCE) == TIM15)  || \
9886                                                ((INSTANCE) == TIM16))
9887 
9888 /****************** TIM Instances : supporting 2 break inputs *****************/
9889 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
9890 
9891 /************* TIM Instances : at least 1 capture/compare channel *************/
9892 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
9893                                          ((INSTANCE) == TIM2)   || \
9894                                          ((INSTANCE) == TIM3)   || \
9895                                          ((INSTANCE) == TIM15)  || \
9896                                          ((INSTANCE) == TIM16))
9897 
9898 /************ TIM Instances : at least 2 capture/compare channels *************/
9899 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
9900                                          ((INSTANCE) == TIM2)   || \
9901                                          ((INSTANCE) == TIM3)   || \
9902                                          ((INSTANCE) == TIM15))
9903 
9904 /************ TIM Instances : at least 3 capture/compare channels *************/
9905 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
9906                                          ((INSTANCE) == TIM2)   || \
9907                                          ((INSTANCE) == TIM3))
9908 
9909 /************ TIM Instances : at least 4 capture/compare channels *************/
9910 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
9911                                          ((INSTANCE) == TIM2)   || \
9912                                          ((INSTANCE) == TIM3))
9913 
9914 /****************** TIM Instances : at least 5 capture/compare channels *******/
9915 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
9916 
9917 /****************** TIM Instances : at least 6 capture/compare channels *******/
9918 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
9919 
9920 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
9921 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
9922                                             ((INSTANCE) == TIM15)  || \
9923                                             ((INSTANCE) == TIM16))
9924 
9925 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
9926 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
9927                                             ((INSTANCE) == TIM2)   || \
9928                                             ((INSTANCE) == TIM3)   || \
9929                                             ((INSTANCE) == TIM6)   || \
9930                                             ((INSTANCE) == TIM7)   || \
9931                                             ((INSTANCE) == TIM15)  || \
9932                                             ((INSTANCE) == TIM16))
9933 
9934 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
9935 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
9936                                             ((INSTANCE) == TIM2)   || \
9937                                             ((INSTANCE) == TIM3)   || \
9938                                             ((INSTANCE) == TIM15)  || \
9939                                             ((INSTANCE) == TIM16))
9940 
9941 /******************** TIM Instances : DMA burst feature ***********************/
9942 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
9943                                             ((INSTANCE) == TIM2)   || \
9944                                             ((INSTANCE) == TIM3)   || \
9945                                             ((INSTANCE) == TIM15)  || \
9946                                             ((INSTANCE) == TIM16))
9947 
9948 /******************* TIM Instances : output(s) available **********************/
9949 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
9950     ((((INSTANCE) == TIM1) &&                  \
9951      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9952       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9953       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9954       ((CHANNEL) == TIM_CHANNEL_4) ||          \
9955       ((CHANNEL) == TIM_CHANNEL_5) ||          \
9956       ((CHANNEL) == TIM_CHANNEL_6)))           \
9957      ||                                        \
9958      (((INSTANCE) == TIM2) &&                  \
9959      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9960       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9961       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9962       ((CHANNEL) == TIM_CHANNEL_4)))           \
9963      ||                                        \
9964      (((INSTANCE) == TIM3) &&                  \
9965      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9966       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9967       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9968       ((CHANNEL) == TIM_CHANNEL_4)))           \
9969      ||                                        \
9970      (((INSTANCE) == TIM15) &&                 \
9971      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9972       ((CHANNEL) == TIM_CHANNEL_2)))           \
9973      ||                                        \
9974      (((INSTANCE) == TIM16) &&                 \
9975      (((CHANNEL) == TIM_CHANNEL_1))))
9976 
9977 /****************** TIM Instances : supporting complementary output(s) ********/
9978 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
9979    ((((INSTANCE) == TIM1) &&                    \
9980      (((CHANNEL) == TIM_CHANNEL_1) ||           \
9981       ((CHANNEL) == TIM_CHANNEL_2) ||           \
9982       ((CHANNEL) == TIM_CHANNEL_3)))            \
9983     ||                                          \
9984     (((INSTANCE) == TIM15) &&                   \
9985      ((CHANNEL) == TIM_CHANNEL_1))              \
9986     ||                                          \
9987     (((INSTANCE) == TIM16) &&                   \
9988      ((CHANNEL) == TIM_CHANNEL_1)))
9989 
9990 /****************** TIM Instances : supporting clock division *****************/
9991 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
9992                                                     ((INSTANCE) == TIM2)    || \
9993                                                     ((INSTANCE) == TIM3)    || \
9994                                                     ((INSTANCE) == TIM15)   || \
9995                                                     ((INSTANCE) == TIM16))
9996 
9997 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
9998 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9999                                                         ((INSTANCE) == TIM2) || \
10000                                                         ((INSTANCE) == TIM3))
10001 
10002 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
10003 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10004                                                         ((INSTANCE) == TIM2) || \
10005                                                         ((INSTANCE) == TIM3))
10006 
10007 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
10008 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
10009                                                         ((INSTANCE) == TIM2) || \
10010                                                         ((INSTANCE) == TIM3) || \
10011                                                         ((INSTANCE) == TIM15))
10012 
10013 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
10014 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
10015                                                         ((INSTANCE) == TIM2) || \
10016                                                         ((INSTANCE) == TIM3) || \
10017                                                         ((INSTANCE) == TIM15))
10018 
10019 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
10020 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10021 
10022 /****************** TIM Instances : supporting commutation event generation ***/
10023 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10024                                                      ((INSTANCE) == TIM15)  || \
10025                                                      ((INSTANCE) == TIM16))
10026 
10027 /****************** TIM Instances : supporting counting mode selection ********/
10028 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
10029                                                         ((INSTANCE) == TIM2) || \
10030                                                         ((INSTANCE) == TIM3))
10031 
10032 /****************** TIM Instances : supporting encoder interface **************/
10033 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
10034                                                       ((INSTANCE) == TIM2)  || \
10035                                                       ((INSTANCE) == TIM3))
10036 
10037 /****************** TIM Instances : supporting Hall sensor interface **********/
10038 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10039                                                          ((INSTANCE) == TIM2)   || \
10040                                                          ((INSTANCE) == TIM3))
10041 
10042 /**************** TIM Instances : external trigger input available ************/
10043 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
10044                                             ((INSTANCE) == TIM2)  || \
10045                                             ((INSTANCE) == TIM3))
10046 
10047 /************* TIM Instances : supporting ETR source selection ***************/
10048 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10049                                              ((INSTANCE) == TIM2)  || \
10050                                              ((INSTANCE) == TIM3))
10051 
10052 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
10053 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
10054                                             ((INSTANCE) == TIM2)  || \
10055                                             ((INSTANCE) == TIM3)  || \
10056                                             ((INSTANCE) == TIM6)  || \
10057                                             ((INSTANCE) == TIM7)  || \
10058                                             ((INSTANCE) == TIM15))
10059 
10060 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10061 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10062                                             ((INSTANCE) == TIM2)  || \
10063                                             ((INSTANCE) == TIM3)  || \
10064                                             ((INSTANCE) == TIM15))
10065 
10066 /****************** TIM Instances : supporting OCxREF clear *******************/
10067 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
10068                                                        ((INSTANCE) == TIM2) || \
10069                                                        ((INSTANCE) == TIM3))
10070 
10071 /******** TIM Instances : supporting bitfield OCCS in SMCR register ***********/
10072 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
10073                                                        ((INSTANCE) == TIM2)  || \
10074                                                        ((INSTANCE) == TIM3))
10075 
10076 /****************** TIM Instances : remapping capability **********************/
10077 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10078                                             ((INSTANCE) == TIM2)  || \
10079                                             ((INSTANCE) == TIM3))
10080 
10081 /****************** TIM Instances : supporting repetition counter *************/
10082 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
10083                                                        ((INSTANCE) == TIM15) || \
10084                                                        ((INSTANCE) == TIM16))
10085 
10086 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
10087 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10088 
10089 /******************* TIM Instances : Timer input XOR function *****************/
10090 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
10091                                             ((INSTANCE) == TIM2)   || \
10092                                             ((INSTANCE) == TIM3)   || \
10093                                             ((INSTANCE) == TIM15))
10094 
10095 /******************* TIM Instances : Timer input selection ********************/
10096 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10097                                          ((INSTANCE) == TIM2)   || \
10098                                          ((INSTANCE) == TIM3)   || \
10099                                          ((INSTANCE) == TIM15)  || \
10100                                          ((INSTANCE) == TIM16))
10101 
10102 /************ TIM Instances : Advanced timers  ********************************/
10103 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10104 
10105 /****************************** TSC Instances *********************************/
10106 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
10107 
10108 /******************** USART Instances : Synchronous mode **********************/
10109 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10110                                      ((INSTANCE) == USART2) || \
10111                                      ((INSTANCE) == USART3) || \
10112                                      ((INSTANCE) == USART4))
10113 
10114 
10115 /******************** USART Instances : SPI slave mode ************************/
10116 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10117                                               ((INSTANCE) == USART2) || \
10118                                               ((INSTANCE) == USART3) || \
10119                                               ((INSTANCE) == USART4))
10120 
10121 /******************** UART Instances : Asynchronous mode **********************/
10122 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
10123                                     ((INSTANCE) == USART2)  || \
10124                                     ((INSTANCE) == USART3)  || \
10125                                     ((INSTANCE) == USART4))
10126 
10127 /******************** UART Instances : FIFO mode.******************************/
10128 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
10129                                          ((INSTANCE) == USART2)  || \
10130                                          ((INSTANCE) == LPUART1) || \
10131                                          ((INSTANCE) == LPUART2))
10132 
10133 /****************** UART Instances : Auto Baud Rate detection *****************/
10134 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10135                                                             ((INSTANCE) == USART2))
10136 
10137 /*********************** UART Instances : Driver Enable ***********************/
10138 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
10139                                                   ((INSTANCE) == USART2)  || \
10140                                                   ((INSTANCE) == USART3)  || \
10141                                                   ((INSTANCE) == USART4)  || \
10142                                                   ((INSTANCE) == LPUART1) || \
10143                                                   ((INSTANCE) == LPUART2))
10144 
10145 /********************* UART Instances : Half-Duplex mode **********************/
10146 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
10147                                                ((INSTANCE) == USART2)  || \
10148                                                ((INSTANCE) == USART3)  || \
10149                                                ((INSTANCE) == USART4)  || \
10150                                                ((INSTANCE) == LPUART1) || \
10151                                                ((INSTANCE) == LPUART2))
10152 
10153 /******************* UART Instances : Hardware Flow control *******************/
10154 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1)  || \
10155                                            ((INSTANCE) == USART2)  || \
10156                                            ((INSTANCE) == USART3)  || \
10157                                            ((INSTANCE) == USART4)  || \
10158                                            ((INSTANCE) == LPUART1) || \
10159                                            ((INSTANCE) == LPUART2))
10160 
10161 /******************** UART Instances : Wake-up from Stop mode **********************/
10162 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10163                                                       ((INSTANCE) == USART2) || \
10164                                                       ((INSTANCE) == LPUART1)|| \
10165                                                       ((INSTANCE) == LPUART2))
10166 
10167 /************************* UART Instances : LIN mode **************************/
10168 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10169                                         ((INSTANCE) == USART2))
10170 
10171 /************************* UART Instances : IRDA mode *************************/
10172 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10173                                     ((INSTANCE) == USART2))
10174 
10175 /********************* USART Instances : Smard card mode **********************/
10176 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10177                                          ((INSTANCE) == USART2))
10178 
10179 /****************************** LPUART Instance *******************************/
10180 #define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1) || \
10181                                       ((INSTANCE) == LPUART2))
10182 
10183 /****************************** IWDG Instances ********************************/
10184 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
10185 
10186 
10187 /****************************** WWDG Instances ********************************/
10188 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
10189 
10190 /****************************** OPAMP Instances *******************************/
10191 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
10192 
10193 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP_COMMON)
10194 
10195 
10196 /******************************************************************************/
10197 
10198 
10199 
10200 /**
10201   * @}
10202   */
10203 
10204 /**
10205   * @}
10206   */
10207 
10208 #ifdef __cplusplus
10209 }
10210 #endif /* __cplusplus */
10211 
10212 #endif /* STM32U031xx_H */
10213 /**
10214   * @}
10215   */
10216