1 /** 2 ****************************************************************************** 3 * @file stm32f048xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F0xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2016 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 /** @addtogroup CMSIS 27 * @{ 28 */ 29 30 /** @addtogroup stm32f048xx 31 * @{ 32 */ 33 34 #ifndef __STM32F048xx_H 35 #define __STM32F048xx_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** @addtogroup Configuration_section_for_CMSIS 42 * @{ 43 */ 44 /** 45 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals 46 */ 47 #define __CM0_REV 0 /*!< Core Revision r0p0 */ 48 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ 49 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 51 52 /** 53 * @} 54 */ 55 56 /** @addtogroup Peripheral_interrupt_number_definition 57 * @{ 58 */ 59 60 /** 61 * @brief STM32F0xx Interrupt Number Definition, according to the selected device 62 * in @ref Library_configuration_section 63 */ 64 65 /*!< Interrupt Number Definition */ 66 typedef enum 67 { 68 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ 69 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 70 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 71 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 72 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 73 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 74 75 /****** STM32F0 specific Interrupt Numbers ******************************************************************/ 76 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 77 VDDIO2_IRQn = 1, /*!< VDDIO2 Interrupt through EXTI Line 31 */ 78 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 79 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 80 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ 81 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ 82 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ 83 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ 84 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ 85 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 86 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ 87 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ 88 ADC1_IRQn = 12, /*!< ADC1 Interrupt */ 89 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ 90 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 91 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ 92 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 93 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 94 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 95 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 96 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 97 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 98 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 99 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 100 USART2_IRQn = 28, /*!< USART2 global Interrupt */ 101 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ 102 USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ 103 } IRQn_Type; 104 105 /** 106 * @} 107 */ 108 109 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ 110 #include "system_stm32f0xx.h" /* STM32F0xx System Header */ 111 #include <stdint.h> 112 113 /** @addtogroup Peripheral_registers_structures 114 * @{ 115 */ 116 117 /** 118 * @brief Analog to Digital Converter 119 */ 120 121 typedef struct 122 { 123 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 124 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 125 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 126 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 127 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 128 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 129 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 130 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 131 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 132 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 133 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 134 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 135 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 136 } ADC_TypeDef; 137 138 typedef struct 139 { 140 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 141 } ADC_Common_TypeDef; 142 143 /** 144 * @brief Controller Area Network TxMailBox 145 */ 146 typedef struct 147 { 148 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 149 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 150 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 151 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 152 }CAN_TxMailBox_TypeDef; 153 154 /** 155 * @brief Controller Area Network FIFOMailBox 156 */ 157 typedef struct 158 { 159 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 160 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 161 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 162 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 163 }CAN_FIFOMailBox_TypeDef; 164 165 /** 166 * @brief Controller Area Network FilterRegister 167 */ 168 typedef struct 169 { 170 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 171 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 172 }CAN_FilterRegister_TypeDef; 173 174 /** 175 * @brief Controller Area Network 176 */ 177 typedef struct 178 { 179 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 180 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 181 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 182 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 183 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 184 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 185 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 186 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 187 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 188 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 189 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 190 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 191 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 192 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 193 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 194 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 195 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 196 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 197 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 198 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 199 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 200 CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN Filter Register, Address offset: 0x240-0x2AC */ 201 }CAN_TypeDef; 202 203 /** 204 * @brief HDMI-CEC 205 */ 206 207 typedef struct 208 { 209 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ 210 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ 211 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ 212 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ 213 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ 214 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ 215 }CEC_TypeDef; 216 217 /** 218 * @brief CRC calculation unit 219 */ 220 221 typedef struct 222 { 223 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 224 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 225 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 226 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 227 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 228 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 229 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 230 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ 231 } CRC_TypeDef; 232 233 /** 234 * @brief Clock Recovery System 235 */ 236 typedef struct 237 { 238 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ 239 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ 240 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ 241 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ 242 }CRS_TypeDef; 243 244 /** 245 * @brief Debug MCU 246 */ 247 248 typedef struct 249 { 250 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 251 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 252 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 253 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 254 }DBGMCU_TypeDef; 255 256 /** 257 * @brief DMA Controller 258 */ 259 260 typedef struct 261 { 262 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 263 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 264 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 265 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 266 } DMA_Channel_TypeDef; 267 268 typedef struct 269 { 270 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 271 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 272 } DMA_TypeDef; 273 274 /** 275 * @brief External Interrupt/Event Controller 276 */ 277 278 typedef struct 279 { 280 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 281 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 282 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 283 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 284 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 285 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 286 } EXTI_TypeDef; 287 288 /** 289 * @brief FLASH Registers 290 */ 291 typedef struct 292 { 293 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ 294 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ 295 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ 296 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ 297 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ 298 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ 299 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ 300 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ 301 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ 302 } FLASH_TypeDef; 303 304 /** 305 * @brief Option Bytes Registers 306 */ 307 typedef struct 308 { 309 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ 310 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ 311 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ 312 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ 313 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ 314 } OB_TypeDef; 315 316 /** 317 * @brief General Purpose I/O 318 */ 319 320 typedef struct 321 { 322 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 323 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 324 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 325 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 326 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 327 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 328 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ 329 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 330 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ 331 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 332 } GPIO_TypeDef; 333 334 /** 335 * @brief SysTem Configuration 336 */ 337 338 typedef struct 339 { 340 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 341 uint32_t RESERVED; /*!< Reserved, 0x04 */ 342 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 343 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 344 } SYSCFG_TypeDef; 345 346 /** 347 * @brief Inter-integrated Circuit Interface 348 */ 349 350 typedef struct 351 { 352 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 353 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 354 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 355 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 356 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 357 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 358 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 359 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 360 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 361 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 362 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 363 } I2C_TypeDef; 364 365 /** 366 * @brief Independent WATCHDOG 367 */ 368 369 typedef struct 370 { 371 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 372 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 373 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 374 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 375 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 376 } IWDG_TypeDef; 377 378 /** 379 * @brief Power Control 380 */ 381 382 typedef struct 383 { 384 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 385 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 386 } PWR_TypeDef; 387 388 /** 389 * @brief Reset and Clock Control 390 */ 391 392 typedef struct 393 { 394 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 395 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 396 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 397 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 398 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 399 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 400 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 401 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 402 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 403 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 404 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 405 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 406 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 407 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ 408 } RCC_TypeDef; 409 410 /** 411 * @brief Real-Time Clock 412 */ 413 typedef struct 414 { 415 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 416 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 417 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 418 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 419 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 420 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 421 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ 422 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 423 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ 424 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 425 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 426 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 427 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 428 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 429 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 430 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 431 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 432 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 433 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */ 434 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */ 435 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 436 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 437 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 438 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 439 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 440 } RTC_TypeDef; 441 442 /** 443 * @brief Serial Peripheral Interface 444 */ 445 446 typedef struct 447 { 448 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 449 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 450 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 451 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 452 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 453 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 454 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 455 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 456 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 457 } SPI_TypeDef; 458 459 /** 460 * @brief TIM 461 */ 462 typedef struct 463 { 464 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 465 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 466 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 467 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 468 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 469 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 470 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 471 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 472 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 473 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 474 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 475 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 476 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 477 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 478 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 479 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 480 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 481 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 482 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 483 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 484 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 485 } TIM_TypeDef; 486 487 /** 488 * @brief Touch Sensing Controller (TSC) 489 */ 490 typedef struct 491 { 492 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 493 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 494 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 495 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 496 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 497 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 498 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 499 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 500 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 501 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 502 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 503 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 504 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 505 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ 506 }TSC_TypeDef; 507 508 /** 509 * @brief Universal Synchronous Asynchronous Receiver Transmitter 510 */ 511 512 typedef struct 513 { 514 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 515 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 516 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 517 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 518 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 519 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 520 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 521 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 522 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 523 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 524 uint16_t RESERVED1; /*!< Reserved, 0x26 */ 525 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 526 uint16_t RESERVED2; /*!< Reserved, 0x2A */ 527 } USART_TypeDef; 528 529 /** 530 * @brief Universal Serial Bus Full Speed Device 531 */ 532 533 typedef struct 534 { 535 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 536 __IO uint16_t RESERVED0; /*!< Reserved */ 537 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 538 __IO uint16_t RESERVED1; /*!< Reserved */ 539 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 540 __IO uint16_t RESERVED2; /*!< Reserved */ 541 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 542 __IO uint16_t RESERVED3; /*!< Reserved */ 543 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 544 __IO uint16_t RESERVED4; /*!< Reserved */ 545 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 546 __IO uint16_t RESERVED5; /*!< Reserved */ 547 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 548 __IO uint16_t RESERVED6; /*!< Reserved */ 549 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 550 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 551 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 552 __IO uint16_t RESERVED8; /*!< Reserved */ 553 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 554 __IO uint16_t RESERVED9; /*!< Reserved */ 555 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 556 __IO uint16_t RESERVEDA; /*!< Reserved */ 557 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 558 __IO uint16_t RESERVEDB; /*!< Reserved */ 559 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 560 __IO uint16_t RESERVEDC; /*!< Reserved */ 561 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ 562 __IO uint16_t RESERVEDD; /*!< Reserved */ 563 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ 564 __IO uint16_t RESERVEDE; /*!< Reserved */ 565 } USB_TypeDef; 566 567 /** 568 * @brief Window WATCHDOG 569 */ 570 typedef struct 571 { 572 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 573 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 574 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 575 } WWDG_TypeDef; 576 577 /** 578 * @} 579 */ 580 581 /** @addtogroup Peripheral_memory_map 582 * @{ 583 */ 584 585 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 586 #define FLASH_BANK1_END 0x08007FFFUL /*!< FLASH END address of bank1 */ 587 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 588 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 589 590 /*!< Peripheral memory map */ 591 #define APBPERIPH_BASE PERIPH_BASE 592 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 593 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 594 595 /*!< APB peripherals */ 596 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) 597 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 598 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) 599 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 600 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 601 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 602 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) 603 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 604 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 605 #define USB_BASE (APBPERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ 606 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ 607 #define CAN_BASE (APBPERIPH_BASE + 0x00006400UL) 608 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL) 609 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 610 #define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) 611 612 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 613 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) 614 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 615 #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) 616 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) 617 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 618 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 619 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) 620 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) 621 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) 622 623 /*!< AHB peripherals */ 624 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 625 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 626 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 627 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 628 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 629 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 630 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 631 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 632 633 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 634 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ 635 #define OB_BASE 0x1FFFF800UL /*!< FLASH Option Bytes base address */ 636 #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ 637 #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ 638 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 639 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL) 640 641 /*!< AHB2 peripherals */ 642 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) 643 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) 644 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) 645 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) 646 647 /** 648 * @} 649 */ 650 651 /** @addtogroup Peripheral_declaration 652 * @{ 653 */ 654 655 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 656 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 657 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 658 #define RTC ((RTC_TypeDef *) RTC_BASE) 659 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 660 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 661 #define USART2 ((USART_TypeDef *) USART2_BASE) 662 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 663 #define CAN ((CAN_TypeDef *) CAN_BASE) 664 #define CRS ((CRS_TypeDef *) CRS_BASE) 665 #define PWR ((PWR_TypeDef *) PWR_BASE) 666 #define CEC ((CEC_TypeDef *) CEC_BASE) 667 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 668 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 669 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 670 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 671 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ 672 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 673 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 674 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 675 #define USART1 ((USART_TypeDef *) USART1_BASE) 676 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 677 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 678 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 679 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 680 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 681 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 682 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 683 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 684 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 685 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 686 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 687 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 688 #define OB ((OB_TypeDef *) OB_BASE) 689 #define RCC ((RCC_TypeDef *) RCC_BASE) 690 #define CRC ((CRC_TypeDef *) CRC_BASE) 691 #define TSC ((TSC_TypeDef *) TSC_BASE) 692 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 693 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 694 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 695 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 696 #define USB ((USB_TypeDef *) USB_BASE) 697 /** 698 * @} 699 */ 700 701 /** @addtogroup Exported_constants 702 * @{ 703 */ 704 705 /** @addtogroup Hardware_Constant_Definition 706 * @{ 707 */ 708 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 709 710 /** 711 * @} 712 */ 713 714 /** @addtogroup Peripheral_Registers_Bits_Definition 715 * @{ 716 */ 717 718 /******************************************************************************/ 719 /* Peripheral Registers Bits Definition */ 720 /******************************************************************************/ 721 722 /******************************************************************************/ 723 /* */ 724 /* Analog to Digital Converter (ADC) */ 725 /* */ 726 /******************************************************************************/ 727 728 /* 729 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 730 */ 731 #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ 732 733 /******************** Bits definition for ADC_ISR register ******************/ 734 #define ADC_ISR_ADRDY_Pos (0U) 735 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 736 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 737 #define ADC_ISR_EOSMP_Pos (1U) 738 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 739 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 740 #define ADC_ISR_EOC_Pos (2U) 741 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 742 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 743 #define ADC_ISR_EOS_Pos (3U) 744 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 745 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 746 #define ADC_ISR_OVR_Pos (4U) 747 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 748 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 749 #define ADC_ISR_AWD1_Pos (7U) 750 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 751 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 752 753 /* Legacy defines */ 754 #define ADC_ISR_AWD (ADC_ISR_AWD1) 755 #define ADC_ISR_EOSEQ (ADC_ISR_EOS) 756 757 /******************** Bits definition for ADC_IER register ******************/ 758 #define ADC_IER_ADRDYIE_Pos (0U) 759 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 760 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 761 #define ADC_IER_EOSMPIE_Pos (1U) 762 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 763 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 764 #define ADC_IER_EOCIE_Pos (2U) 765 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 766 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 767 #define ADC_IER_EOSIE_Pos (3U) 768 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 769 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 770 #define ADC_IER_OVRIE_Pos (4U) 771 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 772 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 773 #define ADC_IER_AWD1IE_Pos (7U) 774 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 775 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 776 777 /* Legacy defines */ 778 #define ADC_IER_AWDIE (ADC_IER_AWD1IE) 779 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) 780 781 /******************** Bits definition for ADC_CR register *******************/ 782 #define ADC_CR_ADEN_Pos (0U) 783 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 784 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 785 #define ADC_CR_ADDIS_Pos (1U) 786 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 787 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 788 #define ADC_CR_ADSTART_Pos (2U) 789 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 790 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 791 #define ADC_CR_ADSTP_Pos (4U) 792 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 793 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 794 #define ADC_CR_ADCAL_Pos (31U) 795 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 796 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 797 798 /******************* Bits definition for ADC_CFGR1 register *****************/ 799 #define ADC_CFGR1_DMAEN_Pos (0U) 800 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 801 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 802 #define ADC_CFGR1_DMACFG_Pos (1U) 803 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 804 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 805 #define ADC_CFGR1_SCANDIR_Pos (2U) 806 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 807 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 808 809 #define ADC_CFGR1_RES_Pos (3U) 810 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 811 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 812 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 813 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 814 815 #define ADC_CFGR1_ALIGN_Pos (5U) 816 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 817 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 818 819 #define ADC_CFGR1_EXTSEL_Pos (6U) 820 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 821 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 822 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 823 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 824 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 825 826 #define ADC_CFGR1_EXTEN_Pos (10U) 827 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 828 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 829 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 830 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 831 832 #define ADC_CFGR1_OVRMOD_Pos (12U) 833 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 834 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 835 #define ADC_CFGR1_CONT_Pos (13U) 836 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 837 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 838 #define ADC_CFGR1_WAIT_Pos (14U) 839 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 840 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 841 #define ADC_CFGR1_AUTOFF_Pos (15U) 842 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 843 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 844 #define ADC_CFGR1_DISCEN_Pos (16U) 845 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 846 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 847 848 #define ADC_CFGR1_AWD1SGL_Pos (22U) 849 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 850 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 851 #define ADC_CFGR1_AWD1EN_Pos (23U) 852 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 853 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 854 855 #define ADC_CFGR1_AWD1CH_Pos (26U) 856 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 857 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 858 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 859 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 860 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 861 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 862 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 863 864 /* Legacy defines */ 865 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) 866 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) 867 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) 868 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) 869 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) 870 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) 871 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) 872 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) 873 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) 874 875 /******************* Bits definition for ADC_CFGR2 register *****************/ 876 #define ADC_CFGR2_CKMODE_Pos (30U) 877 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 878 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 879 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 880 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 881 882 /* Legacy defines */ 883 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ 884 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ 885 886 /****************** Bit definition for ADC_SMPR register ********************/ 887 #define ADC_SMPR_SMP_Pos (0U) 888 #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 889 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ 890 #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 891 #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 892 #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 893 894 /* Legacy defines */ 895 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ 896 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ 897 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ 898 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ 899 900 /******************* Bit definition for ADC_TR register ********************/ 901 #define ADC_TR1_LT1_Pos (0U) 902 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 903 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 904 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 905 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 906 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 907 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 908 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 909 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 910 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 911 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 912 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 913 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 914 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 915 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 916 917 #define ADC_TR1_HT1_Pos (16U) 918 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 919 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 920 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 921 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 922 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 923 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 924 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 925 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 926 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 927 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 928 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 929 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 930 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 931 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 932 933 /* Legacy defines */ 934 #define ADC_TR_HT (ADC_TR1_HT1) 935 #define ADC_TR_LT (ADC_TR1_LT1) 936 #define ADC_HTR_HT (ADC_TR1_HT1) 937 #define ADC_LTR_LT (ADC_TR1_LT1) 938 939 /****************** Bit definition for ADC_CHSELR register ******************/ 940 #define ADC_CHSELR_CHSEL_Pos (0U) 941 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 942 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 943 #define ADC_CHSELR_CHSEL18_Pos (18U) 944 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 945 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ 946 #define ADC_CHSELR_CHSEL17_Pos (17U) 947 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 948 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 949 #define ADC_CHSELR_CHSEL16_Pos (16U) 950 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 951 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 952 #define ADC_CHSELR_CHSEL15_Pos (15U) 953 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 954 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 955 #define ADC_CHSELR_CHSEL14_Pos (14U) 956 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 957 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 958 #define ADC_CHSELR_CHSEL13_Pos (13U) 959 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 960 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 961 #define ADC_CHSELR_CHSEL12_Pos (12U) 962 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 963 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 964 #define ADC_CHSELR_CHSEL11_Pos (11U) 965 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 966 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 967 #define ADC_CHSELR_CHSEL10_Pos (10U) 968 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 969 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 970 #define ADC_CHSELR_CHSEL9_Pos (9U) 971 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 972 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 973 #define ADC_CHSELR_CHSEL8_Pos (8U) 974 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 975 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 976 #define ADC_CHSELR_CHSEL7_Pos (7U) 977 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 978 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 979 #define ADC_CHSELR_CHSEL6_Pos (6U) 980 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 981 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 982 #define ADC_CHSELR_CHSEL5_Pos (5U) 983 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 984 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 985 #define ADC_CHSELR_CHSEL4_Pos (4U) 986 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 987 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 988 #define ADC_CHSELR_CHSEL3_Pos (3U) 989 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 990 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 991 #define ADC_CHSELR_CHSEL2_Pos (2U) 992 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 993 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 994 #define ADC_CHSELR_CHSEL1_Pos (1U) 995 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 996 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 997 #define ADC_CHSELR_CHSEL0_Pos (0U) 998 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 999 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 1000 1001 /******************** Bit definition for ADC_DR register ********************/ 1002 #define ADC_DR_DATA_Pos (0U) 1003 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1004 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1005 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 1006 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 1007 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 1008 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 1009 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 1010 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 1011 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 1012 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 1013 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 1014 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 1015 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 1016 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 1017 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 1018 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 1019 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 1020 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 1021 1022 /************************* ADC Common registers *****************************/ 1023 /******************* Bit definition for ADC_CCR register ********************/ 1024 #define ADC_CCR_VREFEN_Pos (22U) 1025 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1026 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 1027 #define ADC_CCR_TSEN_Pos (23U) 1028 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 1029 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 1030 1031 #define ADC_CCR_VBATEN_Pos (24U) 1032 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 1033 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 1034 1035 /******************************************************************************/ 1036 /* */ 1037 /* Controller Area Network (CAN ) */ 1038 /* */ 1039 /******************************************************************************/ 1040 /*!<CAN control and status registers */ 1041 /******************* Bit definition for CAN_MCR register ********************/ 1042 #define CAN_MCR_INRQ_Pos (0U) 1043 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ 1044 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ 1045 #define CAN_MCR_SLEEP_Pos (1U) 1046 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ 1047 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ 1048 #define CAN_MCR_TXFP_Pos (2U) 1049 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ 1050 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ 1051 #define CAN_MCR_RFLM_Pos (3U) 1052 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ 1053 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ 1054 #define CAN_MCR_NART_Pos (4U) 1055 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ 1056 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ 1057 #define CAN_MCR_AWUM_Pos (5U) 1058 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ 1059 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ 1060 #define CAN_MCR_ABOM_Pos (6U) 1061 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ 1062 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ 1063 #define CAN_MCR_TTCM_Pos (7U) 1064 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ 1065 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ 1066 #define CAN_MCR_RESET_Pos (15U) 1067 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ 1068 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ 1069 1070 /******************* Bit definition for CAN_MSR register ********************/ 1071 #define CAN_MSR_INAK_Pos (0U) 1072 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ 1073 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ 1074 #define CAN_MSR_SLAK_Pos (1U) 1075 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ 1076 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ 1077 #define CAN_MSR_ERRI_Pos (2U) 1078 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ 1079 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ 1080 #define CAN_MSR_WKUI_Pos (3U) 1081 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ 1082 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ 1083 #define CAN_MSR_SLAKI_Pos (4U) 1084 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ 1085 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ 1086 #define CAN_MSR_TXM_Pos (8U) 1087 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ 1088 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ 1089 #define CAN_MSR_RXM_Pos (9U) 1090 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ 1091 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ 1092 #define CAN_MSR_SAMP_Pos (10U) 1093 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ 1094 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ 1095 #define CAN_MSR_RX_Pos (11U) 1096 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ 1097 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ 1098 1099 /******************* Bit definition for CAN_TSR register ********************/ 1100 #define CAN_TSR_RQCP0_Pos (0U) 1101 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ 1102 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ 1103 #define CAN_TSR_TXOK0_Pos (1U) 1104 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ 1105 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ 1106 #define CAN_TSR_ALST0_Pos (2U) 1107 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ 1108 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ 1109 #define CAN_TSR_TERR0_Pos (3U) 1110 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ 1111 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ 1112 #define CAN_TSR_ABRQ0_Pos (7U) 1113 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ 1114 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ 1115 #define CAN_TSR_RQCP1_Pos (8U) 1116 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ 1117 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ 1118 #define CAN_TSR_TXOK1_Pos (9U) 1119 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ 1120 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ 1121 #define CAN_TSR_ALST1_Pos (10U) 1122 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ 1123 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ 1124 #define CAN_TSR_TERR1_Pos (11U) 1125 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ 1126 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ 1127 #define CAN_TSR_ABRQ1_Pos (15U) 1128 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ 1129 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ 1130 #define CAN_TSR_RQCP2_Pos (16U) 1131 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ 1132 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ 1133 #define CAN_TSR_TXOK2_Pos (17U) 1134 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ 1135 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ 1136 #define CAN_TSR_ALST2_Pos (18U) 1137 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ 1138 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ 1139 #define CAN_TSR_TERR2_Pos (19U) 1140 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ 1141 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ 1142 #define CAN_TSR_ABRQ2_Pos (23U) 1143 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ 1144 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ 1145 #define CAN_TSR_CODE_Pos (24U) 1146 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ 1147 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ 1148 1149 #define CAN_TSR_TME_Pos (26U) 1150 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ 1151 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ 1152 #define CAN_TSR_TME0_Pos (26U) 1153 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ 1154 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ 1155 #define CAN_TSR_TME1_Pos (27U) 1156 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ 1157 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ 1158 #define CAN_TSR_TME2_Pos (28U) 1159 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ 1160 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ 1161 1162 #define CAN_TSR_LOW_Pos (29U) 1163 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ 1164 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ 1165 #define CAN_TSR_LOW0_Pos (29U) 1166 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ 1167 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ 1168 #define CAN_TSR_LOW1_Pos (30U) 1169 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ 1170 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ 1171 #define CAN_TSR_LOW2_Pos (31U) 1172 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ 1173 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ 1174 1175 /******************* Bit definition for CAN_RF0R register *******************/ 1176 #define CAN_RF0R_FMP0_Pos (0U) 1177 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ 1178 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ 1179 #define CAN_RF0R_FULL0_Pos (3U) 1180 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ 1181 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ 1182 #define CAN_RF0R_FOVR0_Pos (4U) 1183 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ 1184 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ 1185 #define CAN_RF0R_RFOM0_Pos (5U) 1186 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ 1187 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ 1188 1189 /******************* Bit definition for CAN_RF1R register *******************/ 1190 #define CAN_RF1R_FMP1_Pos (0U) 1191 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ 1192 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ 1193 #define CAN_RF1R_FULL1_Pos (3U) 1194 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ 1195 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ 1196 #define CAN_RF1R_FOVR1_Pos (4U) 1197 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ 1198 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ 1199 #define CAN_RF1R_RFOM1_Pos (5U) 1200 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ 1201 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ 1202 1203 /******************** Bit definition for CAN_IER register *******************/ 1204 #define CAN_IER_TMEIE_Pos (0U) 1205 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ 1206 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ 1207 #define CAN_IER_FMPIE0_Pos (1U) 1208 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ 1209 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ 1210 #define CAN_IER_FFIE0_Pos (2U) 1211 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ 1212 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ 1213 #define CAN_IER_FOVIE0_Pos (3U) 1214 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ 1215 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ 1216 #define CAN_IER_FMPIE1_Pos (4U) 1217 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ 1218 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ 1219 #define CAN_IER_FFIE1_Pos (5U) 1220 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ 1221 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ 1222 #define CAN_IER_FOVIE1_Pos (6U) 1223 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ 1224 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ 1225 #define CAN_IER_EWGIE_Pos (8U) 1226 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ 1227 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ 1228 #define CAN_IER_EPVIE_Pos (9U) 1229 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ 1230 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ 1231 #define CAN_IER_BOFIE_Pos (10U) 1232 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ 1233 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ 1234 #define CAN_IER_LECIE_Pos (11U) 1235 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ 1236 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ 1237 #define CAN_IER_ERRIE_Pos (15U) 1238 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ 1239 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ 1240 #define CAN_IER_WKUIE_Pos (16U) 1241 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ 1242 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ 1243 #define CAN_IER_SLKIE_Pos (17U) 1244 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ 1245 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ 1246 1247 /******************** Bit definition for CAN_ESR register *******************/ 1248 #define CAN_ESR_EWGF_Pos (0U) 1249 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ 1250 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ 1251 #define CAN_ESR_EPVF_Pos (1U) 1252 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ 1253 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ 1254 #define CAN_ESR_BOFF_Pos (2U) 1255 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ 1256 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ 1257 1258 #define CAN_ESR_LEC_Pos (4U) 1259 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ 1260 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ 1261 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ 1262 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ 1263 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ 1264 1265 #define CAN_ESR_TEC_Pos (16U) 1266 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ 1267 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ 1268 #define CAN_ESR_REC_Pos (24U) 1269 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ 1270 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ 1271 1272 /******************* Bit definition for CAN_BTR register ********************/ 1273 #define CAN_BTR_BRP_Pos (0U) 1274 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ 1275 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ 1276 #define CAN_BTR_TS1_Pos (16U) 1277 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ 1278 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ 1279 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ 1280 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ 1281 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ 1282 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ 1283 #define CAN_BTR_TS2_Pos (20U) 1284 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ 1285 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ 1286 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ 1287 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ 1288 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ 1289 #define CAN_BTR_SJW_Pos (24U) 1290 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ 1291 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ 1292 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ 1293 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ 1294 #define CAN_BTR_LBKM_Pos (30U) 1295 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ 1296 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ 1297 #define CAN_BTR_SILM_Pos (31U) 1298 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ 1299 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ 1300 1301 /*!<Mailbox registers */ 1302 /****************** Bit definition for CAN_TI0R register ********************/ 1303 #define CAN_TI0R_TXRQ_Pos (0U) 1304 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ 1305 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ 1306 #define CAN_TI0R_RTR_Pos (1U) 1307 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ 1308 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ 1309 #define CAN_TI0R_IDE_Pos (2U) 1310 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ 1311 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ 1312 #define CAN_TI0R_EXID_Pos (3U) 1313 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ 1314 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ 1315 #define CAN_TI0R_STID_Pos (21U) 1316 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ 1317 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 1318 1319 /****************** Bit definition for CAN_TDT0R register *******************/ 1320 #define CAN_TDT0R_DLC_Pos (0U) 1321 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ 1322 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ 1323 #define CAN_TDT0R_TGT_Pos (8U) 1324 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ 1325 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ 1326 #define CAN_TDT0R_TIME_Pos (16U) 1327 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 1328 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ 1329 1330 /****************** Bit definition for CAN_TDL0R register *******************/ 1331 #define CAN_TDL0R_DATA0_Pos (0U) 1332 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ 1333 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ 1334 #define CAN_TDL0R_DATA1_Pos (8U) 1335 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 1336 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ 1337 #define CAN_TDL0R_DATA2_Pos (16U) 1338 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 1339 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ 1340 #define CAN_TDL0R_DATA3_Pos (24U) 1341 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ 1342 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ 1343 1344 /****************** Bit definition for CAN_TDH0R register *******************/ 1345 #define CAN_TDH0R_DATA4_Pos (0U) 1346 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ 1347 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ 1348 #define CAN_TDH0R_DATA5_Pos (8U) 1349 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 1350 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ 1351 #define CAN_TDH0R_DATA6_Pos (16U) 1352 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 1353 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ 1354 #define CAN_TDH0R_DATA7_Pos (24U) 1355 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ 1356 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ 1357 1358 /******************* Bit definition for CAN_TI1R register *******************/ 1359 #define CAN_TI1R_TXRQ_Pos (0U) 1360 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ 1361 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ 1362 #define CAN_TI1R_RTR_Pos (1U) 1363 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ 1364 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ 1365 #define CAN_TI1R_IDE_Pos (2U) 1366 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ 1367 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ 1368 #define CAN_TI1R_EXID_Pos (3U) 1369 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ 1370 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ 1371 #define CAN_TI1R_STID_Pos (21U) 1372 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ 1373 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 1374 1375 /******************* Bit definition for CAN_TDT1R register ******************/ 1376 #define CAN_TDT1R_DLC_Pos (0U) 1377 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ 1378 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ 1379 #define CAN_TDT1R_TGT_Pos (8U) 1380 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ 1381 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ 1382 #define CAN_TDT1R_TIME_Pos (16U) 1383 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 1384 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ 1385 1386 /******************* Bit definition for CAN_TDL1R register ******************/ 1387 #define CAN_TDL1R_DATA0_Pos (0U) 1388 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ 1389 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ 1390 #define CAN_TDL1R_DATA1_Pos (8U) 1391 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 1392 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ 1393 #define CAN_TDL1R_DATA2_Pos (16U) 1394 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 1395 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ 1396 #define CAN_TDL1R_DATA3_Pos (24U) 1397 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ 1398 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ 1399 1400 /******************* Bit definition for CAN_TDH1R register ******************/ 1401 #define CAN_TDH1R_DATA4_Pos (0U) 1402 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ 1403 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ 1404 #define CAN_TDH1R_DATA5_Pos (8U) 1405 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 1406 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ 1407 #define CAN_TDH1R_DATA6_Pos (16U) 1408 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 1409 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ 1410 #define CAN_TDH1R_DATA7_Pos (24U) 1411 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ 1412 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ 1413 1414 /******************* Bit definition for CAN_TI2R register *******************/ 1415 #define CAN_TI2R_TXRQ_Pos (0U) 1416 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ 1417 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ 1418 #define CAN_TI2R_RTR_Pos (1U) 1419 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ 1420 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ 1421 #define CAN_TI2R_IDE_Pos (2U) 1422 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ 1423 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ 1424 #define CAN_TI2R_EXID_Pos (3U) 1425 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ 1426 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ 1427 #define CAN_TI2R_STID_Pos (21U) 1428 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ 1429 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 1430 1431 /******************* Bit definition for CAN_TDT2R register ******************/ 1432 #define CAN_TDT2R_DLC_Pos (0U) 1433 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ 1434 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ 1435 #define CAN_TDT2R_TGT_Pos (8U) 1436 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ 1437 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ 1438 #define CAN_TDT2R_TIME_Pos (16U) 1439 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ 1440 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ 1441 1442 /******************* Bit definition for CAN_TDL2R register ******************/ 1443 #define CAN_TDL2R_DATA0_Pos (0U) 1444 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ 1445 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ 1446 #define CAN_TDL2R_DATA1_Pos (8U) 1447 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ 1448 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ 1449 #define CAN_TDL2R_DATA2_Pos (16U) 1450 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ 1451 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ 1452 #define CAN_TDL2R_DATA3_Pos (24U) 1453 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ 1454 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ 1455 1456 /******************* Bit definition for CAN_TDH2R register ******************/ 1457 #define CAN_TDH2R_DATA4_Pos (0U) 1458 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ 1459 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ 1460 #define CAN_TDH2R_DATA5_Pos (8U) 1461 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ 1462 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ 1463 #define CAN_TDH2R_DATA6_Pos (16U) 1464 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ 1465 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ 1466 #define CAN_TDH2R_DATA7_Pos (24U) 1467 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ 1468 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ 1469 1470 /******************* Bit definition for CAN_RI0R register *******************/ 1471 #define CAN_RI0R_RTR_Pos (1U) 1472 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ 1473 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ 1474 #define CAN_RI0R_IDE_Pos (2U) 1475 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ 1476 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ 1477 #define CAN_RI0R_EXID_Pos (3U) 1478 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ 1479 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ 1480 #define CAN_RI0R_STID_Pos (21U) 1481 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ 1482 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 1483 1484 /******************* Bit definition for CAN_RDT0R register ******************/ 1485 #define CAN_RDT0R_DLC_Pos (0U) 1486 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ 1487 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ 1488 #define CAN_RDT0R_FMI_Pos (8U) 1489 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ 1490 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ 1491 #define CAN_RDT0R_TIME_Pos (16U) 1492 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 1493 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ 1494 1495 /******************* Bit definition for CAN_RDL0R register ******************/ 1496 #define CAN_RDL0R_DATA0_Pos (0U) 1497 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ 1498 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ 1499 #define CAN_RDL0R_DATA1_Pos (8U) 1500 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 1501 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ 1502 #define CAN_RDL0R_DATA2_Pos (16U) 1503 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 1504 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ 1505 #define CAN_RDL0R_DATA3_Pos (24U) 1506 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ 1507 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ 1508 1509 /******************* Bit definition for CAN_RDH0R register ******************/ 1510 #define CAN_RDH0R_DATA4_Pos (0U) 1511 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ 1512 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ 1513 #define CAN_RDH0R_DATA5_Pos (8U) 1514 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 1515 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ 1516 #define CAN_RDH0R_DATA6_Pos (16U) 1517 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 1518 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ 1519 #define CAN_RDH0R_DATA7_Pos (24U) 1520 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ 1521 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ 1522 1523 /******************* Bit definition for CAN_RI1R register *******************/ 1524 #define CAN_RI1R_RTR_Pos (1U) 1525 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ 1526 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ 1527 #define CAN_RI1R_IDE_Pos (2U) 1528 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ 1529 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ 1530 #define CAN_RI1R_EXID_Pos (3U) 1531 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ 1532 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ 1533 #define CAN_RI1R_STID_Pos (21U) 1534 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ 1535 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 1536 1537 /******************* Bit definition for CAN_RDT1R register ******************/ 1538 #define CAN_RDT1R_DLC_Pos (0U) 1539 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ 1540 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ 1541 #define CAN_RDT1R_FMI_Pos (8U) 1542 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ 1543 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ 1544 #define CAN_RDT1R_TIME_Pos (16U) 1545 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 1546 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ 1547 1548 /******************* Bit definition for CAN_RDL1R register ******************/ 1549 #define CAN_RDL1R_DATA0_Pos (0U) 1550 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ 1551 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ 1552 #define CAN_RDL1R_DATA1_Pos (8U) 1553 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 1554 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ 1555 #define CAN_RDL1R_DATA2_Pos (16U) 1556 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 1557 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ 1558 #define CAN_RDL1R_DATA3_Pos (24U) 1559 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ 1560 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ 1561 1562 /******************* Bit definition for CAN_RDH1R register ******************/ 1563 #define CAN_RDH1R_DATA4_Pos (0U) 1564 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ 1565 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ 1566 #define CAN_RDH1R_DATA5_Pos (8U) 1567 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 1568 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ 1569 #define CAN_RDH1R_DATA6_Pos (16U) 1570 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 1571 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ 1572 #define CAN_RDH1R_DATA7_Pos (24U) 1573 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ 1574 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ 1575 1576 /*!<CAN filter registers */ 1577 /******************* Bit definition for CAN_FMR register ********************/ 1578 #define CAN_FMR_FINIT_Pos (0U) 1579 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ 1580 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ 1581 #define CAN_FMR_CAN2SB_Pos (8U) 1582 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ 1583 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */ 1584 1585 /******************* Bit definition for CAN_FM1R register *******************/ 1586 #define CAN_FM1R_FBM_Pos (0U) 1587 #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */ 1588 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ 1589 #define CAN_FM1R_FBM0_Pos (0U) 1590 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ 1591 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ 1592 #define CAN_FM1R_FBM1_Pos (1U) 1593 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ 1594 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ 1595 #define CAN_FM1R_FBM2_Pos (2U) 1596 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ 1597 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ 1598 #define CAN_FM1R_FBM3_Pos (3U) 1599 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ 1600 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ 1601 #define CAN_FM1R_FBM4_Pos (4U) 1602 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ 1603 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ 1604 #define CAN_FM1R_FBM5_Pos (5U) 1605 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ 1606 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ 1607 #define CAN_FM1R_FBM6_Pos (6U) 1608 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ 1609 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ 1610 #define CAN_FM1R_FBM7_Pos (7U) 1611 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ 1612 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ 1613 #define CAN_FM1R_FBM8_Pos (8U) 1614 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ 1615 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ 1616 #define CAN_FM1R_FBM9_Pos (9U) 1617 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ 1618 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ 1619 #define CAN_FM1R_FBM10_Pos (10U) 1620 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ 1621 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ 1622 #define CAN_FM1R_FBM11_Pos (11U) 1623 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ 1624 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ 1625 #define CAN_FM1R_FBM12_Pos (12U) 1626 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ 1627 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ 1628 #define CAN_FM1R_FBM13_Pos (13U) 1629 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ 1630 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ 1631 1632 /******************* Bit definition for CAN_FS1R register *******************/ 1633 #define CAN_FS1R_FSC_Pos (0U) 1634 #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */ 1635 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ 1636 #define CAN_FS1R_FSC0_Pos (0U) 1637 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ 1638 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ 1639 #define CAN_FS1R_FSC1_Pos (1U) 1640 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ 1641 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ 1642 #define CAN_FS1R_FSC2_Pos (2U) 1643 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ 1644 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ 1645 #define CAN_FS1R_FSC3_Pos (3U) 1646 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ 1647 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ 1648 #define CAN_FS1R_FSC4_Pos (4U) 1649 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ 1650 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ 1651 #define CAN_FS1R_FSC5_Pos (5U) 1652 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ 1653 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ 1654 #define CAN_FS1R_FSC6_Pos (6U) 1655 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ 1656 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ 1657 #define CAN_FS1R_FSC7_Pos (7U) 1658 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ 1659 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ 1660 #define CAN_FS1R_FSC8_Pos (8U) 1661 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ 1662 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ 1663 #define CAN_FS1R_FSC9_Pos (9U) 1664 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ 1665 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ 1666 #define CAN_FS1R_FSC10_Pos (10U) 1667 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ 1668 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ 1669 #define CAN_FS1R_FSC11_Pos (11U) 1670 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ 1671 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ 1672 #define CAN_FS1R_FSC12_Pos (12U) 1673 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ 1674 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ 1675 #define CAN_FS1R_FSC13_Pos (13U) 1676 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ 1677 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ 1678 1679 /****************** Bit definition for CAN_FFA1R register *******************/ 1680 #define CAN_FFA1R_FFA_Pos (0U) 1681 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */ 1682 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ 1683 #define CAN_FFA1R_FFA0_Pos (0U) 1684 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ 1685 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */ 1686 #define CAN_FFA1R_FFA1_Pos (1U) 1687 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ 1688 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */ 1689 #define CAN_FFA1R_FFA2_Pos (2U) 1690 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ 1691 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */ 1692 #define CAN_FFA1R_FFA3_Pos (3U) 1693 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ 1694 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */ 1695 #define CAN_FFA1R_FFA4_Pos (4U) 1696 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ 1697 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */ 1698 #define CAN_FFA1R_FFA5_Pos (5U) 1699 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ 1700 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */ 1701 #define CAN_FFA1R_FFA6_Pos (6U) 1702 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ 1703 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */ 1704 #define CAN_FFA1R_FFA7_Pos (7U) 1705 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ 1706 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */ 1707 #define CAN_FFA1R_FFA8_Pos (8U) 1708 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ 1709 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */ 1710 #define CAN_FFA1R_FFA9_Pos (9U) 1711 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ 1712 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */ 1713 #define CAN_FFA1R_FFA10_Pos (10U) 1714 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ 1715 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */ 1716 #define CAN_FFA1R_FFA11_Pos (11U) 1717 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ 1718 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */ 1719 #define CAN_FFA1R_FFA12_Pos (12U) 1720 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ 1721 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */ 1722 #define CAN_FFA1R_FFA13_Pos (13U) 1723 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ 1724 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */ 1725 1726 /******************* Bit definition for CAN_FA1R register *******************/ 1727 #define CAN_FA1R_FACT_Pos (0U) 1728 #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */ 1729 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ 1730 #define CAN_FA1R_FACT0_Pos (0U) 1731 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ 1732 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */ 1733 #define CAN_FA1R_FACT1_Pos (1U) 1734 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ 1735 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */ 1736 #define CAN_FA1R_FACT2_Pos (2U) 1737 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ 1738 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */ 1739 #define CAN_FA1R_FACT3_Pos (3U) 1740 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ 1741 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */ 1742 #define CAN_FA1R_FACT4_Pos (4U) 1743 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ 1744 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */ 1745 #define CAN_FA1R_FACT5_Pos (5U) 1746 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ 1747 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */ 1748 #define CAN_FA1R_FACT6_Pos (6U) 1749 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ 1750 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */ 1751 #define CAN_FA1R_FACT7_Pos (7U) 1752 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ 1753 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */ 1754 #define CAN_FA1R_FACT8_Pos (8U) 1755 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ 1756 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */ 1757 #define CAN_FA1R_FACT9_Pos (9U) 1758 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ 1759 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */ 1760 #define CAN_FA1R_FACT10_Pos (10U) 1761 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ 1762 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */ 1763 #define CAN_FA1R_FACT11_Pos (11U) 1764 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ 1765 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */ 1766 #define CAN_FA1R_FACT12_Pos (12U) 1767 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ 1768 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */ 1769 #define CAN_FA1R_FACT13_Pos (13U) 1770 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ 1771 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */ 1772 1773 /******************* Bit definition for CAN_F0R1 register *******************/ 1774 #define CAN_F0R1_FB0_Pos (0U) 1775 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ 1776 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ 1777 #define CAN_F0R1_FB1_Pos (1U) 1778 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ 1779 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ 1780 #define CAN_F0R1_FB2_Pos (2U) 1781 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ 1782 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ 1783 #define CAN_F0R1_FB3_Pos (3U) 1784 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ 1785 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ 1786 #define CAN_F0R1_FB4_Pos (4U) 1787 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ 1788 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ 1789 #define CAN_F0R1_FB5_Pos (5U) 1790 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ 1791 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ 1792 #define CAN_F0R1_FB6_Pos (6U) 1793 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ 1794 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ 1795 #define CAN_F0R1_FB7_Pos (7U) 1796 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ 1797 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ 1798 #define CAN_F0R1_FB8_Pos (8U) 1799 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ 1800 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ 1801 #define CAN_F0R1_FB9_Pos (9U) 1802 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ 1803 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ 1804 #define CAN_F0R1_FB10_Pos (10U) 1805 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ 1806 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ 1807 #define CAN_F0R1_FB11_Pos (11U) 1808 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ 1809 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ 1810 #define CAN_F0R1_FB12_Pos (12U) 1811 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ 1812 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ 1813 #define CAN_F0R1_FB13_Pos (13U) 1814 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ 1815 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ 1816 #define CAN_F0R1_FB14_Pos (14U) 1817 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ 1818 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ 1819 #define CAN_F0R1_FB15_Pos (15U) 1820 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ 1821 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ 1822 #define CAN_F0R1_FB16_Pos (16U) 1823 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ 1824 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ 1825 #define CAN_F0R1_FB17_Pos (17U) 1826 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ 1827 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ 1828 #define CAN_F0R1_FB18_Pos (18U) 1829 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ 1830 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ 1831 #define CAN_F0R1_FB19_Pos (19U) 1832 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ 1833 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ 1834 #define CAN_F0R1_FB20_Pos (20U) 1835 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ 1836 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ 1837 #define CAN_F0R1_FB21_Pos (21U) 1838 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ 1839 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ 1840 #define CAN_F0R1_FB22_Pos (22U) 1841 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ 1842 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ 1843 #define CAN_F0R1_FB23_Pos (23U) 1844 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ 1845 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ 1846 #define CAN_F0R1_FB24_Pos (24U) 1847 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ 1848 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ 1849 #define CAN_F0R1_FB25_Pos (25U) 1850 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ 1851 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ 1852 #define CAN_F0R1_FB26_Pos (26U) 1853 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ 1854 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ 1855 #define CAN_F0R1_FB27_Pos (27U) 1856 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ 1857 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ 1858 #define CAN_F0R1_FB28_Pos (28U) 1859 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ 1860 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ 1861 #define CAN_F0R1_FB29_Pos (29U) 1862 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ 1863 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ 1864 #define CAN_F0R1_FB30_Pos (30U) 1865 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ 1866 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ 1867 #define CAN_F0R1_FB31_Pos (31U) 1868 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ 1869 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ 1870 1871 /******************* Bit definition for CAN_F1R1 register *******************/ 1872 #define CAN_F1R1_FB0_Pos (0U) 1873 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ 1874 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ 1875 #define CAN_F1R1_FB1_Pos (1U) 1876 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ 1877 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ 1878 #define CAN_F1R1_FB2_Pos (2U) 1879 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ 1880 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ 1881 #define CAN_F1R1_FB3_Pos (3U) 1882 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ 1883 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ 1884 #define CAN_F1R1_FB4_Pos (4U) 1885 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ 1886 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ 1887 #define CAN_F1R1_FB5_Pos (5U) 1888 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ 1889 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ 1890 #define CAN_F1R1_FB6_Pos (6U) 1891 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ 1892 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ 1893 #define CAN_F1R1_FB7_Pos (7U) 1894 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ 1895 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ 1896 #define CAN_F1R1_FB8_Pos (8U) 1897 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ 1898 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ 1899 #define CAN_F1R1_FB9_Pos (9U) 1900 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ 1901 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ 1902 #define CAN_F1R1_FB10_Pos (10U) 1903 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ 1904 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ 1905 #define CAN_F1R1_FB11_Pos (11U) 1906 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ 1907 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ 1908 #define CAN_F1R1_FB12_Pos (12U) 1909 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ 1910 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ 1911 #define CAN_F1R1_FB13_Pos (13U) 1912 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ 1913 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ 1914 #define CAN_F1R1_FB14_Pos (14U) 1915 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ 1916 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ 1917 #define CAN_F1R1_FB15_Pos (15U) 1918 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ 1919 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ 1920 #define CAN_F1R1_FB16_Pos (16U) 1921 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ 1922 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ 1923 #define CAN_F1R1_FB17_Pos (17U) 1924 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ 1925 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ 1926 #define CAN_F1R1_FB18_Pos (18U) 1927 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ 1928 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ 1929 #define CAN_F1R1_FB19_Pos (19U) 1930 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ 1931 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ 1932 #define CAN_F1R1_FB20_Pos (20U) 1933 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ 1934 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ 1935 #define CAN_F1R1_FB21_Pos (21U) 1936 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ 1937 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ 1938 #define CAN_F1R1_FB22_Pos (22U) 1939 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ 1940 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ 1941 #define CAN_F1R1_FB23_Pos (23U) 1942 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ 1943 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ 1944 #define CAN_F1R1_FB24_Pos (24U) 1945 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ 1946 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ 1947 #define CAN_F1R1_FB25_Pos (25U) 1948 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ 1949 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ 1950 #define CAN_F1R1_FB26_Pos (26U) 1951 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ 1952 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ 1953 #define CAN_F1R1_FB27_Pos (27U) 1954 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ 1955 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ 1956 #define CAN_F1R1_FB28_Pos (28U) 1957 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ 1958 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ 1959 #define CAN_F1R1_FB29_Pos (29U) 1960 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ 1961 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ 1962 #define CAN_F1R1_FB30_Pos (30U) 1963 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ 1964 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ 1965 #define CAN_F1R1_FB31_Pos (31U) 1966 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ 1967 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ 1968 1969 /******************* Bit definition for CAN_F2R1 register *******************/ 1970 #define CAN_F2R1_FB0_Pos (0U) 1971 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ 1972 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ 1973 #define CAN_F2R1_FB1_Pos (1U) 1974 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ 1975 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ 1976 #define CAN_F2R1_FB2_Pos (2U) 1977 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ 1978 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ 1979 #define CAN_F2R1_FB3_Pos (3U) 1980 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ 1981 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ 1982 #define CAN_F2R1_FB4_Pos (4U) 1983 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ 1984 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ 1985 #define CAN_F2R1_FB5_Pos (5U) 1986 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ 1987 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ 1988 #define CAN_F2R1_FB6_Pos (6U) 1989 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ 1990 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ 1991 #define CAN_F2R1_FB7_Pos (7U) 1992 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ 1993 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ 1994 #define CAN_F2R1_FB8_Pos (8U) 1995 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ 1996 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ 1997 #define CAN_F2R1_FB9_Pos (9U) 1998 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ 1999 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ 2000 #define CAN_F2R1_FB10_Pos (10U) 2001 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ 2002 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ 2003 #define CAN_F2R1_FB11_Pos (11U) 2004 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ 2005 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ 2006 #define CAN_F2R1_FB12_Pos (12U) 2007 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ 2008 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ 2009 #define CAN_F2R1_FB13_Pos (13U) 2010 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ 2011 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ 2012 #define CAN_F2R1_FB14_Pos (14U) 2013 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ 2014 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ 2015 #define CAN_F2R1_FB15_Pos (15U) 2016 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ 2017 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ 2018 #define CAN_F2R1_FB16_Pos (16U) 2019 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ 2020 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ 2021 #define CAN_F2R1_FB17_Pos (17U) 2022 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ 2023 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ 2024 #define CAN_F2R1_FB18_Pos (18U) 2025 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ 2026 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ 2027 #define CAN_F2R1_FB19_Pos (19U) 2028 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ 2029 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ 2030 #define CAN_F2R1_FB20_Pos (20U) 2031 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ 2032 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ 2033 #define CAN_F2R1_FB21_Pos (21U) 2034 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ 2035 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ 2036 #define CAN_F2R1_FB22_Pos (22U) 2037 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ 2038 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ 2039 #define CAN_F2R1_FB23_Pos (23U) 2040 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ 2041 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ 2042 #define CAN_F2R1_FB24_Pos (24U) 2043 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ 2044 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ 2045 #define CAN_F2R1_FB25_Pos (25U) 2046 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ 2047 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ 2048 #define CAN_F2R1_FB26_Pos (26U) 2049 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ 2050 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ 2051 #define CAN_F2R1_FB27_Pos (27U) 2052 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ 2053 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ 2054 #define CAN_F2R1_FB28_Pos (28U) 2055 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ 2056 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ 2057 #define CAN_F2R1_FB29_Pos (29U) 2058 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ 2059 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ 2060 #define CAN_F2R1_FB30_Pos (30U) 2061 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ 2062 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ 2063 #define CAN_F2R1_FB31_Pos (31U) 2064 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ 2065 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ 2066 2067 /******************* Bit definition for CAN_F3R1 register *******************/ 2068 #define CAN_F3R1_FB0_Pos (0U) 2069 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ 2070 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ 2071 #define CAN_F3R1_FB1_Pos (1U) 2072 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ 2073 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ 2074 #define CAN_F3R1_FB2_Pos (2U) 2075 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ 2076 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ 2077 #define CAN_F3R1_FB3_Pos (3U) 2078 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ 2079 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ 2080 #define CAN_F3R1_FB4_Pos (4U) 2081 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ 2082 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ 2083 #define CAN_F3R1_FB5_Pos (5U) 2084 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ 2085 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ 2086 #define CAN_F3R1_FB6_Pos (6U) 2087 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ 2088 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ 2089 #define CAN_F3R1_FB7_Pos (7U) 2090 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ 2091 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ 2092 #define CAN_F3R1_FB8_Pos (8U) 2093 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ 2094 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ 2095 #define CAN_F3R1_FB9_Pos (9U) 2096 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ 2097 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ 2098 #define CAN_F3R1_FB10_Pos (10U) 2099 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ 2100 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ 2101 #define CAN_F3R1_FB11_Pos (11U) 2102 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ 2103 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ 2104 #define CAN_F3R1_FB12_Pos (12U) 2105 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ 2106 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ 2107 #define CAN_F3R1_FB13_Pos (13U) 2108 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ 2109 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ 2110 #define CAN_F3R1_FB14_Pos (14U) 2111 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ 2112 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ 2113 #define CAN_F3R1_FB15_Pos (15U) 2114 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ 2115 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ 2116 #define CAN_F3R1_FB16_Pos (16U) 2117 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ 2118 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ 2119 #define CAN_F3R1_FB17_Pos (17U) 2120 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ 2121 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ 2122 #define CAN_F3R1_FB18_Pos (18U) 2123 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ 2124 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ 2125 #define CAN_F3R1_FB19_Pos (19U) 2126 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ 2127 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ 2128 #define CAN_F3R1_FB20_Pos (20U) 2129 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ 2130 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ 2131 #define CAN_F3R1_FB21_Pos (21U) 2132 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ 2133 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ 2134 #define CAN_F3R1_FB22_Pos (22U) 2135 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ 2136 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ 2137 #define CAN_F3R1_FB23_Pos (23U) 2138 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ 2139 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ 2140 #define CAN_F3R1_FB24_Pos (24U) 2141 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ 2142 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ 2143 #define CAN_F3R1_FB25_Pos (25U) 2144 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ 2145 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ 2146 #define CAN_F3R1_FB26_Pos (26U) 2147 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ 2148 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ 2149 #define CAN_F3R1_FB27_Pos (27U) 2150 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ 2151 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ 2152 #define CAN_F3R1_FB28_Pos (28U) 2153 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ 2154 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ 2155 #define CAN_F3R1_FB29_Pos (29U) 2156 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ 2157 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ 2158 #define CAN_F3R1_FB30_Pos (30U) 2159 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ 2160 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ 2161 #define CAN_F3R1_FB31_Pos (31U) 2162 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ 2163 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ 2164 2165 /******************* Bit definition for CAN_F4R1 register *******************/ 2166 #define CAN_F4R1_FB0_Pos (0U) 2167 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ 2168 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ 2169 #define CAN_F4R1_FB1_Pos (1U) 2170 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ 2171 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ 2172 #define CAN_F4R1_FB2_Pos (2U) 2173 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ 2174 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ 2175 #define CAN_F4R1_FB3_Pos (3U) 2176 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ 2177 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ 2178 #define CAN_F4R1_FB4_Pos (4U) 2179 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ 2180 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ 2181 #define CAN_F4R1_FB5_Pos (5U) 2182 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ 2183 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ 2184 #define CAN_F4R1_FB6_Pos (6U) 2185 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ 2186 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ 2187 #define CAN_F4R1_FB7_Pos (7U) 2188 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ 2189 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ 2190 #define CAN_F4R1_FB8_Pos (8U) 2191 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ 2192 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ 2193 #define CAN_F4R1_FB9_Pos (9U) 2194 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ 2195 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ 2196 #define CAN_F4R1_FB10_Pos (10U) 2197 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ 2198 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ 2199 #define CAN_F4R1_FB11_Pos (11U) 2200 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ 2201 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ 2202 #define CAN_F4R1_FB12_Pos (12U) 2203 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ 2204 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ 2205 #define CAN_F4R1_FB13_Pos (13U) 2206 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ 2207 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ 2208 #define CAN_F4R1_FB14_Pos (14U) 2209 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ 2210 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ 2211 #define CAN_F4R1_FB15_Pos (15U) 2212 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ 2213 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ 2214 #define CAN_F4R1_FB16_Pos (16U) 2215 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ 2216 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ 2217 #define CAN_F4R1_FB17_Pos (17U) 2218 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ 2219 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ 2220 #define CAN_F4R1_FB18_Pos (18U) 2221 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ 2222 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ 2223 #define CAN_F4R1_FB19_Pos (19U) 2224 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ 2225 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ 2226 #define CAN_F4R1_FB20_Pos (20U) 2227 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ 2228 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ 2229 #define CAN_F4R1_FB21_Pos (21U) 2230 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ 2231 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ 2232 #define CAN_F4R1_FB22_Pos (22U) 2233 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ 2234 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ 2235 #define CAN_F4R1_FB23_Pos (23U) 2236 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ 2237 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ 2238 #define CAN_F4R1_FB24_Pos (24U) 2239 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ 2240 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ 2241 #define CAN_F4R1_FB25_Pos (25U) 2242 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ 2243 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ 2244 #define CAN_F4R1_FB26_Pos (26U) 2245 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ 2246 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ 2247 #define CAN_F4R1_FB27_Pos (27U) 2248 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ 2249 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ 2250 #define CAN_F4R1_FB28_Pos (28U) 2251 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ 2252 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ 2253 #define CAN_F4R1_FB29_Pos (29U) 2254 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ 2255 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ 2256 #define CAN_F4R1_FB30_Pos (30U) 2257 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ 2258 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ 2259 #define CAN_F4R1_FB31_Pos (31U) 2260 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ 2261 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ 2262 2263 /******************* Bit definition for CAN_F5R1 register *******************/ 2264 #define CAN_F5R1_FB0_Pos (0U) 2265 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ 2266 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ 2267 #define CAN_F5R1_FB1_Pos (1U) 2268 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ 2269 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ 2270 #define CAN_F5R1_FB2_Pos (2U) 2271 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ 2272 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ 2273 #define CAN_F5R1_FB3_Pos (3U) 2274 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ 2275 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ 2276 #define CAN_F5R1_FB4_Pos (4U) 2277 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ 2278 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ 2279 #define CAN_F5R1_FB5_Pos (5U) 2280 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ 2281 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ 2282 #define CAN_F5R1_FB6_Pos (6U) 2283 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ 2284 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ 2285 #define CAN_F5R1_FB7_Pos (7U) 2286 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ 2287 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ 2288 #define CAN_F5R1_FB8_Pos (8U) 2289 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ 2290 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ 2291 #define CAN_F5R1_FB9_Pos (9U) 2292 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ 2293 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ 2294 #define CAN_F5R1_FB10_Pos (10U) 2295 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ 2296 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ 2297 #define CAN_F5R1_FB11_Pos (11U) 2298 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ 2299 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ 2300 #define CAN_F5R1_FB12_Pos (12U) 2301 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ 2302 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ 2303 #define CAN_F5R1_FB13_Pos (13U) 2304 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ 2305 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ 2306 #define CAN_F5R1_FB14_Pos (14U) 2307 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ 2308 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ 2309 #define CAN_F5R1_FB15_Pos (15U) 2310 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ 2311 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ 2312 #define CAN_F5R1_FB16_Pos (16U) 2313 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ 2314 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ 2315 #define CAN_F5R1_FB17_Pos (17U) 2316 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ 2317 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ 2318 #define CAN_F5R1_FB18_Pos (18U) 2319 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ 2320 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ 2321 #define CAN_F5R1_FB19_Pos (19U) 2322 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ 2323 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ 2324 #define CAN_F5R1_FB20_Pos (20U) 2325 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ 2326 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ 2327 #define CAN_F5R1_FB21_Pos (21U) 2328 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ 2329 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ 2330 #define CAN_F5R1_FB22_Pos (22U) 2331 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ 2332 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ 2333 #define CAN_F5R1_FB23_Pos (23U) 2334 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ 2335 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ 2336 #define CAN_F5R1_FB24_Pos (24U) 2337 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ 2338 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ 2339 #define CAN_F5R1_FB25_Pos (25U) 2340 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ 2341 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ 2342 #define CAN_F5R1_FB26_Pos (26U) 2343 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ 2344 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ 2345 #define CAN_F5R1_FB27_Pos (27U) 2346 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ 2347 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ 2348 #define CAN_F5R1_FB28_Pos (28U) 2349 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ 2350 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ 2351 #define CAN_F5R1_FB29_Pos (29U) 2352 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ 2353 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ 2354 #define CAN_F5R1_FB30_Pos (30U) 2355 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ 2356 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ 2357 #define CAN_F5R1_FB31_Pos (31U) 2358 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ 2359 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ 2360 2361 /******************* Bit definition for CAN_F6R1 register *******************/ 2362 #define CAN_F6R1_FB0_Pos (0U) 2363 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ 2364 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ 2365 #define CAN_F6R1_FB1_Pos (1U) 2366 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ 2367 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ 2368 #define CAN_F6R1_FB2_Pos (2U) 2369 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ 2370 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ 2371 #define CAN_F6R1_FB3_Pos (3U) 2372 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ 2373 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ 2374 #define CAN_F6R1_FB4_Pos (4U) 2375 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ 2376 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ 2377 #define CAN_F6R1_FB5_Pos (5U) 2378 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ 2379 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ 2380 #define CAN_F6R1_FB6_Pos (6U) 2381 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ 2382 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ 2383 #define CAN_F6R1_FB7_Pos (7U) 2384 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ 2385 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ 2386 #define CAN_F6R1_FB8_Pos (8U) 2387 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ 2388 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ 2389 #define CAN_F6R1_FB9_Pos (9U) 2390 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ 2391 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ 2392 #define CAN_F6R1_FB10_Pos (10U) 2393 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ 2394 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ 2395 #define CAN_F6R1_FB11_Pos (11U) 2396 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ 2397 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ 2398 #define CAN_F6R1_FB12_Pos (12U) 2399 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ 2400 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ 2401 #define CAN_F6R1_FB13_Pos (13U) 2402 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ 2403 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ 2404 #define CAN_F6R1_FB14_Pos (14U) 2405 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ 2406 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ 2407 #define CAN_F6R1_FB15_Pos (15U) 2408 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ 2409 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ 2410 #define CAN_F6R1_FB16_Pos (16U) 2411 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ 2412 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ 2413 #define CAN_F6R1_FB17_Pos (17U) 2414 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ 2415 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ 2416 #define CAN_F6R1_FB18_Pos (18U) 2417 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ 2418 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ 2419 #define CAN_F6R1_FB19_Pos (19U) 2420 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ 2421 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ 2422 #define CAN_F6R1_FB20_Pos (20U) 2423 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ 2424 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ 2425 #define CAN_F6R1_FB21_Pos (21U) 2426 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ 2427 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ 2428 #define CAN_F6R1_FB22_Pos (22U) 2429 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ 2430 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ 2431 #define CAN_F6R1_FB23_Pos (23U) 2432 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ 2433 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ 2434 #define CAN_F6R1_FB24_Pos (24U) 2435 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ 2436 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ 2437 #define CAN_F6R1_FB25_Pos (25U) 2438 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ 2439 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ 2440 #define CAN_F6R1_FB26_Pos (26U) 2441 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ 2442 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ 2443 #define CAN_F6R1_FB27_Pos (27U) 2444 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ 2445 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ 2446 #define CAN_F6R1_FB28_Pos (28U) 2447 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ 2448 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ 2449 #define CAN_F6R1_FB29_Pos (29U) 2450 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ 2451 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ 2452 #define CAN_F6R1_FB30_Pos (30U) 2453 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ 2454 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ 2455 #define CAN_F6R1_FB31_Pos (31U) 2456 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ 2457 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ 2458 2459 /******************* Bit definition for CAN_F7R1 register *******************/ 2460 #define CAN_F7R1_FB0_Pos (0U) 2461 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ 2462 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ 2463 #define CAN_F7R1_FB1_Pos (1U) 2464 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ 2465 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ 2466 #define CAN_F7R1_FB2_Pos (2U) 2467 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ 2468 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ 2469 #define CAN_F7R1_FB3_Pos (3U) 2470 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ 2471 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ 2472 #define CAN_F7R1_FB4_Pos (4U) 2473 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ 2474 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ 2475 #define CAN_F7R1_FB5_Pos (5U) 2476 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ 2477 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ 2478 #define CAN_F7R1_FB6_Pos (6U) 2479 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ 2480 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ 2481 #define CAN_F7R1_FB7_Pos (7U) 2482 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ 2483 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ 2484 #define CAN_F7R1_FB8_Pos (8U) 2485 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ 2486 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ 2487 #define CAN_F7R1_FB9_Pos (9U) 2488 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ 2489 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ 2490 #define CAN_F7R1_FB10_Pos (10U) 2491 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ 2492 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ 2493 #define CAN_F7R1_FB11_Pos (11U) 2494 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ 2495 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ 2496 #define CAN_F7R1_FB12_Pos (12U) 2497 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ 2498 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ 2499 #define CAN_F7R1_FB13_Pos (13U) 2500 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ 2501 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ 2502 #define CAN_F7R1_FB14_Pos (14U) 2503 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ 2504 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ 2505 #define CAN_F7R1_FB15_Pos (15U) 2506 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ 2507 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ 2508 #define CAN_F7R1_FB16_Pos (16U) 2509 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ 2510 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ 2511 #define CAN_F7R1_FB17_Pos (17U) 2512 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ 2513 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ 2514 #define CAN_F7R1_FB18_Pos (18U) 2515 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ 2516 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ 2517 #define CAN_F7R1_FB19_Pos (19U) 2518 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ 2519 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ 2520 #define CAN_F7R1_FB20_Pos (20U) 2521 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ 2522 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ 2523 #define CAN_F7R1_FB21_Pos (21U) 2524 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ 2525 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ 2526 #define CAN_F7R1_FB22_Pos (22U) 2527 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ 2528 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ 2529 #define CAN_F7R1_FB23_Pos (23U) 2530 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ 2531 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ 2532 #define CAN_F7R1_FB24_Pos (24U) 2533 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ 2534 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ 2535 #define CAN_F7R1_FB25_Pos (25U) 2536 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ 2537 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ 2538 #define CAN_F7R1_FB26_Pos (26U) 2539 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ 2540 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ 2541 #define CAN_F7R1_FB27_Pos (27U) 2542 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ 2543 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ 2544 #define CAN_F7R1_FB28_Pos (28U) 2545 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ 2546 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ 2547 #define CAN_F7R1_FB29_Pos (29U) 2548 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ 2549 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ 2550 #define CAN_F7R1_FB30_Pos (30U) 2551 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ 2552 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ 2553 #define CAN_F7R1_FB31_Pos (31U) 2554 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ 2555 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ 2556 2557 /******************* Bit definition for CAN_F8R1 register *******************/ 2558 #define CAN_F8R1_FB0_Pos (0U) 2559 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ 2560 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ 2561 #define CAN_F8R1_FB1_Pos (1U) 2562 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ 2563 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ 2564 #define CAN_F8R1_FB2_Pos (2U) 2565 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ 2566 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ 2567 #define CAN_F8R1_FB3_Pos (3U) 2568 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ 2569 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ 2570 #define CAN_F8R1_FB4_Pos (4U) 2571 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ 2572 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ 2573 #define CAN_F8R1_FB5_Pos (5U) 2574 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ 2575 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ 2576 #define CAN_F8R1_FB6_Pos (6U) 2577 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ 2578 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ 2579 #define CAN_F8R1_FB7_Pos (7U) 2580 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ 2581 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ 2582 #define CAN_F8R1_FB8_Pos (8U) 2583 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ 2584 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ 2585 #define CAN_F8R1_FB9_Pos (9U) 2586 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ 2587 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ 2588 #define CAN_F8R1_FB10_Pos (10U) 2589 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ 2590 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ 2591 #define CAN_F8R1_FB11_Pos (11U) 2592 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ 2593 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ 2594 #define CAN_F8R1_FB12_Pos (12U) 2595 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ 2596 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ 2597 #define CAN_F8R1_FB13_Pos (13U) 2598 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ 2599 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ 2600 #define CAN_F8R1_FB14_Pos (14U) 2601 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ 2602 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ 2603 #define CAN_F8R1_FB15_Pos (15U) 2604 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ 2605 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ 2606 #define CAN_F8R1_FB16_Pos (16U) 2607 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ 2608 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ 2609 #define CAN_F8R1_FB17_Pos (17U) 2610 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ 2611 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ 2612 #define CAN_F8R1_FB18_Pos (18U) 2613 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ 2614 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ 2615 #define CAN_F8R1_FB19_Pos (19U) 2616 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ 2617 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ 2618 #define CAN_F8R1_FB20_Pos (20U) 2619 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ 2620 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ 2621 #define CAN_F8R1_FB21_Pos (21U) 2622 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ 2623 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ 2624 #define CAN_F8R1_FB22_Pos (22U) 2625 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ 2626 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ 2627 #define CAN_F8R1_FB23_Pos (23U) 2628 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ 2629 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ 2630 #define CAN_F8R1_FB24_Pos (24U) 2631 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ 2632 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ 2633 #define CAN_F8R1_FB25_Pos (25U) 2634 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ 2635 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ 2636 #define CAN_F8R1_FB26_Pos (26U) 2637 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ 2638 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ 2639 #define CAN_F8R1_FB27_Pos (27U) 2640 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ 2641 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ 2642 #define CAN_F8R1_FB28_Pos (28U) 2643 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ 2644 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ 2645 #define CAN_F8R1_FB29_Pos (29U) 2646 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ 2647 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ 2648 #define CAN_F8R1_FB30_Pos (30U) 2649 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ 2650 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ 2651 #define CAN_F8R1_FB31_Pos (31U) 2652 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ 2653 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ 2654 2655 /******************* Bit definition for CAN_F9R1 register *******************/ 2656 #define CAN_F9R1_FB0_Pos (0U) 2657 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ 2658 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ 2659 #define CAN_F9R1_FB1_Pos (1U) 2660 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ 2661 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ 2662 #define CAN_F9R1_FB2_Pos (2U) 2663 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ 2664 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ 2665 #define CAN_F9R1_FB3_Pos (3U) 2666 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ 2667 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ 2668 #define CAN_F9R1_FB4_Pos (4U) 2669 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ 2670 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ 2671 #define CAN_F9R1_FB5_Pos (5U) 2672 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ 2673 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ 2674 #define CAN_F9R1_FB6_Pos (6U) 2675 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ 2676 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ 2677 #define CAN_F9R1_FB7_Pos (7U) 2678 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ 2679 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ 2680 #define CAN_F9R1_FB8_Pos (8U) 2681 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ 2682 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ 2683 #define CAN_F9R1_FB9_Pos (9U) 2684 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ 2685 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ 2686 #define CAN_F9R1_FB10_Pos (10U) 2687 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ 2688 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ 2689 #define CAN_F9R1_FB11_Pos (11U) 2690 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ 2691 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ 2692 #define CAN_F9R1_FB12_Pos (12U) 2693 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ 2694 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ 2695 #define CAN_F9R1_FB13_Pos (13U) 2696 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ 2697 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ 2698 #define CAN_F9R1_FB14_Pos (14U) 2699 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ 2700 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ 2701 #define CAN_F9R1_FB15_Pos (15U) 2702 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ 2703 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ 2704 #define CAN_F9R1_FB16_Pos (16U) 2705 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ 2706 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ 2707 #define CAN_F9R1_FB17_Pos (17U) 2708 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ 2709 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ 2710 #define CAN_F9R1_FB18_Pos (18U) 2711 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ 2712 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ 2713 #define CAN_F9R1_FB19_Pos (19U) 2714 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ 2715 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ 2716 #define CAN_F9R1_FB20_Pos (20U) 2717 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ 2718 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ 2719 #define CAN_F9R1_FB21_Pos (21U) 2720 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ 2721 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ 2722 #define CAN_F9R1_FB22_Pos (22U) 2723 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ 2724 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ 2725 #define CAN_F9R1_FB23_Pos (23U) 2726 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ 2727 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ 2728 #define CAN_F9R1_FB24_Pos (24U) 2729 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ 2730 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ 2731 #define CAN_F9R1_FB25_Pos (25U) 2732 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ 2733 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ 2734 #define CAN_F9R1_FB26_Pos (26U) 2735 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ 2736 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ 2737 #define CAN_F9R1_FB27_Pos (27U) 2738 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ 2739 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ 2740 #define CAN_F9R1_FB28_Pos (28U) 2741 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ 2742 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ 2743 #define CAN_F9R1_FB29_Pos (29U) 2744 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ 2745 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ 2746 #define CAN_F9R1_FB30_Pos (30U) 2747 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ 2748 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ 2749 #define CAN_F9R1_FB31_Pos (31U) 2750 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ 2751 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ 2752 2753 /******************* Bit definition for CAN_F10R1 register ******************/ 2754 #define CAN_F10R1_FB0_Pos (0U) 2755 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ 2756 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ 2757 #define CAN_F10R1_FB1_Pos (1U) 2758 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ 2759 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ 2760 #define CAN_F10R1_FB2_Pos (2U) 2761 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ 2762 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ 2763 #define CAN_F10R1_FB3_Pos (3U) 2764 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ 2765 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ 2766 #define CAN_F10R1_FB4_Pos (4U) 2767 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ 2768 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ 2769 #define CAN_F10R1_FB5_Pos (5U) 2770 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ 2771 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ 2772 #define CAN_F10R1_FB6_Pos (6U) 2773 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ 2774 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ 2775 #define CAN_F10R1_FB7_Pos (7U) 2776 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ 2777 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ 2778 #define CAN_F10R1_FB8_Pos (8U) 2779 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ 2780 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ 2781 #define CAN_F10R1_FB9_Pos (9U) 2782 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ 2783 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ 2784 #define CAN_F10R1_FB10_Pos (10U) 2785 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ 2786 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ 2787 #define CAN_F10R1_FB11_Pos (11U) 2788 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ 2789 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ 2790 #define CAN_F10R1_FB12_Pos (12U) 2791 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ 2792 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ 2793 #define CAN_F10R1_FB13_Pos (13U) 2794 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ 2795 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ 2796 #define CAN_F10R1_FB14_Pos (14U) 2797 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ 2798 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ 2799 #define CAN_F10R1_FB15_Pos (15U) 2800 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ 2801 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ 2802 #define CAN_F10R1_FB16_Pos (16U) 2803 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ 2804 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ 2805 #define CAN_F10R1_FB17_Pos (17U) 2806 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ 2807 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ 2808 #define CAN_F10R1_FB18_Pos (18U) 2809 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ 2810 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ 2811 #define CAN_F10R1_FB19_Pos (19U) 2812 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ 2813 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ 2814 #define CAN_F10R1_FB20_Pos (20U) 2815 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ 2816 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ 2817 #define CAN_F10R1_FB21_Pos (21U) 2818 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ 2819 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ 2820 #define CAN_F10R1_FB22_Pos (22U) 2821 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ 2822 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ 2823 #define CAN_F10R1_FB23_Pos (23U) 2824 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ 2825 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ 2826 #define CAN_F10R1_FB24_Pos (24U) 2827 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ 2828 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ 2829 #define CAN_F10R1_FB25_Pos (25U) 2830 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ 2831 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ 2832 #define CAN_F10R1_FB26_Pos (26U) 2833 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ 2834 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ 2835 #define CAN_F10R1_FB27_Pos (27U) 2836 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ 2837 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ 2838 #define CAN_F10R1_FB28_Pos (28U) 2839 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ 2840 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ 2841 #define CAN_F10R1_FB29_Pos (29U) 2842 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ 2843 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ 2844 #define CAN_F10R1_FB30_Pos (30U) 2845 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ 2846 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ 2847 #define CAN_F10R1_FB31_Pos (31U) 2848 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ 2849 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ 2850 2851 /******************* Bit definition for CAN_F11R1 register ******************/ 2852 #define CAN_F11R1_FB0_Pos (0U) 2853 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ 2854 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ 2855 #define CAN_F11R1_FB1_Pos (1U) 2856 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ 2857 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ 2858 #define CAN_F11R1_FB2_Pos (2U) 2859 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ 2860 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ 2861 #define CAN_F11R1_FB3_Pos (3U) 2862 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ 2863 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ 2864 #define CAN_F11R1_FB4_Pos (4U) 2865 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ 2866 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ 2867 #define CAN_F11R1_FB5_Pos (5U) 2868 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ 2869 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ 2870 #define CAN_F11R1_FB6_Pos (6U) 2871 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ 2872 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ 2873 #define CAN_F11R1_FB7_Pos (7U) 2874 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ 2875 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ 2876 #define CAN_F11R1_FB8_Pos (8U) 2877 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ 2878 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ 2879 #define CAN_F11R1_FB9_Pos (9U) 2880 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ 2881 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ 2882 #define CAN_F11R1_FB10_Pos (10U) 2883 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ 2884 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ 2885 #define CAN_F11R1_FB11_Pos (11U) 2886 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ 2887 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ 2888 #define CAN_F11R1_FB12_Pos (12U) 2889 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ 2890 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ 2891 #define CAN_F11R1_FB13_Pos (13U) 2892 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ 2893 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ 2894 #define CAN_F11R1_FB14_Pos (14U) 2895 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ 2896 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ 2897 #define CAN_F11R1_FB15_Pos (15U) 2898 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ 2899 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ 2900 #define CAN_F11R1_FB16_Pos (16U) 2901 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ 2902 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ 2903 #define CAN_F11R1_FB17_Pos (17U) 2904 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ 2905 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ 2906 #define CAN_F11R1_FB18_Pos (18U) 2907 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ 2908 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ 2909 #define CAN_F11R1_FB19_Pos (19U) 2910 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ 2911 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ 2912 #define CAN_F11R1_FB20_Pos (20U) 2913 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ 2914 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ 2915 #define CAN_F11R1_FB21_Pos (21U) 2916 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ 2917 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ 2918 #define CAN_F11R1_FB22_Pos (22U) 2919 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ 2920 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ 2921 #define CAN_F11R1_FB23_Pos (23U) 2922 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ 2923 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ 2924 #define CAN_F11R1_FB24_Pos (24U) 2925 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ 2926 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ 2927 #define CAN_F11R1_FB25_Pos (25U) 2928 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ 2929 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ 2930 #define CAN_F11R1_FB26_Pos (26U) 2931 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ 2932 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ 2933 #define CAN_F11R1_FB27_Pos (27U) 2934 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ 2935 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ 2936 #define CAN_F11R1_FB28_Pos (28U) 2937 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ 2938 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ 2939 #define CAN_F11R1_FB29_Pos (29U) 2940 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ 2941 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ 2942 #define CAN_F11R1_FB30_Pos (30U) 2943 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ 2944 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ 2945 #define CAN_F11R1_FB31_Pos (31U) 2946 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ 2947 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ 2948 2949 /******************* Bit definition for CAN_F12R1 register ******************/ 2950 #define CAN_F12R1_FB0_Pos (0U) 2951 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ 2952 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ 2953 #define CAN_F12R1_FB1_Pos (1U) 2954 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ 2955 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ 2956 #define CAN_F12R1_FB2_Pos (2U) 2957 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ 2958 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ 2959 #define CAN_F12R1_FB3_Pos (3U) 2960 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ 2961 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ 2962 #define CAN_F12R1_FB4_Pos (4U) 2963 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ 2964 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ 2965 #define CAN_F12R1_FB5_Pos (5U) 2966 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ 2967 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ 2968 #define CAN_F12R1_FB6_Pos (6U) 2969 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ 2970 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ 2971 #define CAN_F12R1_FB7_Pos (7U) 2972 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ 2973 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ 2974 #define CAN_F12R1_FB8_Pos (8U) 2975 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ 2976 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ 2977 #define CAN_F12R1_FB9_Pos (9U) 2978 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ 2979 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ 2980 #define CAN_F12R1_FB10_Pos (10U) 2981 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ 2982 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ 2983 #define CAN_F12R1_FB11_Pos (11U) 2984 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ 2985 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ 2986 #define CAN_F12R1_FB12_Pos (12U) 2987 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ 2988 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ 2989 #define CAN_F12R1_FB13_Pos (13U) 2990 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ 2991 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ 2992 #define CAN_F12R1_FB14_Pos (14U) 2993 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ 2994 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ 2995 #define CAN_F12R1_FB15_Pos (15U) 2996 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ 2997 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ 2998 #define CAN_F12R1_FB16_Pos (16U) 2999 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ 3000 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ 3001 #define CAN_F12R1_FB17_Pos (17U) 3002 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ 3003 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ 3004 #define CAN_F12R1_FB18_Pos (18U) 3005 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ 3006 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ 3007 #define CAN_F12R1_FB19_Pos (19U) 3008 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ 3009 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ 3010 #define CAN_F12R1_FB20_Pos (20U) 3011 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ 3012 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ 3013 #define CAN_F12R1_FB21_Pos (21U) 3014 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ 3015 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ 3016 #define CAN_F12R1_FB22_Pos (22U) 3017 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ 3018 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ 3019 #define CAN_F12R1_FB23_Pos (23U) 3020 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ 3021 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ 3022 #define CAN_F12R1_FB24_Pos (24U) 3023 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ 3024 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ 3025 #define CAN_F12R1_FB25_Pos (25U) 3026 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ 3027 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ 3028 #define CAN_F12R1_FB26_Pos (26U) 3029 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ 3030 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ 3031 #define CAN_F12R1_FB27_Pos (27U) 3032 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ 3033 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ 3034 #define CAN_F12R1_FB28_Pos (28U) 3035 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ 3036 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ 3037 #define CAN_F12R1_FB29_Pos (29U) 3038 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ 3039 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ 3040 #define CAN_F12R1_FB30_Pos (30U) 3041 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ 3042 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ 3043 #define CAN_F12R1_FB31_Pos (31U) 3044 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ 3045 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ 3046 3047 /******************* Bit definition for CAN_F13R1 register ******************/ 3048 #define CAN_F13R1_FB0_Pos (0U) 3049 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ 3050 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ 3051 #define CAN_F13R1_FB1_Pos (1U) 3052 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ 3053 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ 3054 #define CAN_F13R1_FB2_Pos (2U) 3055 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ 3056 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ 3057 #define CAN_F13R1_FB3_Pos (3U) 3058 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ 3059 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ 3060 #define CAN_F13R1_FB4_Pos (4U) 3061 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ 3062 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ 3063 #define CAN_F13R1_FB5_Pos (5U) 3064 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ 3065 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ 3066 #define CAN_F13R1_FB6_Pos (6U) 3067 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ 3068 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ 3069 #define CAN_F13R1_FB7_Pos (7U) 3070 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ 3071 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ 3072 #define CAN_F13R1_FB8_Pos (8U) 3073 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ 3074 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ 3075 #define CAN_F13R1_FB9_Pos (9U) 3076 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ 3077 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ 3078 #define CAN_F13R1_FB10_Pos (10U) 3079 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ 3080 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ 3081 #define CAN_F13R1_FB11_Pos (11U) 3082 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ 3083 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ 3084 #define CAN_F13R1_FB12_Pos (12U) 3085 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ 3086 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ 3087 #define CAN_F13R1_FB13_Pos (13U) 3088 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ 3089 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ 3090 #define CAN_F13R1_FB14_Pos (14U) 3091 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ 3092 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ 3093 #define CAN_F13R1_FB15_Pos (15U) 3094 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ 3095 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ 3096 #define CAN_F13R1_FB16_Pos (16U) 3097 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ 3098 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ 3099 #define CAN_F13R1_FB17_Pos (17U) 3100 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ 3101 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ 3102 #define CAN_F13R1_FB18_Pos (18U) 3103 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ 3104 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ 3105 #define CAN_F13R1_FB19_Pos (19U) 3106 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ 3107 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ 3108 #define CAN_F13R1_FB20_Pos (20U) 3109 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ 3110 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ 3111 #define CAN_F13R1_FB21_Pos (21U) 3112 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ 3113 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ 3114 #define CAN_F13R1_FB22_Pos (22U) 3115 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ 3116 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ 3117 #define CAN_F13R1_FB23_Pos (23U) 3118 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ 3119 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ 3120 #define CAN_F13R1_FB24_Pos (24U) 3121 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ 3122 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ 3123 #define CAN_F13R1_FB25_Pos (25U) 3124 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ 3125 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ 3126 #define CAN_F13R1_FB26_Pos (26U) 3127 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ 3128 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ 3129 #define CAN_F13R1_FB27_Pos (27U) 3130 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ 3131 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ 3132 #define CAN_F13R1_FB28_Pos (28U) 3133 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ 3134 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ 3135 #define CAN_F13R1_FB29_Pos (29U) 3136 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ 3137 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ 3138 #define CAN_F13R1_FB30_Pos (30U) 3139 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ 3140 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ 3141 #define CAN_F13R1_FB31_Pos (31U) 3142 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ 3143 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ 3144 3145 /******************* Bit definition for CAN_F0R2 register *******************/ 3146 #define CAN_F0R2_FB0_Pos (0U) 3147 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ 3148 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ 3149 #define CAN_F0R2_FB1_Pos (1U) 3150 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ 3151 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ 3152 #define CAN_F0R2_FB2_Pos (2U) 3153 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ 3154 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ 3155 #define CAN_F0R2_FB3_Pos (3U) 3156 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ 3157 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ 3158 #define CAN_F0R2_FB4_Pos (4U) 3159 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ 3160 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ 3161 #define CAN_F0R2_FB5_Pos (5U) 3162 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ 3163 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ 3164 #define CAN_F0R2_FB6_Pos (6U) 3165 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ 3166 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ 3167 #define CAN_F0R2_FB7_Pos (7U) 3168 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ 3169 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ 3170 #define CAN_F0R2_FB8_Pos (8U) 3171 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ 3172 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ 3173 #define CAN_F0R2_FB9_Pos (9U) 3174 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ 3175 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ 3176 #define CAN_F0R2_FB10_Pos (10U) 3177 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ 3178 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ 3179 #define CAN_F0R2_FB11_Pos (11U) 3180 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ 3181 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ 3182 #define CAN_F0R2_FB12_Pos (12U) 3183 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ 3184 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ 3185 #define CAN_F0R2_FB13_Pos (13U) 3186 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ 3187 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ 3188 #define CAN_F0R2_FB14_Pos (14U) 3189 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ 3190 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ 3191 #define CAN_F0R2_FB15_Pos (15U) 3192 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ 3193 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ 3194 #define CAN_F0R2_FB16_Pos (16U) 3195 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ 3196 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ 3197 #define CAN_F0R2_FB17_Pos (17U) 3198 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ 3199 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ 3200 #define CAN_F0R2_FB18_Pos (18U) 3201 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ 3202 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ 3203 #define CAN_F0R2_FB19_Pos (19U) 3204 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ 3205 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ 3206 #define CAN_F0R2_FB20_Pos (20U) 3207 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ 3208 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ 3209 #define CAN_F0R2_FB21_Pos (21U) 3210 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ 3211 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ 3212 #define CAN_F0R2_FB22_Pos (22U) 3213 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ 3214 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ 3215 #define CAN_F0R2_FB23_Pos (23U) 3216 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ 3217 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ 3218 #define CAN_F0R2_FB24_Pos (24U) 3219 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ 3220 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ 3221 #define CAN_F0R2_FB25_Pos (25U) 3222 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ 3223 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ 3224 #define CAN_F0R2_FB26_Pos (26U) 3225 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ 3226 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ 3227 #define CAN_F0R2_FB27_Pos (27U) 3228 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ 3229 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ 3230 #define CAN_F0R2_FB28_Pos (28U) 3231 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ 3232 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ 3233 #define CAN_F0R2_FB29_Pos (29U) 3234 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ 3235 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ 3236 #define CAN_F0R2_FB30_Pos (30U) 3237 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ 3238 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ 3239 #define CAN_F0R2_FB31_Pos (31U) 3240 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ 3241 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ 3242 3243 /******************* Bit definition for CAN_F1R2 register *******************/ 3244 #define CAN_F1R2_FB0_Pos (0U) 3245 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ 3246 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ 3247 #define CAN_F1R2_FB1_Pos (1U) 3248 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ 3249 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ 3250 #define CAN_F1R2_FB2_Pos (2U) 3251 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ 3252 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ 3253 #define CAN_F1R2_FB3_Pos (3U) 3254 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ 3255 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ 3256 #define CAN_F1R2_FB4_Pos (4U) 3257 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ 3258 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ 3259 #define CAN_F1R2_FB5_Pos (5U) 3260 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ 3261 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ 3262 #define CAN_F1R2_FB6_Pos (6U) 3263 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ 3264 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ 3265 #define CAN_F1R2_FB7_Pos (7U) 3266 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ 3267 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ 3268 #define CAN_F1R2_FB8_Pos (8U) 3269 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ 3270 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ 3271 #define CAN_F1R2_FB9_Pos (9U) 3272 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ 3273 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ 3274 #define CAN_F1R2_FB10_Pos (10U) 3275 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ 3276 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ 3277 #define CAN_F1R2_FB11_Pos (11U) 3278 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ 3279 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ 3280 #define CAN_F1R2_FB12_Pos (12U) 3281 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ 3282 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ 3283 #define CAN_F1R2_FB13_Pos (13U) 3284 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ 3285 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ 3286 #define CAN_F1R2_FB14_Pos (14U) 3287 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ 3288 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ 3289 #define CAN_F1R2_FB15_Pos (15U) 3290 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ 3291 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ 3292 #define CAN_F1R2_FB16_Pos (16U) 3293 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ 3294 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ 3295 #define CAN_F1R2_FB17_Pos (17U) 3296 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ 3297 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ 3298 #define CAN_F1R2_FB18_Pos (18U) 3299 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ 3300 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ 3301 #define CAN_F1R2_FB19_Pos (19U) 3302 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ 3303 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ 3304 #define CAN_F1R2_FB20_Pos (20U) 3305 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ 3306 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ 3307 #define CAN_F1R2_FB21_Pos (21U) 3308 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ 3309 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ 3310 #define CAN_F1R2_FB22_Pos (22U) 3311 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ 3312 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ 3313 #define CAN_F1R2_FB23_Pos (23U) 3314 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ 3315 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ 3316 #define CAN_F1R2_FB24_Pos (24U) 3317 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ 3318 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ 3319 #define CAN_F1R2_FB25_Pos (25U) 3320 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ 3321 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ 3322 #define CAN_F1R2_FB26_Pos (26U) 3323 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ 3324 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ 3325 #define CAN_F1R2_FB27_Pos (27U) 3326 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ 3327 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ 3328 #define CAN_F1R2_FB28_Pos (28U) 3329 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ 3330 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ 3331 #define CAN_F1R2_FB29_Pos (29U) 3332 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ 3333 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ 3334 #define CAN_F1R2_FB30_Pos (30U) 3335 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ 3336 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ 3337 #define CAN_F1R2_FB31_Pos (31U) 3338 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ 3339 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ 3340 3341 /******************* Bit definition for CAN_F2R2 register *******************/ 3342 #define CAN_F2R2_FB0_Pos (0U) 3343 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ 3344 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ 3345 #define CAN_F2R2_FB1_Pos (1U) 3346 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ 3347 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ 3348 #define CAN_F2R2_FB2_Pos (2U) 3349 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ 3350 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ 3351 #define CAN_F2R2_FB3_Pos (3U) 3352 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ 3353 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ 3354 #define CAN_F2R2_FB4_Pos (4U) 3355 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ 3356 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ 3357 #define CAN_F2R2_FB5_Pos (5U) 3358 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ 3359 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ 3360 #define CAN_F2R2_FB6_Pos (6U) 3361 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ 3362 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ 3363 #define CAN_F2R2_FB7_Pos (7U) 3364 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ 3365 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ 3366 #define CAN_F2R2_FB8_Pos (8U) 3367 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ 3368 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ 3369 #define CAN_F2R2_FB9_Pos (9U) 3370 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ 3371 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ 3372 #define CAN_F2R2_FB10_Pos (10U) 3373 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ 3374 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ 3375 #define CAN_F2R2_FB11_Pos (11U) 3376 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ 3377 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ 3378 #define CAN_F2R2_FB12_Pos (12U) 3379 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ 3380 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ 3381 #define CAN_F2R2_FB13_Pos (13U) 3382 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ 3383 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ 3384 #define CAN_F2R2_FB14_Pos (14U) 3385 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ 3386 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ 3387 #define CAN_F2R2_FB15_Pos (15U) 3388 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ 3389 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ 3390 #define CAN_F2R2_FB16_Pos (16U) 3391 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ 3392 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ 3393 #define CAN_F2R2_FB17_Pos (17U) 3394 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ 3395 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ 3396 #define CAN_F2R2_FB18_Pos (18U) 3397 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ 3398 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ 3399 #define CAN_F2R2_FB19_Pos (19U) 3400 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ 3401 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ 3402 #define CAN_F2R2_FB20_Pos (20U) 3403 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ 3404 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ 3405 #define CAN_F2R2_FB21_Pos (21U) 3406 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ 3407 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ 3408 #define CAN_F2R2_FB22_Pos (22U) 3409 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ 3410 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ 3411 #define CAN_F2R2_FB23_Pos (23U) 3412 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ 3413 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ 3414 #define CAN_F2R2_FB24_Pos (24U) 3415 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ 3416 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ 3417 #define CAN_F2R2_FB25_Pos (25U) 3418 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ 3419 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ 3420 #define CAN_F2R2_FB26_Pos (26U) 3421 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ 3422 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ 3423 #define CAN_F2R2_FB27_Pos (27U) 3424 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ 3425 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ 3426 #define CAN_F2R2_FB28_Pos (28U) 3427 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ 3428 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ 3429 #define CAN_F2R2_FB29_Pos (29U) 3430 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ 3431 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ 3432 #define CAN_F2R2_FB30_Pos (30U) 3433 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ 3434 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ 3435 #define CAN_F2R2_FB31_Pos (31U) 3436 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ 3437 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ 3438 3439 /******************* Bit definition for CAN_F3R2 register *******************/ 3440 #define CAN_F3R2_FB0_Pos (0U) 3441 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ 3442 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ 3443 #define CAN_F3R2_FB1_Pos (1U) 3444 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ 3445 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ 3446 #define CAN_F3R2_FB2_Pos (2U) 3447 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ 3448 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ 3449 #define CAN_F3R2_FB3_Pos (3U) 3450 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ 3451 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ 3452 #define CAN_F3R2_FB4_Pos (4U) 3453 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ 3454 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ 3455 #define CAN_F3R2_FB5_Pos (5U) 3456 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ 3457 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ 3458 #define CAN_F3R2_FB6_Pos (6U) 3459 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ 3460 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ 3461 #define CAN_F3R2_FB7_Pos (7U) 3462 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ 3463 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ 3464 #define CAN_F3R2_FB8_Pos (8U) 3465 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ 3466 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ 3467 #define CAN_F3R2_FB9_Pos (9U) 3468 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ 3469 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ 3470 #define CAN_F3R2_FB10_Pos (10U) 3471 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ 3472 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ 3473 #define CAN_F3R2_FB11_Pos (11U) 3474 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ 3475 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ 3476 #define CAN_F3R2_FB12_Pos (12U) 3477 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ 3478 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ 3479 #define CAN_F3R2_FB13_Pos (13U) 3480 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ 3481 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ 3482 #define CAN_F3R2_FB14_Pos (14U) 3483 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ 3484 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ 3485 #define CAN_F3R2_FB15_Pos (15U) 3486 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ 3487 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ 3488 #define CAN_F3R2_FB16_Pos (16U) 3489 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ 3490 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ 3491 #define CAN_F3R2_FB17_Pos (17U) 3492 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ 3493 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ 3494 #define CAN_F3R2_FB18_Pos (18U) 3495 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ 3496 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ 3497 #define CAN_F3R2_FB19_Pos (19U) 3498 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ 3499 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ 3500 #define CAN_F3R2_FB20_Pos (20U) 3501 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ 3502 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ 3503 #define CAN_F3R2_FB21_Pos (21U) 3504 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ 3505 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ 3506 #define CAN_F3R2_FB22_Pos (22U) 3507 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ 3508 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ 3509 #define CAN_F3R2_FB23_Pos (23U) 3510 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ 3511 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ 3512 #define CAN_F3R2_FB24_Pos (24U) 3513 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ 3514 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ 3515 #define CAN_F3R2_FB25_Pos (25U) 3516 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ 3517 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ 3518 #define CAN_F3R2_FB26_Pos (26U) 3519 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ 3520 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ 3521 #define CAN_F3R2_FB27_Pos (27U) 3522 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ 3523 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ 3524 #define CAN_F3R2_FB28_Pos (28U) 3525 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ 3526 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ 3527 #define CAN_F3R2_FB29_Pos (29U) 3528 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ 3529 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ 3530 #define CAN_F3R2_FB30_Pos (30U) 3531 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ 3532 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ 3533 #define CAN_F3R2_FB31_Pos (31U) 3534 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ 3535 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ 3536 3537 /******************* Bit definition for CAN_F4R2 register *******************/ 3538 #define CAN_F4R2_FB0_Pos (0U) 3539 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ 3540 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ 3541 #define CAN_F4R2_FB1_Pos (1U) 3542 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ 3543 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ 3544 #define CAN_F4R2_FB2_Pos (2U) 3545 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ 3546 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ 3547 #define CAN_F4R2_FB3_Pos (3U) 3548 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ 3549 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ 3550 #define CAN_F4R2_FB4_Pos (4U) 3551 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ 3552 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ 3553 #define CAN_F4R2_FB5_Pos (5U) 3554 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ 3555 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ 3556 #define CAN_F4R2_FB6_Pos (6U) 3557 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ 3558 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ 3559 #define CAN_F4R2_FB7_Pos (7U) 3560 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ 3561 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ 3562 #define CAN_F4R2_FB8_Pos (8U) 3563 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ 3564 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ 3565 #define CAN_F4R2_FB9_Pos (9U) 3566 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ 3567 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ 3568 #define CAN_F4R2_FB10_Pos (10U) 3569 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ 3570 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ 3571 #define CAN_F4R2_FB11_Pos (11U) 3572 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ 3573 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ 3574 #define CAN_F4R2_FB12_Pos (12U) 3575 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ 3576 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ 3577 #define CAN_F4R2_FB13_Pos (13U) 3578 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ 3579 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ 3580 #define CAN_F4R2_FB14_Pos (14U) 3581 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ 3582 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ 3583 #define CAN_F4R2_FB15_Pos (15U) 3584 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ 3585 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ 3586 #define CAN_F4R2_FB16_Pos (16U) 3587 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ 3588 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ 3589 #define CAN_F4R2_FB17_Pos (17U) 3590 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ 3591 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ 3592 #define CAN_F4R2_FB18_Pos (18U) 3593 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ 3594 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ 3595 #define CAN_F4R2_FB19_Pos (19U) 3596 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ 3597 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ 3598 #define CAN_F4R2_FB20_Pos (20U) 3599 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ 3600 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ 3601 #define CAN_F4R2_FB21_Pos (21U) 3602 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ 3603 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ 3604 #define CAN_F4R2_FB22_Pos (22U) 3605 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ 3606 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ 3607 #define CAN_F4R2_FB23_Pos (23U) 3608 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ 3609 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ 3610 #define CAN_F4R2_FB24_Pos (24U) 3611 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ 3612 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ 3613 #define CAN_F4R2_FB25_Pos (25U) 3614 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ 3615 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ 3616 #define CAN_F4R2_FB26_Pos (26U) 3617 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ 3618 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ 3619 #define CAN_F4R2_FB27_Pos (27U) 3620 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ 3621 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ 3622 #define CAN_F4R2_FB28_Pos (28U) 3623 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ 3624 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ 3625 #define CAN_F4R2_FB29_Pos (29U) 3626 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ 3627 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ 3628 #define CAN_F4R2_FB30_Pos (30U) 3629 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ 3630 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ 3631 #define CAN_F4R2_FB31_Pos (31U) 3632 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ 3633 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ 3634 3635 /******************* Bit definition for CAN_F5R2 register *******************/ 3636 #define CAN_F5R2_FB0_Pos (0U) 3637 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ 3638 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ 3639 #define CAN_F5R2_FB1_Pos (1U) 3640 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ 3641 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ 3642 #define CAN_F5R2_FB2_Pos (2U) 3643 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ 3644 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ 3645 #define CAN_F5R2_FB3_Pos (3U) 3646 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ 3647 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ 3648 #define CAN_F5R2_FB4_Pos (4U) 3649 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ 3650 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ 3651 #define CAN_F5R2_FB5_Pos (5U) 3652 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ 3653 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ 3654 #define CAN_F5R2_FB6_Pos (6U) 3655 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ 3656 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ 3657 #define CAN_F5R2_FB7_Pos (7U) 3658 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ 3659 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ 3660 #define CAN_F5R2_FB8_Pos (8U) 3661 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ 3662 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ 3663 #define CAN_F5R2_FB9_Pos (9U) 3664 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ 3665 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ 3666 #define CAN_F5R2_FB10_Pos (10U) 3667 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ 3668 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ 3669 #define CAN_F5R2_FB11_Pos (11U) 3670 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ 3671 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ 3672 #define CAN_F5R2_FB12_Pos (12U) 3673 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ 3674 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ 3675 #define CAN_F5R2_FB13_Pos (13U) 3676 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ 3677 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ 3678 #define CAN_F5R2_FB14_Pos (14U) 3679 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ 3680 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ 3681 #define CAN_F5R2_FB15_Pos (15U) 3682 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ 3683 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ 3684 #define CAN_F5R2_FB16_Pos (16U) 3685 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ 3686 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ 3687 #define CAN_F5R2_FB17_Pos (17U) 3688 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ 3689 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ 3690 #define CAN_F5R2_FB18_Pos (18U) 3691 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ 3692 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ 3693 #define CAN_F5R2_FB19_Pos (19U) 3694 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ 3695 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ 3696 #define CAN_F5R2_FB20_Pos (20U) 3697 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ 3698 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ 3699 #define CAN_F5R2_FB21_Pos (21U) 3700 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ 3701 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ 3702 #define CAN_F5R2_FB22_Pos (22U) 3703 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ 3704 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ 3705 #define CAN_F5R2_FB23_Pos (23U) 3706 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ 3707 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ 3708 #define CAN_F5R2_FB24_Pos (24U) 3709 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ 3710 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ 3711 #define CAN_F5R2_FB25_Pos (25U) 3712 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ 3713 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ 3714 #define CAN_F5R2_FB26_Pos (26U) 3715 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ 3716 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ 3717 #define CAN_F5R2_FB27_Pos (27U) 3718 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ 3719 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ 3720 #define CAN_F5R2_FB28_Pos (28U) 3721 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ 3722 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ 3723 #define CAN_F5R2_FB29_Pos (29U) 3724 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ 3725 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ 3726 #define CAN_F5R2_FB30_Pos (30U) 3727 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ 3728 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ 3729 #define CAN_F5R2_FB31_Pos (31U) 3730 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ 3731 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ 3732 3733 /******************* Bit definition for CAN_F6R2 register *******************/ 3734 #define CAN_F6R2_FB0_Pos (0U) 3735 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ 3736 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ 3737 #define CAN_F6R2_FB1_Pos (1U) 3738 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ 3739 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ 3740 #define CAN_F6R2_FB2_Pos (2U) 3741 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ 3742 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ 3743 #define CAN_F6R2_FB3_Pos (3U) 3744 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ 3745 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ 3746 #define CAN_F6R2_FB4_Pos (4U) 3747 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ 3748 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ 3749 #define CAN_F6R2_FB5_Pos (5U) 3750 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ 3751 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ 3752 #define CAN_F6R2_FB6_Pos (6U) 3753 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ 3754 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ 3755 #define CAN_F6R2_FB7_Pos (7U) 3756 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ 3757 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ 3758 #define CAN_F6R2_FB8_Pos (8U) 3759 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ 3760 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ 3761 #define CAN_F6R2_FB9_Pos (9U) 3762 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ 3763 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ 3764 #define CAN_F6R2_FB10_Pos (10U) 3765 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ 3766 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ 3767 #define CAN_F6R2_FB11_Pos (11U) 3768 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ 3769 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ 3770 #define CAN_F6R2_FB12_Pos (12U) 3771 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ 3772 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ 3773 #define CAN_F6R2_FB13_Pos (13U) 3774 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ 3775 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ 3776 #define CAN_F6R2_FB14_Pos (14U) 3777 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ 3778 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ 3779 #define CAN_F6R2_FB15_Pos (15U) 3780 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ 3781 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ 3782 #define CAN_F6R2_FB16_Pos (16U) 3783 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ 3784 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ 3785 #define CAN_F6R2_FB17_Pos (17U) 3786 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ 3787 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ 3788 #define CAN_F6R2_FB18_Pos (18U) 3789 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ 3790 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ 3791 #define CAN_F6R2_FB19_Pos (19U) 3792 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ 3793 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ 3794 #define CAN_F6R2_FB20_Pos (20U) 3795 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ 3796 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ 3797 #define CAN_F6R2_FB21_Pos (21U) 3798 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ 3799 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ 3800 #define CAN_F6R2_FB22_Pos (22U) 3801 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ 3802 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ 3803 #define CAN_F6R2_FB23_Pos (23U) 3804 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ 3805 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ 3806 #define CAN_F6R2_FB24_Pos (24U) 3807 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ 3808 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ 3809 #define CAN_F6R2_FB25_Pos (25U) 3810 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ 3811 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ 3812 #define CAN_F6R2_FB26_Pos (26U) 3813 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ 3814 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ 3815 #define CAN_F6R2_FB27_Pos (27U) 3816 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ 3817 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ 3818 #define CAN_F6R2_FB28_Pos (28U) 3819 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ 3820 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ 3821 #define CAN_F6R2_FB29_Pos (29U) 3822 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ 3823 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ 3824 #define CAN_F6R2_FB30_Pos (30U) 3825 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ 3826 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ 3827 #define CAN_F6R2_FB31_Pos (31U) 3828 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ 3829 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ 3830 3831 /******************* Bit definition for CAN_F7R2 register *******************/ 3832 #define CAN_F7R2_FB0_Pos (0U) 3833 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ 3834 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ 3835 #define CAN_F7R2_FB1_Pos (1U) 3836 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ 3837 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ 3838 #define CAN_F7R2_FB2_Pos (2U) 3839 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ 3840 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ 3841 #define CAN_F7R2_FB3_Pos (3U) 3842 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ 3843 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ 3844 #define CAN_F7R2_FB4_Pos (4U) 3845 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ 3846 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ 3847 #define CAN_F7R2_FB5_Pos (5U) 3848 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ 3849 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ 3850 #define CAN_F7R2_FB6_Pos (6U) 3851 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ 3852 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ 3853 #define CAN_F7R2_FB7_Pos (7U) 3854 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ 3855 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ 3856 #define CAN_F7R2_FB8_Pos (8U) 3857 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ 3858 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ 3859 #define CAN_F7R2_FB9_Pos (9U) 3860 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ 3861 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ 3862 #define CAN_F7R2_FB10_Pos (10U) 3863 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ 3864 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ 3865 #define CAN_F7R2_FB11_Pos (11U) 3866 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ 3867 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ 3868 #define CAN_F7R2_FB12_Pos (12U) 3869 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ 3870 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ 3871 #define CAN_F7R2_FB13_Pos (13U) 3872 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ 3873 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ 3874 #define CAN_F7R2_FB14_Pos (14U) 3875 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ 3876 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ 3877 #define CAN_F7R2_FB15_Pos (15U) 3878 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ 3879 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ 3880 #define CAN_F7R2_FB16_Pos (16U) 3881 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ 3882 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ 3883 #define CAN_F7R2_FB17_Pos (17U) 3884 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ 3885 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ 3886 #define CAN_F7R2_FB18_Pos (18U) 3887 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ 3888 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ 3889 #define CAN_F7R2_FB19_Pos (19U) 3890 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ 3891 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ 3892 #define CAN_F7R2_FB20_Pos (20U) 3893 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ 3894 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ 3895 #define CAN_F7R2_FB21_Pos (21U) 3896 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ 3897 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ 3898 #define CAN_F7R2_FB22_Pos (22U) 3899 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ 3900 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ 3901 #define CAN_F7R2_FB23_Pos (23U) 3902 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ 3903 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ 3904 #define CAN_F7R2_FB24_Pos (24U) 3905 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ 3906 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ 3907 #define CAN_F7R2_FB25_Pos (25U) 3908 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ 3909 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ 3910 #define CAN_F7R2_FB26_Pos (26U) 3911 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ 3912 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ 3913 #define CAN_F7R2_FB27_Pos (27U) 3914 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ 3915 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ 3916 #define CAN_F7R2_FB28_Pos (28U) 3917 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ 3918 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ 3919 #define CAN_F7R2_FB29_Pos (29U) 3920 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ 3921 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ 3922 #define CAN_F7R2_FB30_Pos (30U) 3923 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ 3924 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ 3925 #define CAN_F7R2_FB31_Pos (31U) 3926 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ 3927 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ 3928 3929 /******************* Bit definition for CAN_F8R2 register *******************/ 3930 #define CAN_F8R2_FB0_Pos (0U) 3931 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ 3932 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ 3933 #define CAN_F8R2_FB1_Pos (1U) 3934 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ 3935 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ 3936 #define CAN_F8R2_FB2_Pos (2U) 3937 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ 3938 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ 3939 #define CAN_F8R2_FB3_Pos (3U) 3940 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ 3941 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ 3942 #define CAN_F8R2_FB4_Pos (4U) 3943 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ 3944 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ 3945 #define CAN_F8R2_FB5_Pos (5U) 3946 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ 3947 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ 3948 #define CAN_F8R2_FB6_Pos (6U) 3949 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ 3950 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ 3951 #define CAN_F8R2_FB7_Pos (7U) 3952 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ 3953 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ 3954 #define CAN_F8R2_FB8_Pos (8U) 3955 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ 3956 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ 3957 #define CAN_F8R2_FB9_Pos (9U) 3958 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ 3959 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ 3960 #define CAN_F8R2_FB10_Pos (10U) 3961 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ 3962 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ 3963 #define CAN_F8R2_FB11_Pos (11U) 3964 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ 3965 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ 3966 #define CAN_F8R2_FB12_Pos (12U) 3967 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ 3968 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ 3969 #define CAN_F8R2_FB13_Pos (13U) 3970 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ 3971 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ 3972 #define CAN_F8R2_FB14_Pos (14U) 3973 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ 3974 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ 3975 #define CAN_F8R2_FB15_Pos (15U) 3976 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ 3977 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ 3978 #define CAN_F8R2_FB16_Pos (16U) 3979 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ 3980 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ 3981 #define CAN_F8R2_FB17_Pos (17U) 3982 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ 3983 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ 3984 #define CAN_F8R2_FB18_Pos (18U) 3985 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ 3986 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ 3987 #define CAN_F8R2_FB19_Pos (19U) 3988 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ 3989 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ 3990 #define CAN_F8R2_FB20_Pos (20U) 3991 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ 3992 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ 3993 #define CAN_F8R2_FB21_Pos (21U) 3994 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ 3995 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ 3996 #define CAN_F8R2_FB22_Pos (22U) 3997 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ 3998 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ 3999 #define CAN_F8R2_FB23_Pos (23U) 4000 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ 4001 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ 4002 #define CAN_F8R2_FB24_Pos (24U) 4003 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ 4004 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ 4005 #define CAN_F8R2_FB25_Pos (25U) 4006 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ 4007 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ 4008 #define CAN_F8R2_FB26_Pos (26U) 4009 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ 4010 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ 4011 #define CAN_F8R2_FB27_Pos (27U) 4012 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ 4013 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ 4014 #define CAN_F8R2_FB28_Pos (28U) 4015 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ 4016 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ 4017 #define CAN_F8R2_FB29_Pos (29U) 4018 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ 4019 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ 4020 #define CAN_F8R2_FB30_Pos (30U) 4021 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ 4022 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ 4023 #define CAN_F8R2_FB31_Pos (31U) 4024 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ 4025 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ 4026 4027 /******************* Bit definition for CAN_F9R2 register *******************/ 4028 #define CAN_F9R2_FB0_Pos (0U) 4029 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ 4030 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ 4031 #define CAN_F9R2_FB1_Pos (1U) 4032 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ 4033 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ 4034 #define CAN_F9R2_FB2_Pos (2U) 4035 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ 4036 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ 4037 #define CAN_F9R2_FB3_Pos (3U) 4038 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ 4039 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ 4040 #define CAN_F9R2_FB4_Pos (4U) 4041 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ 4042 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ 4043 #define CAN_F9R2_FB5_Pos (5U) 4044 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ 4045 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ 4046 #define CAN_F9R2_FB6_Pos (6U) 4047 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ 4048 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ 4049 #define CAN_F9R2_FB7_Pos (7U) 4050 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ 4051 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ 4052 #define CAN_F9R2_FB8_Pos (8U) 4053 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ 4054 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ 4055 #define CAN_F9R2_FB9_Pos (9U) 4056 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ 4057 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ 4058 #define CAN_F9R2_FB10_Pos (10U) 4059 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ 4060 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ 4061 #define CAN_F9R2_FB11_Pos (11U) 4062 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ 4063 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ 4064 #define CAN_F9R2_FB12_Pos (12U) 4065 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ 4066 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ 4067 #define CAN_F9R2_FB13_Pos (13U) 4068 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ 4069 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ 4070 #define CAN_F9R2_FB14_Pos (14U) 4071 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ 4072 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ 4073 #define CAN_F9R2_FB15_Pos (15U) 4074 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ 4075 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ 4076 #define CAN_F9R2_FB16_Pos (16U) 4077 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ 4078 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ 4079 #define CAN_F9R2_FB17_Pos (17U) 4080 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ 4081 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ 4082 #define CAN_F9R2_FB18_Pos (18U) 4083 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ 4084 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ 4085 #define CAN_F9R2_FB19_Pos (19U) 4086 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ 4087 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ 4088 #define CAN_F9R2_FB20_Pos (20U) 4089 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ 4090 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ 4091 #define CAN_F9R2_FB21_Pos (21U) 4092 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ 4093 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ 4094 #define CAN_F9R2_FB22_Pos (22U) 4095 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ 4096 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ 4097 #define CAN_F9R2_FB23_Pos (23U) 4098 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ 4099 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ 4100 #define CAN_F9R2_FB24_Pos (24U) 4101 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ 4102 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ 4103 #define CAN_F9R2_FB25_Pos (25U) 4104 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ 4105 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ 4106 #define CAN_F9R2_FB26_Pos (26U) 4107 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ 4108 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ 4109 #define CAN_F9R2_FB27_Pos (27U) 4110 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ 4111 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ 4112 #define CAN_F9R2_FB28_Pos (28U) 4113 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ 4114 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ 4115 #define CAN_F9R2_FB29_Pos (29U) 4116 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ 4117 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ 4118 #define CAN_F9R2_FB30_Pos (30U) 4119 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ 4120 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ 4121 #define CAN_F9R2_FB31_Pos (31U) 4122 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ 4123 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ 4124 4125 /******************* Bit definition for CAN_F10R2 register ******************/ 4126 #define CAN_F10R2_FB0_Pos (0U) 4127 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ 4128 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ 4129 #define CAN_F10R2_FB1_Pos (1U) 4130 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ 4131 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ 4132 #define CAN_F10R2_FB2_Pos (2U) 4133 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ 4134 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ 4135 #define CAN_F10R2_FB3_Pos (3U) 4136 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ 4137 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ 4138 #define CAN_F10R2_FB4_Pos (4U) 4139 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ 4140 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ 4141 #define CAN_F10R2_FB5_Pos (5U) 4142 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ 4143 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ 4144 #define CAN_F10R2_FB6_Pos (6U) 4145 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ 4146 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ 4147 #define CAN_F10R2_FB7_Pos (7U) 4148 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ 4149 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ 4150 #define CAN_F10R2_FB8_Pos (8U) 4151 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ 4152 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ 4153 #define CAN_F10R2_FB9_Pos (9U) 4154 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ 4155 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ 4156 #define CAN_F10R2_FB10_Pos (10U) 4157 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ 4158 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ 4159 #define CAN_F10R2_FB11_Pos (11U) 4160 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ 4161 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ 4162 #define CAN_F10R2_FB12_Pos (12U) 4163 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ 4164 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ 4165 #define CAN_F10R2_FB13_Pos (13U) 4166 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ 4167 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ 4168 #define CAN_F10R2_FB14_Pos (14U) 4169 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ 4170 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ 4171 #define CAN_F10R2_FB15_Pos (15U) 4172 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ 4173 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ 4174 #define CAN_F10R2_FB16_Pos (16U) 4175 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ 4176 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ 4177 #define CAN_F10R2_FB17_Pos (17U) 4178 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ 4179 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ 4180 #define CAN_F10R2_FB18_Pos (18U) 4181 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ 4182 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ 4183 #define CAN_F10R2_FB19_Pos (19U) 4184 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ 4185 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ 4186 #define CAN_F10R2_FB20_Pos (20U) 4187 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ 4188 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ 4189 #define CAN_F10R2_FB21_Pos (21U) 4190 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ 4191 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ 4192 #define CAN_F10R2_FB22_Pos (22U) 4193 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ 4194 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ 4195 #define CAN_F10R2_FB23_Pos (23U) 4196 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ 4197 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ 4198 #define CAN_F10R2_FB24_Pos (24U) 4199 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ 4200 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ 4201 #define CAN_F10R2_FB25_Pos (25U) 4202 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ 4203 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ 4204 #define CAN_F10R2_FB26_Pos (26U) 4205 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ 4206 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ 4207 #define CAN_F10R2_FB27_Pos (27U) 4208 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ 4209 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ 4210 #define CAN_F10R2_FB28_Pos (28U) 4211 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ 4212 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ 4213 #define CAN_F10R2_FB29_Pos (29U) 4214 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ 4215 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ 4216 #define CAN_F10R2_FB30_Pos (30U) 4217 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ 4218 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ 4219 #define CAN_F10R2_FB31_Pos (31U) 4220 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ 4221 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ 4222 4223 /******************* Bit definition for CAN_F11R2 register ******************/ 4224 #define CAN_F11R2_FB0_Pos (0U) 4225 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ 4226 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ 4227 #define CAN_F11R2_FB1_Pos (1U) 4228 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ 4229 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ 4230 #define CAN_F11R2_FB2_Pos (2U) 4231 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ 4232 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ 4233 #define CAN_F11R2_FB3_Pos (3U) 4234 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ 4235 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ 4236 #define CAN_F11R2_FB4_Pos (4U) 4237 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ 4238 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ 4239 #define CAN_F11R2_FB5_Pos (5U) 4240 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ 4241 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ 4242 #define CAN_F11R2_FB6_Pos (6U) 4243 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ 4244 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ 4245 #define CAN_F11R2_FB7_Pos (7U) 4246 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ 4247 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ 4248 #define CAN_F11R2_FB8_Pos (8U) 4249 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ 4250 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ 4251 #define CAN_F11R2_FB9_Pos (9U) 4252 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ 4253 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ 4254 #define CAN_F11R2_FB10_Pos (10U) 4255 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ 4256 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ 4257 #define CAN_F11R2_FB11_Pos (11U) 4258 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ 4259 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ 4260 #define CAN_F11R2_FB12_Pos (12U) 4261 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ 4262 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ 4263 #define CAN_F11R2_FB13_Pos (13U) 4264 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ 4265 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ 4266 #define CAN_F11R2_FB14_Pos (14U) 4267 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ 4268 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ 4269 #define CAN_F11R2_FB15_Pos (15U) 4270 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ 4271 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ 4272 #define CAN_F11R2_FB16_Pos (16U) 4273 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ 4274 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ 4275 #define CAN_F11R2_FB17_Pos (17U) 4276 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ 4277 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ 4278 #define CAN_F11R2_FB18_Pos (18U) 4279 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ 4280 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ 4281 #define CAN_F11R2_FB19_Pos (19U) 4282 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ 4283 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ 4284 #define CAN_F11R2_FB20_Pos (20U) 4285 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ 4286 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ 4287 #define CAN_F11R2_FB21_Pos (21U) 4288 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ 4289 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ 4290 #define CAN_F11R2_FB22_Pos (22U) 4291 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ 4292 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ 4293 #define CAN_F11R2_FB23_Pos (23U) 4294 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ 4295 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ 4296 #define CAN_F11R2_FB24_Pos (24U) 4297 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ 4298 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ 4299 #define CAN_F11R2_FB25_Pos (25U) 4300 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ 4301 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ 4302 #define CAN_F11R2_FB26_Pos (26U) 4303 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ 4304 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ 4305 #define CAN_F11R2_FB27_Pos (27U) 4306 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ 4307 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ 4308 #define CAN_F11R2_FB28_Pos (28U) 4309 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ 4310 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ 4311 #define CAN_F11R2_FB29_Pos (29U) 4312 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ 4313 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ 4314 #define CAN_F11R2_FB30_Pos (30U) 4315 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ 4316 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ 4317 #define CAN_F11R2_FB31_Pos (31U) 4318 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ 4319 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ 4320 4321 /******************* Bit definition for CAN_F12R2 register ******************/ 4322 #define CAN_F12R2_FB0_Pos (0U) 4323 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ 4324 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ 4325 #define CAN_F12R2_FB1_Pos (1U) 4326 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ 4327 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ 4328 #define CAN_F12R2_FB2_Pos (2U) 4329 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ 4330 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ 4331 #define CAN_F12R2_FB3_Pos (3U) 4332 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ 4333 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ 4334 #define CAN_F12R2_FB4_Pos (4U) 4335 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ 4336 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ 4337 #define CAN_F12R2_FB5_Pos (5U) 4338 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ 4339 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ 4340 #define CAN_F12R2_FB6_Pos (6U) 4341 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ 4342 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ 4343 #define CAN_F12R2_FB7_Pos (7U) 4344 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ 4345 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ 4346 #define CAN_F12R2_FB8_Pos (8U) 4347 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ 4348 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ 4349 #define CAN_F12R2_FB9_Pos (9U) 4350 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ 4351 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ 4352 #define CAN_F12R2_FB10_Pos (10U) 4353 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ 4354 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ 4355 #define CAN_F12R2_FB11_Pos (11U) 4356 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ 4357 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ 4358 #define CAN_F12R2_FB12_Pos (12U) 4359 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ 4360 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ 4361 #define CAN_F12R2_FB13_Pos (13U) 4362 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ 4363 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ 4364 #define CAN_F12R2_FB14_Pos (14U) 4365 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ 4366 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ 4367 #define CAN_F12R2_FB15_Pos (15U) 4368 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ 4369 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ 4370 #define CAN_F12R2_FB16_Pos (16U) 4371 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ 4372 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ 4373 #define CAN_F12R2_FB17_Pos (17U) 4374 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ 4375 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ 4376 #define CAN_F12R2_FB18_Pos (18U) 4377 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ 4378 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ 4379 #define CAN_F12R2_FB19_Pos (19U) 4380 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ 4381 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ 4382 #define CAN_F12R2_FB20_Pos (20U) 4383 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ 4384 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ 4385 #define CAN_F12R2_FB21_Pos (21U) 4386 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ 4387 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ 4388 #define CAN_F12R2_FB22_Pos (22U) 4389 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ 4390 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ 4391 #define CAN_F12R2_FB23_Pos (23U) 4392 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ 4393 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ 4394 #define CAN_F12R2_FB24_Pos (24U) 4395 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ 4396 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ 4397 #define CAN_F12R2_FB25_Pos (25U) 4398 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ 4399 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ 4400 #define CAN_F12R2_FB26_Pos (26U) 4401 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ 4402 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ 4403 #define CAN_F12R2_FB27_Pos (27U) 4404 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ 4405 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ 4406 #define CAN_F12R2_FB28_Pos (28U) 4407 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ 4408 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ 4409 #define CAN_F12R2_FB29_Pos (29U) 4410 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ 4411 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ 4412 #define CAN_F12R2_FB30_Pos (30U) 4413 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ 4414 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ 4415 #define CAN_F12R2_FB31_Pos (31U) 4416 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ 4417 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ 4418 4419 /******************* Bit definition for CAN_F13R2 register ******************/ 4420 #define CAN_F13R2_FB0_Pos (0U) 4421 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ 4422 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ 4423 #define CAN_F13R2_FB1_Pos (1U) 4424 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ 4425 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ 4426 #define CAN_F13R2_FB2_Pos (2U) 4427 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ 4428 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ 4429 #define CAN_F13R2_FB3_Pos (3U) 4430 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ 4431 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ 4432 #define CAN_F13R2_FB4_Pos (4U) 4433 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ 4434 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ 4435 #define CAN_F13R2_FB5_Pos (5U) 4436 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ 4437 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ 4438 #define CAN_F13R2_FB6_Pos (6U) 4439 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ 4440 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ 4441 #define CAN_F13R2_FB7_Pos (7U) 4442 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ 4443 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ 4444 #define CAN_F13R2_FB8_Pos (8U) 4445 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ 4446 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ 4447 #define CAN_F13R2_FB9_Pos (9U) 4448 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ 4449 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ 4450 #define CAN_F13R2_FB10_Pos (10U) 4451 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ 4452 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ 4453 #define CAN_F13R2_FB11_Pos (11U) 4454 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ 4455 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ 4456 #define CAN_F13R2_FB12_Pos (12U) 4457 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ 4458 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ 4459 #define CAN_F13R2_FB13_Pos (13U) 4460 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ 4461 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ 4462 #define CAN_F13R2_FB14_Pos (14U) 4463 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ 4464 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ 4465 #define CAN_F13R2_FB15_Pos (15U) 4466 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ 4467 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ 4468 #define CAN_F13R2_FB16_Pos (16U) 4469 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ 4470 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ 4471 #define CAN_F13R2_FB17_Pos (17U) 4472 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ 4473 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ 4474 #define CAN_F13R2_FB18_Pos (18U) 4475 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ 4476 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ 4477 #define CAN_F13R2_FB19_Pos (19U) 4478 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ 4479 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ 4480 #define CAN_F13R2_FB20_Pos (20U) 4481 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ 4482 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ 4483 #define CAN_F13R2_FB21_Pos (21U) 4484 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ 4485 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ 4486 #define CAN_F13R2_FB22_Pos (22U) 4487 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ 4488 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ 4489 #define CAN_F13R2_FB23_Pos (23U) 4490 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ 4491 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ 4492 #define CAN_F13R2_FB24_Pos (24U) 4493 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ 4494 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ 4495 #define CAN_F13R2_FB25_Pos (25U) 4496 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ 4497 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ 4498 #define CAN_F13R2_FB26_Pos (26U) 4499 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ 4500 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ 4501 #define CAN_F13R2_FB27_Pos (27U) 4502 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ 4503 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ 4504 #define CAN_F13R2_FB28_Pos (28U) 4505 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ 4506 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ 4507 #define CAN_F13R2_FB29_Pos (29U) 4508 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ 4509 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ 4510 #define CAN_F13R2_FB30_Pos (30U) 4511 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ 4512 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ 4513 #define CAN_F13R2_FB31_Pos (31U) 4514 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ 4515 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ 4516 4517 /* CAN filters Legacy aliases */ 4518 #define CAN_FM1R_FBM14_Pos (14U) 4519 #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */ 4520 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */ 4521 #define CAN_FM1R_FBM15_Pos (15U) 4522 #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */ 4523 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */ 4524 #define CAN_FM1R_FBM16_Pos (16U) 4525 #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */ 4526 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */ 4527 #define CAN_FM1R_FBM17_Pos (17U) 4528 #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */ 4529 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */ 4530 #define CAN_FM1R_FBM18_Pos (18U) 4531 #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */ 4532 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */ 4533 #define CAN_FM1R_FBM19_Pos (19U) 4534 #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */ 4535 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */ 4536 #define CAN_FM1R_FBM20_Pos (20U) 4537 #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */ 4538 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */ 4539 #define CAN_FM1R_FBM21_Pos (21U) 4540 #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */ 4541 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */ 4542 #define CAN_FM1R_FBM22_Pos (22U) 4543 #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */ 4544 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */ 4545 #define CAN_FM1R_FBM23_Pos (23U) 4546 #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */ 4547 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */ 4548 #define CAN_FM1R_FBM24_Pos (24U) 4549 #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */ 4550 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */ 4551 #define CAN_FM1R_FBM25_Pos (25U) 4552 #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */ 4553 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */ 4554 #define CAN_FM1R_FBM26_Pos (26U) 4555 #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */ 4556 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */ 4557 #define CAN_FM1R_FBM27_Pos (27U) 4558 #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */ 4559 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */ 4560 4561 #define CAN_FS1R_FSC14_Pos (14U) 4562 #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */ 4563 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */ 4564 #define CAN_FS1R_FSC15_Pos (15U) 4565 #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */ 4566 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */ 4567 #define CAN_FS1R_FSC16_Pos (16U) 4568 #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */ 4569 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */ 4570 #define CAN_FS1R_FSC17_Pos (17U) 4571 #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */ 4572 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */ 4573 #define CAN_FS1R_FSC18_Pos (18U) 4574 #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */ 4575 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */ 4576 #define CAN_FS1R_FSC19_Pos (19U) 4577 #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */ 4578 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */ 4579 #define CAN_FS1R_FSC20_Pos (20U) 4580 #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */ 4581 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */ 4582 #define CAN_FS1R_FSC21_Pos (21U) 4583 #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */ 4584 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */ 4585 #define CAN_FS1R_FSC22_Pos (22U) 4586 #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */ 4587 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */ 4588 #define CAN_FS1R_FSC23_Pos (23U) 4589 #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */ 4590 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */ 4591 #define CAN_FS1R_FSC24_Pos (24U) 4592 #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */ 4593 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */ 4594 #define CAN_FS1R_FSC25_Pos (25U) 4595 #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */ 4596 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */ 4597 #define CAN_FS1R_FSC26_Pos (26U) 4598 #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */ 4599 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */ 4600 #define CAN_FS1R_FSC27_Pos (27U) 4601 #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */ 4602 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */ 4603 4604 #define CAN_FFA1R_FFA14_Pos (14U) 4605 #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */ 4606 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */ 4607 #define CAN_FFA1R_FFA15_Pos (15U) 4608 #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */ 4609 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */ 4610 #define CAN_FFA1R_FFA16_Pos (16U) 4611 #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */ 4612 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */ 4613 #define CAN_FFA1R_FFA17_Pos (17U) 4614 #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */ 4615 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */ 4616 #define CAN_FFA1R_FFA18_Pos (18U) 4617 #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */ 4618 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */ 4619 #define CAN_FFA1R_FFA19_Pos (19U) 4620 #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */ 4621 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */ 4622 #define CAN_FFA1R_FFA20_Pos (20U) 4623 #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */ 4624 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */ 4625 #define CAN_FFA1R_FFA21_Pos (21U) 4626 #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */ 4627 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */ 4628 #define CAN_FFA1R_FFA22_Pos (22U) 4629 #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */ 4630 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */ 4631 #define CAN_FFA1R_FFA23_Pos (23U) 4632 #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */ 4633 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */ 4634 #define CAN_FFA1R_FFA24_Pos (24U) 4635 #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */ 4636 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */ 4637 #define CAN_FFA1R_FFA25_Pos (25U) 4638 #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */ 4639 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */ 4640 #define CAN_FFA1R_FFA26_Pos (26U) 4641 #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */ 4642 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */ 4643 #define CAN_FFA1R_FFA27_Pos (27U) 4644 #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */ 4645 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */ 4646 4647 #define CAN_FA1R_FACT14_Pos (14U) 4648 #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */ 4649 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */ 4650 #define CAN_FA1R_FACT15_Pos (15U) 4651 #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */ 4652 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */ 4653 #define CAN_FA1R_FACT16_Pos (16U) 4654 #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */ 4655 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */ 4656 #define CAN_FA1R_FACT17_Pos (17U) 4657 #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */ 4658 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */ 4659 #define CAN_FA1R_FACT18_Pos (18U) 4660 #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */ 4661 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */ 4662 #define CAN_FA1R_FACT19_Pos (19U) 4663 #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */ 4664 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */ 4665 #define CAN_FA1R_FACT20_Pos (20U) 4666 #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */ 4667 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */ 4668 #define CAN_FA1R_FACT21_Pos (21U) 4669 #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */ 4670 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */ 4671 #define CAN_FA1R_FACT22_Pos (22U) 4672 #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */ 4673 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */ 4674 #define CAN_FA1R_FACT23_Pos (23U) 4675 #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */ 4676 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */ 4677 #define CAN_FA1R_FACT24_Pos (24U) 4678 #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */ 4679 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */ 4680 #define CAN_FA1R_FACT25_Pos (25U) 4681 #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */ 4682 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */ 4683 #define CAN_FA1R_FACT26_Pos (26U) 4684 #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */ 4685 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */ 4686 #define CAN_FA1R_FACT27_Pos (27U) 4687 #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */ 4688 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */ 4689 4690 /******************************************************************************/ 4691 /* */ 4692 /* HDMI-CEC (CEC) */ 4693 /* */ 4694 /******************************************************************************/ 4695 4696 /******************* Bit definition for CEC_CR register *********************/ 4697 #define CEC_CR_CECEN_Pos (0U) 4698 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ 4699 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ 4700 #define CEC_CR_TXSOM_Pos (1U) 4701 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ 4702 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ 4703 #define CEC_CR_TXEOM_Pos (2U) 4704 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ 4705 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ 4706 4707 /******************* Bit definition for CEC_CFGR register *******************/ 4708 #define CEC_CFGR_SFT_Pos (0U) 4709 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ 4710 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ 4711 #define CEC_CFGR_RXTOL_Pos (3U) 4712 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ 4713 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ 4714 #define CEC_CFGR_BRESTP_Pos (4U) 4715 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ 4716 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ 4717 #define CEC_CFGR_BREGEN_Pos (5U) 4718 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ 4719 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ 4720 #define CEC_CFGR_LBPEGEN_Pos (6U) 4721 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ 4722 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ 4723 #define CEC_CFGR_BRDNOGEN_Pos (7U) 4724 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ 4725 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ 4726 #define CEC_CFGR_SFTOPT_Pos (8U) 4727 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ 4728 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ 4729 #define CEC_CFGR_OAR_Pos (16U) 4730 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ 4731 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ 4732 #define CEC_CFGR_LSTN_Pos (31U) 4733 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ 4734 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ 4735 4736 /******************* Bit definition for CEC_TXDR register *******************/ 4737 #define CEC_TXDR_TXD_Pos (0U) 4738 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ 4739 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ 4740 4741 /******************* Bit definition for CEC_RXDR register *******************/ 4742 #define CEC_RXDR_RXD_Pos (0U) 4743 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ 4744 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ 4745 /* Legacy aliases */ 4746 #define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos 4747 #define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk 4748 #define CEC_TXDR_RXD CEC_RXDR_RXD 4749 /******************* Bit definition for CEC_ISR register ********************/ 4750 #define CEC_ISR_RXBR_Pos (0U) 4751 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ 4752 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ 4753 #define CEC_ISR_RXEND_Pos (1U) 4754 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ 4755 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ 4756 #define CEC_ISR_RXOVR_Pos (2U) 4757 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ 4758 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ 4759 #define CEC_ISR_BRE_Pos (3U) 4760 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ 4761 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ 4762 #define CEC_ISR_SBPE_Pos (4U) 4763 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ 4764 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ 4765 #define CEC_ISR_LBPE_Pos (5U) 4766 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ 4767 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ 4768 #define CEC_ISR_RXACKE_Pos (6U) 4769 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ 4770 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ 4771 #define CEC_ISR_ARBLST_Pos (7U) 4772 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ 4773 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ 4774 #define CEC_ISR_TXBR_Pos (8U) 4775 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ 4776 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ 4777 #define CEC_ISR_TXEND_Pos (9U) 4778 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ 4779 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ 4780 #define CEC_ISR_TXUDR_Pos (10U) 4781 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ 4782 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ 4783 #define CEC_ISR_TXERR_Pos (11U) 4784 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ 4785 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ 4786 #define CEC_ISR_TXACKE_Pos (12U) 4787 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ 4788 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ 4789 4790 /******************* Bit definition for CEC_IER register ********************/ 4791 #define CEC_IER_RXBRIE_Pos (0U) 4792 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ 4793 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ 4794 #define CEC_IER_RXENDIE_Pos (1U) 4795 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ 4796 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ 4797 #define CEC_IER_RXOVRIE_Pos (2U) 4798 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ 4799 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ 4800 #define CEC_IER_BREIE_Pos (3U) 4801 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ 4802 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ 4803 #define CEC_IER_SBPEIE_Pos (4U) 4804 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ 4805 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ 4806 #define CEC_IER_LBPEIE_Pos (5U) 4807 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ 4808 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ 4809 #define CEC_IER_RXACKEIE_Pos (6U) 4810 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ 4811 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ 4812 #define CEC_IER_ARBLSTIE_Pos (7U) 4813 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ 4814 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ 4815 #define CEC_IER_TXBRIE_Pos (8U) 4816 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ 4817 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ 4818 #define CEC_IER_TXENDIE_Pos (9U) 4819 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ 4820 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ 4821 #define CEC_IER_TXUDRIE_Pos (10U) 4822 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ 4823 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ 4824 #define CEC_IER_TXERRIE_Pos (11U) 4825 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ 4826 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ 4827 #define CEC_IER_TXACKEIE_Pos (12U) 4828 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ 4829 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ 4830 4831 /******************************************************************************/ 4832 /* */ 4833 /* CRC calculation unit (CRC) */ 4834 /* */ 4835 /******************************************************************************/ 4836 /******************* Bit definition for CRC_DR register *********************/ 4837 #define CRC_DR_DR_Pos (0U) 4838 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 4839 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 4840 4841 /******************* Bit definition for CRC_IDR register ********************/ 4842 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 4843 4844 /******************** Bit definition for CRC_CR register ********************/ 4845 #define CRC_CR_RESET_Pos (0U) 4846 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 4847 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 4848 #define CRC_CR_REV_IN_Pos (5U) 4849 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 4850 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 4851 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 4852 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 4853 #define CRC_CR_REV_OUT_Pos (7U) 4854 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 4855 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 4856 4857 /******************* Bit definition for CRC_INIT register *******************/ 4858 #define CRC_INIT_INIT_Pos (0U) 4859 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 4860 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 4861 4862 /******************************************************************************/ 4863 /* */ 4864 /* CRS Clock Recovery System */ 4865 /******************************************************************************/ 4866 4867 /******************* Bit definition for CRS_CR register *********************/ 4868 #define CRS_CR_SYNCOKIE_Pos (0U) 4869 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ 4870 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */ 4871 #define CRS_CR_SYNCWARNIE_Pos (1U) 4872 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ 4873 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */ 4874 #define CRS_CR_ERRIE_Pos (2U) 4875 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ 4876 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */ 4877 #define CRS_CR_ESYNCIE_Pos (3U) 4878 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ 4879 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/ 4880 #define CRS_CR_CEN_Pos (5U) 4881 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ 4882 #define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */ 4883 #define CRS_CR_AUTOTRIMEN_Pos (6U) 4884 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ 4885 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */ 4886 #define CRS_CR_SWSYNC_Pos (7U) 4887 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ 4888 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */ 4889 #define CRS_CR_TRIM_Pos (8U) 4890 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ 4891 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */ 4892 4893 /******************* Bit definition for CRS_CFGR register *********************/ 4894 #define CRS_CFGR_RELOAD_Pos (0U) 4895 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ 4896 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */ 4897 #define CRS_CFGR_FELIM_Pos (16U) 4898 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ 4899 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */ 4900 4901 #define CRS_CFGR_SYNCDIV_Pos (24U) 4902 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ 4903 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */ 4904 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ 4905 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ 4906 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ 4907 4908 #define CRS_CFGR_SYNCSRC_Pos (28U) 4909 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ 4910 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */ 4911 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ 4912 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ 4913 4914 #define CRS_CFGR_SYNCPOL_Pos (31U) 4915 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ 4916 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */ 4917 4918 /******************* Bit definition for CRS_ISR register *********************/ 4919 #define CRS_ISR_SYNCOKF_Pos (0U) 4920 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ 4921 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */ 4922 #define CRS_ISR_SYNCWARNF_Pos (1U) 4923 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ 4924 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */ 4925 #define CRS_ISR_ERRF_Pos (2U) 4926 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ 4927 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */ 4928 #define CRS_ISR_ESYNCF_Pos (3U) 4929 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ 4930 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */ 4931 #define CRS_ISR_SYNCERR_Pos (8U) 4932 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ 4933 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */ 4934 #define CRS_ISR_SYNCMISS_Pos (9U) 4935 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ 4936 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */ 4937 #define CRS_ISR_TRIMOVF_Pos (10U) 4938 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ 4939 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */ 4940 #define CRS_ISR_FEDIR_Pos (15U) 4941 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ 4942 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */ 4943 #define CRS_ISR_FECAP_Pos (16U) 4944 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ 4945 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */ 4946 4947 /******************* Bit definition for CRS_ICR register *********************/ 4948 #define CRS_ICR_SYNCOKC_Pos (0U) 4949 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ 4950 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */ 4951 #define CRS_ICR_SYNCWARNC_Pos (1U) 4952 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ 4953 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */ 4954 #define CRS_ICR_ERRC_Pos (2U) 4955 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ 4956 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */ 4957 #define CRS_ICR_ESYNCC_Pos (3U) 4958 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ 4959 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */ 4960 4961 /******************************************************************************/ 4962 /* */ 4963 /* Debug MCU (DBGMCU) */ 4964 /* */ 4965 /******************************************************************************/ 4966 4967 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 4968 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 4969 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 4970 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 4971 4972 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 4973 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 4974 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 4975 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 4976 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 4977 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 4978 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 4979 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 4980 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 4981 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 4982 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 4983 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 4984 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 4985 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 4986 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 4987 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 4988 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 4989 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 4990 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 4991 4992 /****************** Bit definition for DBGMCU_CR register *******************/ 4993 #define DBGMCU_CR_DBG_STOP_Pos (1U) 4994 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 4995 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 4996 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 4997 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 4998 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 4999 5000 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 5001 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 5002 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 5003 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 5004 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 5005 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 5006 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 5007 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) 5008 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ 5009 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ 5010 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 5011 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 5012 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 5013 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 5014 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 5015 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 5016 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 5017 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 5018 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 5019 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 5020 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 5021 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 5022 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U) 5023 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */ 5024 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk /*!< CAN debug stopped when Core is halted */ 5025 5026 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 5027 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) 5028 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 5029 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 5030 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) 5031 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 5032 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ 5033 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) 5034 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 5035 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ 5036 5037 /******************************************************************************/ 5038 /* */ 5039 /* DMA Controller (DMA) */ 5040 /* */ 5041 /******************************************************************************/ 5042 /******************* Bit definition for DMA_ISR register ********************/ 5043 #define DMA_ISR_GIF1_Pos (0U) 5044 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 5045 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 5046 #define DMA_ISR_TCIF1_Pos (1U) 5047 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 5048 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 5049 #define DMA_ISR_HTIF1_Pos (2U) 5050 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 5051 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 5052 #define DMA_ISR_TEIF1_Pos (3U) 5053 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 5054 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 5055 #define DMA_ISR_GIF2_Pos (4U) 5056 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 5057 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 5058 #define DMA_ISR_TCIF2_Pos (5U) 5059 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 5060 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 5061 #define DMA_ISR_HTIF2_Pos (6U) 5062 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 5063 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 5064 #define DMA_ISR_TEIF2_Pos (7U) 5065 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 5066 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 5067 #define DMA_ISR_GIF3_Pos (8U) 5068 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 5069 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 5070 #define DMA_ISR_TCIF3_Pos (9U) 5071 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 5072 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 5073 #define DMA_ISR_HTIF3_Pos (10U) 5074 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 5075 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 5076 #define DMA_ISR_TEIF3_Pos (11U) 5077 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 5078 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 5079 #define DMA_ISR_GIF4_Pos (12U) 5080 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 5081 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 5082 #define DMA_ISR_TCIF4_Pos (13U) 5083 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 5084 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 5085 #define DMA_ISR_HTIF4_Pos (14U) 5086 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 5087 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 5088 #define DMA_ISR_TEIF4_Pos (15U) 5089 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 5090 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 5091 #define DMA_ISR_GIF5_Pos (16U) 5092 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 5093 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 5094 #define DMA_ISR_TCIF5_Pos (17U) 5095 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 5096 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 5097 #define DMA_ISR_HTIF5_Pos (18U) 5098 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 5099 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 5100 #define DMA_ISR_TEIF5_Pos (19U) 5101 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 5102 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 5103 #define DMA_ISR_GIF6_Pos (20U) 5104 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 5105 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 5106 #define DMA_ISR_TCIF6_Pos (21U) 5107 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 5108 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 5109 #define DMA_ISR_HTIF6_Pos (22U) 5110 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 5111 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 5112 #define DMA_ISR_TEIF6_Pos (23U) 5113 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 5114 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 5115 #define DMA_ISR_GIF7_Pos (24U) 5116 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 5117 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 5118 #define DMA_ISR_TCIF7_Pos (25U) 5119 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 5120 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 5121 #define DMA_ISR_HTIF7_Pos (26U) 5122 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 5123 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 5124 #define DMA_ISR_TEIF7_Pos (27U) 5125 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 5126 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 5127 5128 /******************* Bit definition for DMA_IFCR register *******************/ 5129 #define DMA_IFCR_CGIF1_Pos (0U) 5130 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 5131 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 5132 #define DMA_IFCR_CTCIF1_Pos (1U) 5133 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 5134 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 5135 #define DMA_IFCR_CHTIF1_Pos (2U) 5136 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 5137 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 5138 #define DMA_IFCR_CTEIF1_Pos (3U) 5139 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 5140 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 5141 #define DMA_IFCR_CGIF2_Pos (4U) 5142 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 5143 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 5144 #define DMA_IFCR_CTCIF2_Pos (5U) 5145 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 5146 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 5147 #define DMA_IFCR_CHTIF2_Pos (6U) 5148 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 5149 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 5150 #define DMA_IFCR_CTEIF2_Pos (7U) 5151 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 5152 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 5153 #define DMA_IFCR_CGIF3_Pos (8U) 5154 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 5155 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 5156 #define DMA_IFCR_CTCIF3_Pos (9U) 5157 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 5158 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 5159 #define DMA_IFCR_CHTIF3_Pos (10U) 5160 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 5161 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 5162 #define DMA_IFCR_CTEIF3_Pos (11U) 5163 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 5164 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 5165 #define DMA_IFCR_CGIF4_Pos (12U) 5166 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 5167 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 5168 #define DMA_IFCR_CTCIF4_Pos (13U) 5169 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 5170 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 5171 #define DMA_IFCR_CHTIF4_Pos (14U) 5172 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 5173 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 5174 #define DMA_IFCR_CTEIF4_Pos (15U) 5175 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 5176 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 5177 #define DMA_IFCR_CGIF5_Pos (16U) 5178 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 5179 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 5180 #define DMA_IFCR_CTCIF5_Pos (17U) 5181 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 5182 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 5183 #define DMA_IFCR_CHTIF5_Pos (18U) 5184 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 5185 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 5186 #define DMA_IFCR_CTEIF5_Pos (19U) 5187 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 5188 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 5189 #define DMA_IFCR_CGIF6_Pos (20U) 5190 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 5191 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 5192 #define DMA_IFCR_CTCIF6_Pos (21U) 5193 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 5194 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 5195 #define DMA_IFCR_CHTIF6_Pos (22U) 5196 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 5197 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 5198 #define DMA_IFCR_CTEIF6_Pos (23U) 5199 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 5200 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 5201 #define DMA_IFCR_CGIF7_Pos (24U) 5202 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 5203 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 5204 #define DMA_IFCR_CTCIF7_Pos (25U) 5205 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 5206 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 5207 #define DMA_IFCR_CHTIF7_Pos (26U) 5208 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 5209 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 5210 #define DMA_IFCR_CTEIF7_Pos (27U) 5211 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 5212 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 5213 5214 /******************* Bit definition for DMA_CCR register ********************/ 5215 #define DMA_CCR_EN_Pos (0U) 5216 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 5217 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 5218 #define DMA_CCR_TCIE_Pos (1U) 5219 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 5220 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 5221 #define DMA_CCR_HTIE_Pos (2U) 5222 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 5223 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 5224 #define DMA_CCR_TEIE_Pos (3U) 5225 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 5226 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 5227 #define DMA_CCR_DIR_Pos (4U) 5228 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 5229 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 5230 #define DMA_CCR_CIRC_Pos (5U) 5231 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 5232 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 5233 #define DMA_CCR_PINC_Pos (6U) 5234 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 5235 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 5236 #define DMA_CCR_MINC_Pos (7U) 5237 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 5238 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 5239 5240 #define DMA_CCR_PSIZE_Pos (8U) 5241 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 5242 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 5243 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 5244 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 5245 5246 #define DMA_CCR_MSIZE_Pos (10U) 5247 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 5248 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 5249 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 5250 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 5251 5252 #define DMA_CCR_PL_Pos (12U) 5253 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 5254 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 5255 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 5256 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 5257 5258 #define DMA_CCR_MEM2MEM_Pos (14U) 5259 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 5260 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 5261 5262 /****************** Bit definition for DMA_CNDTR register *******************/ 5263 #define DMA_CNDTR_NDT_Pos (0U) 5264 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 5265 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 5266 5267 /****************** Bit definition for DMA_CPAR register ********************/ 5268 #define DMA_CPAR_PA_Pos (0U) 5269 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 5270 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 5271 5272 /****************** Bit definition for DMA_CMAR register ********************/ 5273 #define DMA_CMAR_MA_Pos (0U) 5274 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 5275 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 5276 5277 /******************************************************************************/ 5278 /* */ 5279 /* External Interrupt/Event Controller (EXTI) */ 5280 /* */ 5281 /******************************************************************************/ 5282 /******************* Bit definition for EXTI_IMR register *******************/ 5283 #define EXTI_IMR_MR0_Pos (0U) 5284 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 5285 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 5286 #define EXTI_IMR_MR1_Pos (1U) 5287 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 5288 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 5289 #define EXTI_IMR_MR2_Pos (2U) 5290 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 5291 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 5292 #define EXTI_IMR_MR3_Pos (3U) 5293 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 5294 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 5295 #define EXTI_IMR_MR4_Pos (4U) 5296 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 5297 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 5298 #define EXTI_IMR_MR5_Pos (5U) 5299 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 5300 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 5301 #define EXTI_IMR_MR6_Pos (6U) 5302 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 5303 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 5304 #define EXTI_IMR_MR7_Pos (7U) 5305 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 5306 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 5307 #define EXTI_IMR_MR8_Pos (8U) 5308 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 5309 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 5310 #define EXTI_IMR_MR9_Pos (9U) 5311 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 5312 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 5313 #define EXTI_IMR_MR10_Pos (10U) 5314 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 5315 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 5316 #define EXTI_IMR_MR11_Pos (11U) 5317 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 5318 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 5319 #define EXTI_IMR_MR12_Pos (12U) 5320 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 5321 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 5322 #define EXTI_IMR_MR13_Pos (13U) 5323 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 5324 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 5325 #define EXTI_IMR_MR14_Pos (14U) 5326 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 5327 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 5328 #define EXTI_IMR_MR15_Pos (15U) 5329 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 5330 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 5331 #define EXTI_IMR_MR16_Pos (16U) 5332 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 5333 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 5334 #define EXTI_IMR_MR17_Pos (17U) 5335 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 5336 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 5337 #define EXTI_IMR_MR18_Pos (18U) 5338 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 5339 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 5340 #define EXTI_IMR_MR19_Pos (19U) 5341 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 5342 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 5343 #define EXTI_IMR_MR21_Pos (21U) 5344 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 5345 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 5346 #define EXTI_IMR_MR22_Pos (22U) 5347 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 5348 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 5349 #define EXTI_IMR_MR23_Pos (23U) 5350 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 5351 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 5352 #define EXTI_IMR_MR25_Pos (25U) 5353 #define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ 5354 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ 5355 #define EXTI_IMR_MR27_Pos (27U) 5356 #define EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ 5357 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ 5358 #define EXTI_IMR_MR31_Pos (31U) 5359 #define EXTI_IMR_MR31_Msk (0x1UL << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */ 5360 #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */ 5361 5362 /* References Defines */ 5363 #define EXTI_IMR_IM0 EXTI_IMR_MR0 5364 #define EXTI_IMR_IM1 EXTI_IMR_MR1 5365 #define EXTI_IMR_IM2 EXTI_IMR_MR2 5366 #define EXTI_IMR_IM3 EXTI_IMR_MR3 5367 #define EXTI_IMR_IM4 EXTI_IMR_MR4 5368 #define EXTI_IMR_IM5 EXTI_IMR_MR5 5369 #define EXTI_IMR_IM6 EXTI_IMR_MR6 5370 #define EXTI_IMR_IM7 EXTI_IMR_MR7 5371 #define EXTI_IMR_IM8 EXTI_IMR_MR8 5372 #define EXTI_IMR_IM9 EXTI_IMR_MR9 5373 #define EXTI_IMR_IM10 EXTI_IMR_MR10 5374 #define EXTI_IMR_IM11 EXTI_IMR_MR11 5375 #define EXTI_IMR_IM12 EXTI_IMR_MR12 5376 #define EXTI_IMR_IM13 EXTI_IMR_MR13 5377 #define EXTI_IMR_IM14 EXTI_IMR_MR14 5378 #define EXTI_IMR_IM15 EXTI_IMR_MR15 5379 #define EXTI_IMR_IM16 EXTI_IMR_MR16 5380 #define EXTI_IMR_IM17 EXTI_IMR_MR17 5381 #define EXTI_IMR_IM18 EXTI_IMR_MR18 5382 #define EXTI_IMR_IM19 EXTI_IMR_MR19 5383 #define EXTI_IMR_IM21 EXTI_IMR_MR21 5384 #define EXTI_IMR_IM22 EXTI_IMR_MR22 5385 #define EXTI_IMR_IM23 EXTI_IMR_MR23 5386 #define EXTI_IMR_IM25 EXTI_IMR_MR25 5387 #define EXTI_IMR_IM27 EXTI_IMR_MR27 5388 #define EXTI_IMR_IM31 EXTI_IMR_MR31 5389 5390 #define EXTI_IMR_IM_Pos (0U) 5391 #define EXTI_IMR_IM_Msk (0x8AEFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x8AEFFFFF */ 5392 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 5393 5394 5395 /****************** Bit definition for EXTI_EMR register ********************/ 5396 #define EXTI_EMR_MR0_Pos (0U) 5397 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 5398 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 5399 #define EXTI_EMR_MR1_Pos (1U) 5400 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 5401 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 5402 #define EXTI_EMR_MR2_Pos (2U) 5403 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 5404 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 5405 #define EXTI_EMR_MR3_Pos (3U) 5406 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 5407 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 5408 #define EXTI_EMR_MR4_Pos (4U) 5409 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 5410 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 5411 #define EXTI_EMR_MR5_Pos (5U) 5412 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 5413 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 5414 #define EXTI_EMR_MR6_Pos (6U) 5415 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 5416 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 5417 #define EXTI_EMR_MR7_Pos (7U) 5418 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 5419 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 5420 #define EXTI_EMR_MR8_Pos (8U) 5421 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 5422 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 5423 #define EXTI_EMR_MR9_Pos (9U) 5424 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 5425 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 5426 #define EXTI_EMR_MR10_Pos (10U) 5427 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 5428 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 5429 #define EXTI_EMR_MR11_Pos (11U) 5430 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 5431 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 5432 #define EXTI_EMR_MR12_Pos (12U) 5433 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 5434 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 5435 #define EXTI_EMR_MR13_Pos (13U) 5436 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 5437 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 5438 #define EXTI_EMR_MR14_Pos (14U) 5439 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 5440 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 5441 #define EXTI_EMR_MR15_Pos (15U) 5442 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 5443 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 5444 #define EXTI_EMR_MR16_Pos (16U) 5445 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 5446 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 5447 #define EXTI_EMR_MR17_Pos (17U) 5448 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 5449 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 5450 #define EXTI_EMR_MR18_Pos (18U) 5451 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 5452 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 5453 #define EXTI_EMR_MR19_Pos (19U) 5454 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 5455 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 5456 #define EXTI_EMR_MR21_Pos (21U) 5457 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 5458 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 5459 #define EXTI_EMR_MR22_Pos (22U) 5460 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 5461 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 5462 #define EXTI_EMR_MR23_Pos (23U) 5463 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 5464 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 5465 #define EXTI_EMR_MR25_Pos (25U) 5466 #define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ 5467 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ 5468 #define EXTI_EMR_MR27_Pos (27U) 5469 #define EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ 5470 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ 5471 #define EXTI_EMR_MR31_Pos (31U) 5472 #define EXTI_EMR_MR31_Msk (0x1UL << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */ 5473 #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */ 5474 5475 /* References Defines */ 5476 #define EXTI_EMR_EM0 EXTI_EMR_MR0 5477 #define EXTI_EMR_EM1 EXTI_EMR_MR1 5478 #define EXTI_EMR_EM2 EXTI_EMR_MR2 5479 #define EXTI_EMR_EM3 EXTI_EMR_MR3 5480 #define EXTI_EMR_EM4 EXTI_EMR_MR4 5481 #define EXTI_EMR_EM5 EXTI_EMR_MR5 5482 #define EXTI_EMR_EM6 EXTI_EMR_MR6 5483 #define EXTI_EMR_EM7 EXTI_EMR_MR7 5484 #define EXTI_EMR_EM8 EXTI_EMR_MR8 5485 #define EXTI_EMR_EM9 EXTI_EMR_MR9 5486 #define EXTI_EMR_EM10 EXTI_EMR_MR10 5487 #define EXTI_EMR_EM11 EXTI_EMR_MR11 5488 #define EXTI_EMR_EM12 EXTI_EMR_MR12 5489 #define EXTI_EMR_EM13 EXTI_EMR_MR13 5490 #define EXTI_EMR_EM14 EXTI_EMR_MR14 5491 #define EXTI_EMR_EM15 EXTI_EMR_MR15 5492 #define EXTI_EMR_EM16 EXTI_EMR_MR16 5493 #define EXTI_EMR_EM17 EXTI_EMR_MR17 5494 #define EXTI_EMR_EM18 EXTI_EMR_MR18 5495 #define EXTI_EMR_EM19 EXTI_EMR_MR19 5496 #define EXTI_EMR_EM21 EXTI_EMR_MR21 5497 #define EXTI_EMR_EM22 EXTI_EMR_MR22 5498 #define EXTI_EMR_EM23 EXTI_EMR_MR23 5499 #define EXTI_EMR_EM25 EXTI_EMR_MR25 5500 #define EXTI_EMR_EM27 EXTI_EMR_MR27 5501 #define EXTI_EMR_EM31 EXTI_EMR_MR31 5502 5503 /******************* Bit definition for EXTI_RTSR register ******************/ 5504 #define EXTI_RTSR_TR0_Pos (0U) 5505 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 5506 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 5507 #define EXTI_RTSR_TR1_Pos (1U) 5508 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 5509 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 5510 #define EXTI_RTSR_TR2_Pos (2U) 5511 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 5512 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 5513 #define EXTI_RTSR_TR3_Pos (3U) 5514 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 5515 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 5516 #define EXTI_RTSR_TR4_Pos (4U) 5517 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 5518 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 5519 #define EXTI_RTSR_TR5_Pos (5U) 5520 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 5521 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 5522 #define EXTI_RTSR_TR6_Pos (6U) 5523 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 5524 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 5525 #define EXTI_RTSR_TR7_Pos (7U) 5526 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 5527 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 5528 #define EXTI_RTSR_TR8_Pos (8U) 5529 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 5530 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 5531 #define EXTI_RTSR_TR9_Pos (9U) 5532 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 5533 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 5534 #define EXTI_RTSR_TR10_Pos (10U) 5535 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 5536 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 5537 #define EXTI_RTSR_TR11_Pos (11U) 5538 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 5539 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 5540 #define EXTI_RTSR_TR12_Pos (12U) 5541 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 5542 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 5543 #define EXTI_RTSR_TR13_Pos (13U) 5544 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 5545 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 5546 #define EXTI_RTSR_TR14_Pos (14U) 5547 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 5548 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 5549 #define EXTI_RTSR_TR15_Pos (15U) 5550 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 5551 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 5552 #define EXTI_RTSR_TR16_Pos (16U) 5553 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 5554 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 5555 #define EXTI_RTSR_TR17_Pos (17U) 5556 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 5557 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 5558 #define EXTI_RTSR_TR19_Pos (19U) 5559 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 5560 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 5561 #define EXTI_RTSR_TR21_Pos (21U) 5562 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 5563 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 5564 #define EXTI_RTSR_TR22_Pos (22U) 5565 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 5566 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 5567 #define EXTI_RTSR_TR31_Pos (31U) 5568 #define EXTI_RTSR_TR31_Msk (0x1UL << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */ 5569 #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */ 5570 5571 /* References Defines */ 5572 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 5573 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 5574 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 5575 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 5576 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 5577 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 5578 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 5579 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 5580 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 5581 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 5582 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 5583 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 5584 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 5585 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 5586 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 5587 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 5588 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 5589 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 5590 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 5591 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 5592 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 5593 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31 5594 5595 /******************* Bit definition for EXTI_FTSR register *******************/ 5596 #define EXTI_FTSR_TR0_Pos (0U) 5597 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 5598 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 5599 #define EXTI_FTSR_TR1_Pos (1U) 5600 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 5601 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 5602 #define EXTI_FTSR_TR2_Pos (2U) 5603 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 5604 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 5605 #define EXTI_FTSR_TR3_Pos (3U) 5606 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 5607 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 5608 #define EXTI_FTSR_TR4_Pos (4U) 5609 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 5610 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 5611 #define EXTI_FTSR_TR5_Pos (5U) 5612 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 5613 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 5614 #define EXTI_FTSR_TR6_Pos (6U) 5615 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 5616 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 5617 #define EXTI_FTSR_TR7_Pos (7U) 5618 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 5619 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 5620 #define EXTI_FTSR_TR8_Pos (8U) 5621 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 5622 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 5623 #define EXTI_FTSR_TR9_Pos (9U) 5624 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 5625 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 5626 #define EXTI_FTSR_TR10_Pos (10U) 5627 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 5628 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 5629 #define EXTI_FTSR_TR11_Pos (11U) 5630 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 5631 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 5632 #define EXTI_FTSR_TR12_Pos (12U) 5633 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 5634 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 5635 #define EXTI_FTSR_TR13_Pos (13U) 5636 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 5637 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 5638 #define EXTI_FTSR_TR14_Pos (14U) 5639 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 5640 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 5641 #define EXTI_FTSR_TR15_Pos (15U) 5642 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 5643 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 5644 #define EXTI_FTSR_TR16_Pos (16U) 5645 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 5646 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 5647 #define EXTI_FTSR_TR17_Pos (17U) 5648 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 5649 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 5650 #define EXTI_FTSR_TR19_Pos (19U) 5651 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 5652 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 5653 #define EXTI_FTSR_TR21_Pos (21U) 5654 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 5655 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 5656 #define EXTI_FTSR_TR22_Pos (22U) 5657 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 5658 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 5659 #define EXTI_FTSR_TR31_Pos (31U) 5660 #define EXTI_FTSR_TR31_Msk (0x1UL << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */ 5661 #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */ 5662 5663 /* References Defines */ 5664 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 5665 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 5666 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 5667 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 5668 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 5669 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 5670 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 5671 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 5672 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 5673 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 5674 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 5675 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 5676 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 5677 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 5678 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 5679 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 5680 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 5681 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 5682 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 5683 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 5684 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 5685 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31 5686 5687 /******************* Bit definition for EXTI_SWIER register *******************/ 5688 #define EXTI_SWIER_SWIER0_Pos (0U) 5689 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 5690 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 5691 #define EXTI_SWIER_SWIER1_Pos (1U) 5692 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 5693 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 5694 #define EXTI_SWIER_SWIER2_Pos (2U) 5695 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 5696 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 5697 #define EXTI_SWIER_SWIER3_Pos (3U) 5698 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 5699 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 5700 #define EXTI_SWIER_SWIER4_Pos (4U) 5701 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 5702 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 5703 #define EXTI_SWIER_SWIER5_Pos (5U) 5704 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 5705 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 5706 #define EXTI_SWIER_SWIER6_Pos (6U) 5707 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 5708 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 5709 #define EXTI_SWIER_SWIER7_Pos (7U) 5710 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 5711 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 5712 #define EXTI_SWIER_SWIER8_Pos (8U) 5713 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 5714 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 5715 #define EXTI_SWIER_SWIER9_Pos (9U) 5716 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 5717 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 5718 #define EXTI_SWIER_SWIER10_Pos (10U) 5719 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 5720 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 5721 #define EXTI_SWIER_SWIER11_Pos (11U) 5722 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 5723 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 5724 #define EXTI_SWIER_SWIER12_Pos (12U) 5725 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 5726 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 5727 #define EXTI_SWIER_SWIER13_Pos (13U) 5728 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 5729 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 5730 #define EXTI_SWIER_SWIER14_Pos (14U) 5731 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 5732 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 5733 #define EXTI_SWIER_SWIER15_Pos (15U) 5734 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 5735 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 5736 #define EXTI_SWIER_SWIER16_Pos (16U) 5737 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 5738 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 5739 #define EXTI_SWIER_SWIER17_Pos (17U) 5740 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 5741 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 5742 #define EXTI_SWIER_SWIER19_Pos (19U) 5743 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 5744 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 5745 #define EXTI_SWIER_SWIER21_Pos (21U) 5746 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 5747 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 5748 #define EXTI_SWIER_SWIER22_Pos (22U) 5749 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 5750 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 5751 #define EXTI_SWIER_SWIER31_Pos (31U) 5752 #define EXTI_SWIER_SWIER31_Msk (0x1UL << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */ 5753 #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */ 5754 5755 /* References Defines */ 5756 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 5757 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 5758 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 5759 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 5760 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 5761 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 5762 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 5763 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 5764 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 5765 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 5766 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 5767 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 5768 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 5769 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 5770 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 5771 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 5772 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 5773 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 5774 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 5775 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 5776 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 5777 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 5778 5779 /****************** Bit definition for EXTI_PR register *********************/ 5780 #define EXTI_PR_PR0_Pos (0U) 5781 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 5782 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ 5783 #define EXTI_PR_PR1_Pos (1U) 5784 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 5785 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ 5786 #define EXTI_PR_PR2_Pos (2U) 5787 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 5788 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ 5789 #define EXTI_PR_PR3_Pos (3U) 5790 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 5791 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ 5792 #define EXTI_PR_PR4_Pos (4U) 5793 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 5794 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ 5795 #define EXTI_PR_PR5_Pos (5U) 5796 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 5797 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ 5798 #define EXTI_PR_PR6_Pos (6U) 5799 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 5800 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ 5801 #define EXTI_PR_PR7_Pos (7U) 5802 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 5803 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ 5804 #define EXTI_PR_PR8_Pos (8U) 5805 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 5806 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ 5807 #define EXTI_PR_PR9_Pos (9U) 5808 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 5809 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ 5810 #define EXTI_PR_PR10_Pos (10U) 5811 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 5812 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ 5813 #define EXTI_PR_PR11_Pos (11U) 5814 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 5815 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ 5816 #define EXTI_PR_PR12_Pos (12U) 5817 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 5818 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ 5819 #define EXTI_PR_PR13_Pos (13U) 5820 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 5821 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ 5822 #define EXTI_PR_PR14_Pos (14U) 5823 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 5824 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ 5825 #define EXTI_PR_PR15_Pos (15U) 5826 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 5827 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ 5828 #define EXTI_PR_PR16_Pos (16U) 5829 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 5830 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ 5831 #define EXTI_PR_PR17_Pos (17U) 5832 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 5833 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ 5834 #define EXTI_PR_PR19_Pos (19U) 5835 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 5836 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ 5837 #define EXTI_PR_PR21_Pos (21U) 5838 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 5839 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */ 5840 #define EXTI_PR_PR22_Pos (22U) 5841 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 5842 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */ 5843 #define EXTI_PR_PR31_Pos (31U) 5844 #define EXTI_PR_PR31_Msk (0x1UL << EXTI_PR_PR31_Pos) /*!< 0x80000000 */ 5845 #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit 31 */ 5846 5847 /* References Defines */ 5848 #define EXTI_PR_PIF0 EXTI_PR_PR0 5849 #define EXTI_PR_PIF1 EXTI_PR_PR1 5850 #define EXTI_PR_PIF2 EXTI_PR_PR2 5851 #define EXTI_PR_PIF3 EXTI_PR_PR3 5852 #define EXTI_PR_PIF4 EXTI_PR_PR4 5853 #define EXTI_PR_PIF5 EXTI_PR_PR5 5854 #define EXTI_PR_PIF6 EXTI_PR_PR6 5855 #define EXTI_PR_PIF7 EXTI_PR_PR7 5856 #define EXTI_PR_PIF8 EXTI_PR_PR8 5857 #define EXTI_PR_PIF9 EXTI_PR_PR9 5858 #define EXTI_PR_PIF10 EXTI_PR_PR10 5859 #define EXTI_PR_PIF11 EXTI_PR_PR11 5860 #define EXTI_PR_PIF12 EXTI_PR_PR12 5861 #define EXTI_PR_PIF13 EXTI_PR_PR13 5862 #define EXTI_PR_PIF14 EXTI_PR_PR14 5863 #define EXTI_PR_PIF15 EXTI_PR_PR15 5864 #define EXTI_PR_PIF16 EXTI_PR_PR16 5865 #define EXTI_PR_PIF17 EXTI_PR_PR17 5866 #define EXTI_PR_PIF19 EXTI_PR_PR19 5867 #define EXTI_PR_PIF21 EXTI_PR_PR21 5868 #define EXTI_PR_PIF22 EXTI_PR_PR22 5869 #define EXTI_PR_PIF31 EXTI_PR_PR31 5870 5871 /******************************************************************************/ 5872 /* */ 5873 /* FLASH and Option Bytes Registers */ 5874 /* */ 5875 /******************************************************************************/ 5876 5877 /******************* Bit definition for FLASH_ACR register ******************/ 5878 #define FLASH_ACR_LATENCY_Pos (0U) 5879 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 5880 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 5881 5882 #define FLASH_ACR_PRFTBE_Pos (4U) 5883 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 5884 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 5885 #define FLASH_ACR_PRFTBS_Pos (5U) 5886 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 5887 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 5888 5889 /****************** Bit definition for FLASH_KEYR register ******************/ 5890 #define FLASH_KEYR_FKEYR_Pos (0U) 5891 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 5892 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 5893 5894 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 5895 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 5896 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 5897 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 5898 5899 /****************** FLASH Keys **********************************************/ 5900 #define FLASH_KEY1_Pos (0U) 5901 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 5902 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ 5903 #define FLASH_KEY2_Pos (0U) 5904 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 5905 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 5906 to unlock the write access to the FPEC. */ 5907 5908 #define FLASH_OPTKEY1_Pos (0U) 5909 #define FLASH_OPTKEY1_Msk (0x45670123UL << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ 5910 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ 5911 #define FLASH_OPTKEY2_Pos (0U) 5912 #define FLASH_OPTKEY2_Msk (0xCDEF89ABUL << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ 5913 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to 5914 unlock the write access to the option byte block */ 5915 5916 /****************** Bit definition for FLASH_SR register *******************/ 5917 #define FLASH_SR_BSY_Pos (0U) 5918 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 5919 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 5920 #define FLASH_SR_PGERR_Pos (2U) 5921 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 5922 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 5923 #define FLASH_SR_WRPRTERR_Pos (4U) 5924 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 5925 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 5926 #define FLASH_SR_EOP_Pos (5U) 5927 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 5928 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 5929 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ 5930 5931 /******************* Bit definition for FLASH_CR register *******************/ 5932 #define FLASH_CR_PG_Pos (0U) 5933 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 5934 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 5935 #define FLASH_CR_PER_Pos (1U) 5936 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 5937 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 5938 #define FLASH_CR_MER_Pos (2U) 5939 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 5940 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 5941 #define FLASH_CR_OPTPG_Pos (4U) 5942 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 5943 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 5944 #define FLASH_CR_OPTER_Pos (5U) 5945 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 5946 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 5947 #define FLASH_CR_STRT_Pos (6U) 5948 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 5949 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 5950 #define FLASH_CR_LOCK_Pos (7U) 5951 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 5952 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 5953 #define FLASH_CR_OPTWRE_Pos (9U) 5954 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 5955 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 5956 #define FLASH_CR_ERRIE_Pos (10U) 5957 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 5958 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 5959 #define FLASH_CR_EOPIE_Pos (12U) 5960 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 5961 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 5962 #define FLASH_CR_OBL_LAUNCH_Pos (13U) 5963 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ 5964 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ 5965 5966 /******************* Bit definition for FLASH_AR register *******************/ 5967 #define FLASH_AR_FAR_Pos (0U) 5968 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 5969 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 5970 5971 /****************** Bit definition for FLASH_OBR register *******************/ 5972 #define FLASH_OBR_OPTERR_Pos (0U) 5973 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 5974 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 5975 #define FLASH_OBR_RDPRT1_Pos (1U) 5976 #define FLASH_OBR_RDPRT1_Msk (0x1UL << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ 5977 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ 5978 #define FLASH_OBR_RDPRT2_Pos (2U) 5979 #define FLASH_OBR_RDPRT2_Msk (0x1UL << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ 5980 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ 5981 5982 #define FLASH_OBR_USER_Pos (8U) 5983 #define FLASH_OBR_USER_Msk (0xFFUL << FLASH_OBR_USER_Pos) /*!< 0x0000FF00 */ 5984 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 5985 #define FLASH_OBR_IWDG_SW_Pos (8U) 5986 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ 5987 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 5988 #define FLASH_OBR_nRST_STOP_Pos (9U) 5989 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ 5990 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 5991 #define FLASH_OBR_nRST_STDBY_Pos (10U) 5992 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ 5993 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 5994 #define FLASH_OBR_nBOOT0_Pos (11U) 5995 #define FLASH_OBR_nBOOT0_Msk (0x1UL << FLASH_OBR_nBOOT0_Pos) /*!< 0x00000800 */ 5996 #define FLASH_OBR_nBOOT0 FLASH_OBR_nBOOT0_Msk /*!< nBOOT0 */ 5997 #define FLASH_OBR_nBOOT1_Pos (12U) 5998 #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ 5999 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ 6000 #define FLASH_OBR_VDDA_MONITOR_Pos (13U) 6001 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ 6002 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ 6003 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) 6004 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ 6005 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ 6006 #define FLASH_OBR_BOOT_SEL_Pos (15U) 6007 #define FLASH_OBR_BOOT_SEL_Msk (0x1UL << FLASH_OBR_BOOT_SEL_Pos) /*!< 0x00008000 */ 6008 #define FLASH_OBR_BOOT_SEL FLASH_OBR_BOOT_SEL_Msk /*!< BOOT selection */ 6009 #define FLASH_OBR_DATA0_Pos (16U) 6010 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ 6011 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 6012 #define FLASH_OBR_DATA1_Pos (24U) 6013 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ 6014 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 6015 6016 /* Old BOOT1 bit definition, maintained for legacy purpose */ 6017 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 6018 6019 /* Old OBR_VDDA bit definition, maintained for legacy purpose */ 6020 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR 6021 6022 /****************** Bit definition for FLASH_WRPR register ******************/ 6023 #define FLASH_WRPR_WRP_Pos (0U) 6024 #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 6025 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 6026 6027 /*----------------------------------------------------------------------------*/ 6028 6029 /****************** Bit definition for OB_RDP register **********************/ 6030 #define OB_RDP_RDP_Pos (0U) 6031 #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ 6032 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ 6033 #define OB_RDP_nRDP_Pos (8U) 6034 #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 6035 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 6036 6037 /****************** Bit definition for OB_USER register *********************/ 6038 #define OB_USER_USER_Pos (16U) 6039 #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ 6040 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ 6041 #define OB_USER_nUSER_Pos (24U) 6042 #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ 6043 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ 6044 6045 /****************** Bit definition for OB_WRP0 register *********************/ 6046 #define OB_WRP0_WRP0_Pos (0U) 6047 #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ 6048 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 6049 #define OB_WRP0_nWRP0_Pos (8U) 6050 #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 6051 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 6052 6053 /******************************************************************************/ 6054 /* */ 6055 /* General Purpose IOs (GPIO) */ 6056 /* */ 6057 /******************************************************************************/ 6058 /******************* Bit definition for GPIO_MODER register *****************/ 6059 #define GPIO_MODER_MODER0_Pos (0U) 6060 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 6061 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 6062 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 6063 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 6064 #define GPIO_MODER_MODER1_Pos (2U) 6065 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 6066 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 6067 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 6068 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 6069 #define GPIO_MODER_MODER2_Pos (4U) 6070 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 6071 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 6072 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 6073 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 6074 #define GPIO_MODER_MODER3_Pos (6U) 6075 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 6076 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 6077 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 6078 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 6079 #define GPIO_MODER_MODER4_Pos (8U) 6080 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 6081 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 6082 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 6083 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 6084 #define GPIO_MODER_MODER5_Pos (10U) 6085 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 6086 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 6087 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 6088 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 6089 #define GPIO_MODER_MODER6_Pos (12U) 6090 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 6091 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 6092 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 6093 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 6094 #define GPIO_MODER_MODER7_Pos (14U) 6095 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 6096 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 6097 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 6098 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 6099 #define GPIO_MODER_MODER8_Pos (16U) 6100 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 6101 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 6102 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 6103 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 6104 #define GPIO_MODER_MODER9_Pos (18U) 6105 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 6106 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 6107 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 6108 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 6109 #define GPIO_MODER_MODER10_Pos (20U) 6110 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 6111 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 6112 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 6113 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 6114 #define GPIO_MODER_MODER11_Pos (22U) 6115 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 6116 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 6117 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 6118 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 6119 #define GPIO_MODER_MODER12_Pos (24U) 6120 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 6121 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 6122 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 6123 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 6124 #define GPIO_MODER_MODER13_Pos (26U) 6125 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 6126 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 6127 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 6128 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 6129 #define GPIO_MODER_MODER14_Pos (28U) 6130 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 6131 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 6132 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 6133 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 6134 #define GPIO_MODER_MODER15_Pos (30U) 6135 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 6136 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 6137 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 6138 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 6139 6140 /****************** Bit definition for GPIO_OTYPER register *****************/ 6141 #define GPIO_OTYPER_OT_0 (0x00000001U) 6142 #define GPIO_OTYPER_OT_1 (0x00000002U) 6143 #define GPIO_OTYPER_OT_2 (0x00000004U) 6144 #define GPIO_OTYPER_OT_3 (0x00000008U) 6145 #define GPIO_OTYPER_OT_4 (0x00000010U) 6146 #define GPIO_OTYPER_OT_5 (0x00000020U) 6147 #define GPIO_OTYPER_OT_6 (0x00000040U) 6148 #define GPIO_OTYPER_OT_7 (0x00000080U) 6149 #define GPIO_OTYPER_OT_8 (0x00000100U) 6150 #define GPIO_OTYPER_OT_9 (0x00000200U) 6151 #define GPIO_OTYPER_OT_10 (0x00000400U) 6152 #define GPIO_OTYPER_OT_11 (0x00000800U) 6153 #define GPIO_OTYPER_OT_12 (0x00001000U) 6154 #define GPIO_OTYPER_OT_13 (0x00002000U) 6155 #define GPIO_OTYPER_OT_14 (0x00004000U) 6156 #define GPIO_OTYPER_OT_15 (0x00008000U) 6157 6158 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 6159 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) 6160 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ 6161 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk 6162 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ 6163 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ 6164 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) 6165 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ 6166 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk 6167 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ 6168 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ 6169 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) 6170 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ 6171 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk 6172 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ 6173 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ 6174 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) 6175 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ 6176 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk 6177 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ 6178 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ 6179 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) 6180 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ 6181 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk 6182 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ 6183 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ 6184 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) 6185 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ 6186 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk 6187 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ 6188 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ 6189 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) 6190 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ 6191 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk 6192 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ 6193 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ 6194 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) 6195 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ 6196 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk 6197 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ 6198 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ 6199 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) 6200 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ 6201 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk 6202 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ 6203 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ 6204 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) 6205 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ 6206 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk 6207 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ 6208 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ 6209 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) 6210 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ 6211 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk 6212 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ 6213 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ 6214 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) 6215 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ 6216 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk 6217 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ 6218 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ 6219 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) 6220 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ 6221 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk 6222 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ 6223 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ 6224 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) 6225 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ 6226 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk 6227 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ 6228 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ 6229 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) 6230 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ 6231 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk 6232 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ 6233 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ 6234 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) 6235 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ 6236 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk 6237 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ 6238 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ 6239 6240 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ 6241 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 6242 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 6243 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 6244 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 6245 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 6246 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 6247 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 6248 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 6249 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 6250 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 6251 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 6252 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 6253 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 6254 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 6255 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 6256 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 6257 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 6258 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 6259 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 6260 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 6261 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 6262 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 6263 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 6264 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 6265 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 6266 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 6267 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 6268 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 6269 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 6270 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 6271 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 6272 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 6273 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 6274 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 6275 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 6276 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 6277 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 6278 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 6279 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 6280 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 6281 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 6282 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 6283 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 6284 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 6285 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 6286 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 6287 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 6288 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 6289 6290 /******************* Bit definition for GPIO_PUPDR register ******************/ 6291 #define GPIO_PUPDR_PUPDR0_Pos (0U) 6292 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 6293 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 6294 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 6295 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 6296 #define GPIO_PUPDR_PUPDR1_Pos (2U) 6297 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 6298 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 6299 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 6300 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 6301 #define GPIO_PUPDR_PUPDR2_Pos (4U) 6302 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 6303 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 6304 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 6305 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 6306 #define GPIO_PUPDR_PUPDR3_Pos (6U) 6307 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 6308 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 6309 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 6310 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 6311 #define GPIO_PUPDR_PUPDR4_Pos (8U) 6312 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 6313 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 6314 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 6315 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 6316 #define GPIO_PUPDR_PUPDR5_Pos (10U) 6317 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 6318 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 6319 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 6320 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 6321 #define GPIO_PUPDR_PUPDR6_Pos (12U) 6322 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 6323 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 6324 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 6325 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 6326 #define GPIO_PUPDR_PUPDR7_Pos (14U) 6327 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 6328 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 6329 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 6330 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 6331 #define GPIO_PUPDR_PUPDR8_Pos (16U) 6332 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 6333 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 6334 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 6335 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 6336 #define GPIO_PUPDR_PUPDR9_Pos (18U) 6337 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 6338 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 6339 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 6340 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 6341 #define GPIO_PUPDR_PUPDR10_Pos (20U) 6342 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 6343 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 6344 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 6345 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 6346 #define GPIO_PUPDR_PUPDR11_Pos (22U) 6347 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 6348 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 6349 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 6350 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 6351 #define GPIO_PUPDR_PUPDR12_Pos (24U) 6352 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 6353 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 6354 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 6355 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 6356 #define GPIO_PUPDR_PUPDR13_Pos (26U) 6357 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 6358 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 6359 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 6360 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 6361 #define GPIO_PUPDR_PUPDR14_Pos (28U) 6362 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 6363 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 6364 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 6365 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 6366 #define GPIO_PUPDR_PUPDR15_Pos (30U) 6367 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 6368 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 6369 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 6370 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 6371 6372 /******************* Bit definition for GPIO_IDR register *******************/ 6373 #define GPIO_IDR_0 (0x00000001U) 6374 #define GPIO_IDR_1 (0x00000002U) 6375 #define GPIO_IDR_2 (0x00000004U) 6376 #define GPIO_IDR_3 (0x00000008U) 6377 #define GPIO_IDR_4 (0x00000010U) 6378 #define GPIO_IDR_5 (0x00000020U) 6379 #define GPIO_IDR_6 (0x00000040U) 6380 #define GPIO_IDR_7 (0x00000080U) 6381 #define GPIO_IDR_8 (0x00000100U) 6382 #define GPIO_IDR_9 (0x00000200U) 6383 #define GPIO_IDR_10 (0x00000400U) 6384 #define GPIO_IDR_11 (0x00000800U) 6385 #define GPIO_IDR_12 (0x00001000U) 6386 #define GPIO_IDR_13 (0x00002000U) 6387 #define GPIO_IDR_14 (0x00004000U) 6388 #define GPIO_IDR_15 (0x00008000U) 6389 6390 /****************** Bit definition for GPIO_ODR register ********************/ 6391 #define GPIO_ODR_0 (0x00000001U) 6392 #define GPIO_ODR_1 (0x00000002U) 6393 #define GPIO_ODR_2 (0x00000004U) 6394 #define GPIO_ODR_3 (0x00000008U) 6395 #define GPIO_ODR_4 (0x00000010U) 6396 #define GPIO_ODR_5 (0x00000020U) 6397 #define GPIO_ODR_6 (0x00000040U) 6398 #define GPIO_ODR_7 (0x00000080U) 6399 #define GPIO_ODR_8 (0x00000100U) 6400 #define GPIO_ODR_9 (0x00000200U) 6401 #define GPIO_ODR_10 (0x00000400U) 6402 #define GPIO_ODR_11 (0x00000800U) 6403 #define GPIO_ODR_12 (0x00001000U) 6404 #define GPIO_ODR_13 (0x00002000U) 6405 #define GPIO_ODR_14 (0x00004000U) 6406 #define GPIO_ODR_15 (0x00008000U) 6407 6408 /****************** Bit definition for GPIO_BSRR register ********************/ 6409 #define GPIO_BSRR_BS_0 (0x00000001U) 6410 #define GPIO_BSRR_BS_1 (0x00000002U) 6411 #define GPIO_BSRR_BS_2 (0x00000004U) 6412 #define GPIO_BSRR_BS_3 (0x00000008U) 6413 #define GPIO_BSRR_BS_4 (0x00000010U) 6414 #define GPIO_BSRR_BS_5 (0x00000020U) 6415 #define GPIO_BSRR_BS_6 (0x00000040U) 6416 #define GPIO_BSRR_BS_7 (0x00000080U) 6417 #define GPIO_BSRR_BS_8 (0x00000100U) 6418 #define GPIO_BSRR_BS_9 (0x00000200U) 6419 #define GPIO_BSRR_BS_10 (0x00000400U) 6420 #define GPIO_BSRR_BS_11 (0x00000800U) 6421 #define GPIO_BSRR_BS_12 (0x00001000U) 6422 #define GPIO_BSRR_BS_13 (0x00002000U) 6423 #define GPIO_BSRR_BS_14 (0x00004000U) 6424 #define GPIO_BSRR_BS_15 (0x00008000U) 6425 #define GPIO_BSRR_BR_0 (0x00010000U) 6426 #define GPIO_BSRR_BR_1 (0x00020000U) 6427 #define GPIO_BSRR_BR_2 (0x00040000U) 6428 #define GPIO_BSRR_BR_3 (0x00080000U) 6429 #define GPIO_BSRR_BR_4 (0x00100000U) 6430 #define GPIO_BSRR_BR_5 (0x00200000U) 6431 #define GPIO_BSRR_BR_6 (0x00400000U) 6432 #define GPIO_BSRR_BR_7 (0x00800000U) 6433 #define GPIO_BSRR_BR_8 (0x01000000U) 6434 #define GPIO_BSRR_BR_9 (0x02000000U) 6435 #define GPIO_BSRR_BR_10 (0x04000000U) 6436 #define GPIO_BSRR_BR_11 (0x08000000U) 6437 #define GPIO_BSRR_BR_12 (0x10000000U) 6438 #define GPIO_BSRR_BR_13 (0x20000000U) 6439 #define GPIO_BSRR_BR_14 (0x40000000U) 6440 #define GPIO_BSRR_BR_15 (0x80000000U) 6441 6442 /****************** Bit definition for GPIO_LCKR register ********************/ 6443 #define GPIO_LCKR_LCK0_Pos (0U) 6444 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 6445 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 6446 #define GPIO_LCKR_LCK1_Pos (1U) 6447 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 6448 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 6449 #define GPIO_LCKR_LCK2_Pos (2U) 6450 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 6451 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 6452 #define GPIO_LCKR_LCK3_Pos (3U) 6453 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 6454 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 6455 #define GPIO_LCKR_LCK4_Pos (4U) 6456 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 6457 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 6458 #define GPIO_LCKR_LCK5_Pos (5U) 6459 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 6460 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 6461 #define GPIO_LCKR_LCK6_Pos (6U) 6462 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 6463 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 6464 #define GPIO_LCKR_LCK7_Pos (7U) 6465 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 6466 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 6467 #define GPIO_LCKR_LCK8_Pos (8U) 6468 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 6469 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 6470 #define GPIO_LCKR_LCK9_Pos (9U) 6471 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 6472 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 6473 #define GPIO_LCKR_LCK10_Pos (10U) 6474 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 6475 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 6476 #define GPIO_LCKR_LCK11_Pos (11U) 6477 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 6478 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 6479 #define GPIO_LCKR_LCK12_Pos (12U) 6480 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 6481 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 6482 #define GPIO_LCKR_LCK13_Pos (13U) 6483 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 6484 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 6485 #define GPIO_LCKR_LCK14_Pos (14U) 6486 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 6487 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 6488 #define GPIO_LCKR_LCK15_Pos (15U) 6489 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 6490 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 6491 #define GPIO_LCKR_LCKK_Pos (16U) 6492 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 6493 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 6494 6495 /****************** Bit definition for GPIO_AFRL register ********************/ 6496 #define GPIO_AFRL_AFSEL0_Pos (0U) 6497 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 6498 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 6499 #define GPIO_AFRL_AFSEL1_Pos (4U) 6500 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 6501 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 6502 #define GPIO_AFRL_AFSEL2_Pos (8U) 6503 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 6504 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 6505 #define GPIO_AFRL_AFSEL3_Pos (12U) 6506 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 6507 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 6508 #define GPIO_AFRL_AFSEL4_Pos (16U) 6509 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 6510 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 6511 #define GPIO_AFRL_AFSEL5_Pos (20U) 6512 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 6513 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 6514 #define GPIO_AFRL_AFSEL6_Pos (24U) 6515 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 6516 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 6517 #define GPIO_AFRL_AFSEL7_Pos (28U) 6518 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 6519 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 6520 6521 /* Legacy aliases */ 6522 #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos 6523 #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk 6524 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 6525 #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos 6526 #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk 6527 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 6528 #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos 6529 #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk 6530 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 6531 #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos 6532 #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk 6533 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 6534 #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos 6535 #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk 6536 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 6537 #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos 6538 #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk 6539 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 6540 #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos 6541 #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk 6542 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 6543 #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos 6544 #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk 6545 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 6546 6547 /****************** Bit definition for GPIO_AFRH register ********************/ 6548 #define GPIO_AFRH_AFSEL8_Pos (0U) 6549 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 6550 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 6551 #define GPIO_AFRH_AFSEL9_Pos (4U) 6552 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 6553 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 6554 #define GPIO_AFRH_AFSEL10_Pos (8U) 6555 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 6556 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 6557 #define GPIO_AFRH_AFSEL11_Pos (12U) 6558 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 6559 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 6560 #define GPIO_AFRH_AFSEL12_Pos (16U) 6561 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 6562 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 6563 #define GPIO_AFRH_AFSEL13_Pos (20U) 6564 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 6565 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 6566 #define GPIO_AFRH_AFSEL14_Pos (24U) 6567 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 6568 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 6569 #define GPIO_AFRH_AFSEL15_Pos (28U) 6570 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 6571 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 6572 6573 /* Legacy aliases */ 6574 #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos 6575 #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk 6576 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 6577 #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos 6578 #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk 6579 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 6580 #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos 6581 #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk 6582 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 6583 #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos 6584 #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk 6585 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 6586 #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos 6587 #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk 6588 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 6589 #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos 6590 #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk 6591 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 6592 #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos 6593 #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk 6594 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 6595 #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos 6596 #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk 6597 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 6598 6599 /****************** Bit definition for GPIO_BRR register *********************/ 6600 #define GPIO_BRR_BR_0 (0x00000001U) 6601 #define GPIO_BRR_BR_1 (0x00000002U) 6602 #define GPIO_BRR_BR_2 (0x00000004U) 6603 #define GPIO_BRR_BR_3 (0x00000008U) 6604 #define GPIO_BRR_BR_4 (0x00000010U) 6605 #define GPIO_BRR_BR_5 (0x00000020U) 6606 #define GPIO_BRR_BR_6 (0x00000040U) 6607 #define GPIO_BRR_BR_7 (0x00000080U) 6608 #define GPIO_BRR_BR_8 (0x00000100U) 6609 #define GPIO_BRR_BR_9 (0x00000200U) 6610 #define GPIO_BRR_BR_10 (0x00000400U) 6611 #define GPIO_BRR_BR_11 (0x00000800U) 6612 #define GPIO_BRR_BR_12 (0x00001000U) 6613 #define GPIO_BRR_BR_13 (0x00002000U) 6614 #define GPIO_BRR_BR_14 (0x00004000U) 6615 #define GPIO_BRR_BR_15 (0x00008000U) 6616 6617 /******************************************************************************/ 6618 /* */ 6619 /* Inter-integrated Circuit Interface (I2C) */ 6620 /* */ 6621 /******************************************************************************/ 6622 6623 /******************* Bit definition for I2C_CR1 register *******************/ 6624 #define I2C_CR1_PE_Pos (0U) 6625 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 6626 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 6627 #define I2C_CR1_TXIE_Pos (1U) 6628 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 6629 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 6630 #define I2C_CR1_RXIE_Pos (2U) 6631 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 6632 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 6633 #define I2C_CR1_ADDRIE_Pos (3U) 6634 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 6635 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 6636 #define I2C_CR1_NACKIE_Pos (4U) 6637 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 6638 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 6639 #define I2C_CR1_STOPIE_Pos (5U) 6640 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 6641 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 6642 #define I2C_CR1_TCIE_Pos (6U) 6643 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 6644 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 6645 #define I2C_CR1_ERRIE_Pos (7U) 6646 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 6647 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 6648 #define I2C_CR1_DNF_Pos (8U) 6649 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 6650 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 6651 #define I2C_CR1_ANFOFF_Pos (12U) 6652 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 6653 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 6654 #define I2C_CR1_SWRST_Pos (13U) 6655 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 6656 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 6657 #define I2C_CR1_TXDMAEN_Pos (14U) 6658 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 6659 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 6660 #define I2C_CR1_RXDMAEN_Pos (15U) 6661 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 6662 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 6663 #define I2C_CR1_SBC_Pos (16U) 6664 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 6665 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 6666 #define I2C_CR1_NOSTRETCH_Pos (17U) 6667 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 6668 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 6669 #define I2C_CR1_WUPEN_Pos (18U) 6670 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 6671 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 6672 #define I2C_CR1_GCEN_Pos (19U) 6673 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 6674 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 6675 #define I2C_CR1_SMBHEN_Pos (20U) 6676 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 6677 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 6678 #define I2C_CR1_SMBDEN_Pos (21U) 6679 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 6680 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 6681 #define I2C_CR1_ALERTEN_Pos (22U) 6682 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 6683 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 6684 #define I2C_CR1_PECEN_Pos (23U) 6685 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 6686 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 6687 6688 /****************** Bit definition for I2C_CR2 register ********************/ 6689 #define I2C_CR2_SADD_Pos (0U) 6690 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 6691 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 6692 #define I2C_CR2_RD_WRN_Pos (10U) 6693 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 6694 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 6695 #define I2C_CR2_ADD10_Pos (11U) 6696 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 6697 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 6698 #define I2C_CR2_HEAD10R_Pos (12U) 6699 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 6700 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 6701 #define I2C_CR2_START_Pos (13U) 6702 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 6703 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 6704 #define I2C_CR2_STOP_Pos (14U) 6705 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 6706 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 6707 #define I2C_CR2_NACK_Pos (15U) 6708 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 6709 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 6710 #define I2C_CR2_NBYTES_Pos (16U) 6711 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 6712 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 6713 #define I2C_CR2_RELOAD_Pos (24U) 6714 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 6715 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 6716 #define I2C_CR2_AUTOEND_Pos (25U) 6717 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 6718 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 6719 #define I2C_CR2_PECBYTE_Pos (26U) 6720 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 6721 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 6722 6723 /******************* Bit definition for I2C_OAR1 register ******************/ 6724 #define I2C_OAR1_OA1_Pos (0U) 6725 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 6726 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 6727 #define I2C_OAR1_OA1MODE_Pos (10U) 6728 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 6729 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 6730 #define I2C_OAR1_OA1EN_Pos (15U) 6731 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 6732 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 6733 6734 /******************* Bit definition for I2C_OAR2 register ******************/ 6735 #define I2C_OAR2_OA2_Pos (1U) 6736 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 6737 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 6738 #define I2C_OAR2_OA2MSK_Pos (8U) 6739 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 6740 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 6741 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 6742 #define I2C_OAR2_OA2MASK01_Pos (8U) 6743 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 6744 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 6745 #define I2C_OAR2_OA2MASK02_Pos (9U) 6746 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 6747 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 6748 #define I2C_OAR2_OA2MASK03_Pos (8U) 6749 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 6750 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 6751 #define I2C_OAR2_OA2MASK04_Pos (10U) 6752 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 6753 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 6754 #define I2C_OAR2_OA2MASK05_Pos (8U) 6755 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 6756 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 6757 #define I2C_OAR2_OA2MASK06_Pos (9U) 6758 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 6759 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 6760 #define I2C_OAR2_OA2MASK07_Pos (8U) 6761 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 6762 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 6763 #define I2C_OAR2_OA2EN_Pos (15U) 6764 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 6765 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 6766 6767 /******************* Bit definition for I2C_TIMINGR register ****************/ 6768 #define I2C_TIMINGR_SCLL_Pos (0U) 6769 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 6770 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 6771 #define I2C_TIMINGR_SCLH_Pos (8U) 6772 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 6773 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 6774 #define I2C_TIMINGR_SDADEL_Pos (16U) 6775 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 6776 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 6777 #define I2C_TIMINGR_SCLDEL_Pos (20U) 6778 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 6779 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 6780 #define I2C_TIMINGR_PRESC_Pos (28U) 6781 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 6782 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 6783 6784 /******************* Bit definition for I2C_TIMEOUTR register ****************/ 6785 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 6786 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 6787 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 6788 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 6789 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 6790 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 6791 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 6792 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 6793 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 6794 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 6795 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 6796 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 6797 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 6798 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 6799 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 6800 6801 /****************** Bit definition for I2C_ISR register ********************/ 6802 #define I2C_ISR_TXE_Pos (0U) 6803 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 6804 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 6805 #define I2C_ISR_TXIS_Pos (1U) 6806 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 6807 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 6808 #define I2C_ISR_RXNE_Pos (2U) 6809 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 6810 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 6811 #define I2C_ISR_ADDR_Pos (3U) 6812 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 6813 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 6814 #define I2C_ISR_NACKF_Pos (4U) 6815 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 6816 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 6817 #define I2C_ISR_STOPF_Pos (5U) 6818 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 6819 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 6820 #define I2C_ISR_TC_Pos (6U) 6821 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 6822 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 6823 #define I2C_ISR_TCR_Pos (7U) 6824 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 6825 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 6826 #define I2C_ISR_BERR_Pos (8U) 6827 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 6828 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 6829 #define I2C_ISR_ARLO_Pos (9U) 6830 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 6831 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 6832 #define I2C_ISR_OVR_Pos (10U) 6833 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 6834 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 6835 #define I2C_ISR_PECERR_Pos (11U) 6836 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 6837 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 6838 #define I2C_ISR_TIMEOUT_Pos (12U) 6839 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 6840 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 6841 #define I2C_ISR_ALERT_Pos (13U) 6842 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 6843 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 6844 #define I2C_ISR_BUSY_Pos (15U) 6845 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 6846 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 6847 #define I2C_ISR_DIR_Pos (16U) 6848 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 6849 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 6850 #define I2C_ISR_ADDCODE_Pos (17U) 6851 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 6852 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 6853 6854 /****************** Bit definition for I2C_ICR register ********************/ 6855 #define I2C_ICR_ADDRCF_Pos (3U) 6856 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 6857 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 6858 #define I2C_ICR_NACKCF_Pos (4U) 6859 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 6860 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 6861 #define I2C_ICR_STOPCF_Pos (5U) 6862 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 6863 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 6864 #define I2C_ICR_BERRCF_Pos (8U) 6865 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 6866 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 6867 #define I2C_ICR_ARLOCF_Pos (9U) 6868 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 6869 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 6870 #define I2C_ICR_OVRCF_Pos (10U) 6871 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 6872 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 6873 #define I2C_ICR_PECCF_Pos (11U) 6874 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 6875 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 6876 #define I2C_ICR_TIMOUTCF_Pos (12U) 6877 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 6878 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 6879 #define I2C_ICR_ALERTCF_Pos (13U) 6880 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 6881 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 6882 6883 /****************** Bit definition for I2C_PECR register *******************/ 6884 #define I2C_PECR_PEC_Pos (0U) 6885 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 6886 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 6887 6888 /****************** Bit definition for I2C_RXDR register *********************/ 6889 #define I2C_RXDR_RXDATA_Pos (0U) 6890 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 6891 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 6892 6893 /****************** Bit definition for I2C_TXDR register *******************/ 6894 #define I2C_TXDR_TXDATA_Pos (0U) 6895 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 6896 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 6897 6898 /*****************************************************************************/ 6899 /* */ 6900 /* Independent WATCHDOG (IWDG) */ 6901 /* */ 6902 /*****************************************************************************/ 6903 /******************* Bit definition for IWDG_KR register *******************/ 6904 #define IWDG_KR_KEY_Pos (0U) 6905 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 6906 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 6907 6908 /******************* Bit definition for IWDG_PR register *******************/ 6909 #define IWDG_PR_PR_Pos (0U) 6910 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 6911 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 6912 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */ 6913 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */ 6914 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */ 6915 6916 /******************* Bit definition for IWDG_RLR register ******************/ 6917 #define IWDG_RLR_RL_Pos (0U) 6918 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 6919 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 6920 6921 /******************* Bit definition for IWDG_SR register *******************/ 6922 #define IWDG_SR_PVU_Pos (0U) 6923 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 6924 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 6925 #define IWDG_SR_RVU_Pos (1U) 6926 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 6927 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 6928 #define IWDG_SR_WVU_Pos (2U) 6929 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 6930 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 6931 6932 /******************* Bit definition for IWDG_KR register *******************/ 6933 #define IWDG_WINR_WIN_Pos (0U) 6934 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 6935 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 6936 6937 /*****************************************************************************/ 6938 /* */ 6939 /* Power Control (PWR) */ 6940 /* */ 6941 /*****************************************************************************/ 6942 6943 /* Note: No specific macro feature on this device */ 6944 6945 6946 /******************** Bit definition for PWR_CR register *******************/ 6947 #define PWR_CR_LPDS_Pos (0U) 6948 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 6949 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ 6950 #define PWR_CR_PDDS_Pos (1U) 6951 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 6952 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 6953 #define PWR_CR_CWUF_Pos (2U) 6954 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 6955 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 6956 #define PWR_CR_CSBF_Pos (3U) 6957 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 6958 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 6959 #define PWR_CR_DBP_Pos (8U) 6960 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 6961 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 6962 6963 /******************* Bit definition for PWR_CSR register *******************/ 6964 #define PWR_CSR_WUF_Pos (0U) 6965 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 6966 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 6967 #define PWR_CSR_SBF_Pos (1U) 6968 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 6969 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 6970 #define PWR_CSR_VREFINTRDYF_Pos (3U) 6971 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 6972 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 6973 6974 #define PWR_CSR_EWUP1_Pos (8U) 6975 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 6976 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 6977 #define PWR_CSR_EWUP2_Pos (9U) 6978 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 6979 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 6980 #define PWR_CSR_EWUP4_Pos (11U) 6981 #define PWR_CSR_EWUP4_Msk (0x1UL << PWR_CSR_EWUP4_Pos) /*!< 0x00000800 */ 6982 #define PWR_CSR_EWUP4 PWR_CSR_EWUP4_Msk /*!< Enable WKUP pin 4 */ 6983 #define PWR_CSR_EWUP6_Pos (13U) 6984 #define PWR_CSR_EWUP6_Msk (0x1UL << PWR_CSR_EWUP6_Pos) /*!< 0x00002000 */ 6985 #define PWR_CSR_EWUP6 PWR_CSR_EWUP6_Msk /*!< Enable WKUP pin 6 */ 6986 #define PWR_CSR_EWUP7_Pos (14U) 6987 #define PWR_CSR_EWUP7_Msk (0x1UL << PWR_CSR_EWUP7_Pos) /*!< 0x00004000 */ 6988 #define PWR_CSR_EWUP7 PWR_CSR_EWUP7_Msk /*!< Enable WKUP pin 7 */ 6989 6990 /*****************************************************************************/ 6991 /* */ 6992 /* Reset and Clock Control */ 6993 /* */ 6994 /*****************************************************************************/ 6995 /* 6996 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 6997 */ 6998 #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ 6999 #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ 7000 7001 /******************** Bit definition for RCC_CR register *******************/ 7002 #define RCC_CR_HSION_Pos (0U) 7003 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 7004 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 7005 #define RCC_CR_HSIRDY_Pos (1U) 7006 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 7007 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 7008 7009 #define RCC_CR_HSITRIM_Pos (3U) 7010 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 7011 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 7012 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 7013 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 7014 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 7015 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 7016 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 7017 7018 #define RCC_CR_HSICAL_Pos (8U) 7019 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 7020 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 7021 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 7022 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 7023 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 7024 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 7025 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 7026 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 7027 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 7028 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 7029 7030 #define RCC_CR_HSEON_Pos (16U) 7031 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 7032 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 7033 #define RCC_CR_HSERDY_Pos (17U) 7034 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 7035 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 7036 #define RCC_CR_HSEBYP_Pos (18U) 7037 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 7038 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 7039 #define RCC_CR_CSSON_Pos (19U) 7040 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 7041 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 7042 #define RCC_CR_PLLON_Pos (24U) 7043 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 7044 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 7045 #define RCC_CR_PLLRDY_Pos (25U) 7046 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 7047 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 7048 7049 /******************** Bit definition for RCC_CFGR register *****************/ 7050 /*!< SW configuration */ 7051 #define RCC_CFGR_SW_Pos (0U) 7052 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 7053 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 7054 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 7055 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 7056 7057 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ 7058 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ 7059 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ 7060 #define RCC_CFGR_SW_HSI48 (0x00000003U) /*!< HSI48 selected as system clock */ 7061 7062 /*!< SWS configuration */ 7063 #define RCC_CFGR_SWS_Pos (2U) 7064 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 7065 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 7066 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 7067 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 7068 7069 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ 7070 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ 7071 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ 7072 #define RCC_CFGR_SWS_HSI48 (0x0000000CU) /*!< HSI48 oscillator used as system clock */ 7073 7074 /*!< HPRE configuration */ 7075 #define RCC_CFGR_HPRE_Pos (4U) 7076 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 7077 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 7078 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 7079 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 7080 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 7081 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 7082 7083 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 7084 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 7085 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 7086 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 7087 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 7088 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 7089 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 7090 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 7091 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 7092 7093 /*!< PPRE configuration */ 7094 #define RCC_CFGR_PPRE_Pos (8U) 7095 #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */ 7096 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */ 7097 #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */ 7098 #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */ 7099 #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */ 7100 7101 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */ 7102 #define RCC_CFGR_PPRE_DIV2_Pos (10U) 7103 #define RCC_CFGR_PPRE_DIV2_Msk (0x1UL << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */ 7104 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */ 7105 #define RCC_CFGR_PPRE_DIV4_Pos (8U) 7106 #define RCC_CFGR_PPRE_DIV4_Msk (0x5UL << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */ 7107 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */ 7108 #define RCC_CFGR_PPRE_DIV8_Pos (9U) 7109 #define RCC_CFGR_PPRE_DIV8_Msk (0x3UL << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */ 7110 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ 7111 #define RCC_CFGR_PPRE_DIV16_Pos (8U) 7112 #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ 7113 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ 7114 7115 /*!< ADCPPRE configuration */ 7116 #define RCC_CFGR_ADCPRE_Pos (14U) 7117 #define RCC_CFGR_ADCPRE_Msk (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 7118 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */ 7119 7120 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */ 7121 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */ 7122 7123 #define RCC_CFGR_PLLSRC_Pos (15U) 7124 #define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */ 7125 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 7126 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 7127 #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */ 7128 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ 7129 #define RCC_CFGR_PLLSRC_HSI48_PREDIV (0x00018000U) /*!< HSI48/PREDIV clock selected as PLL entry clock source */ 7130 7131 #define RCC_CFGR_PLLXTPRE_Pos (17U) 7132 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 7133 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 7134 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ 7135 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ 7136 7137 /*!< PLLMUL configuration */ 7138 #define RCC_CFGR_PLLMUL_Pos (18U) 7139 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 7140 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 7141 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 7142 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 7143 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 7144 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 7145 7146 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ 7147 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ 7148 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ 7149 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ 7150 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ 7151 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ 7152 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ 7153 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ 7154 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ 7155 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ 7156 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ 7157 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ 7158 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ 7159 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ 7160 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ 7161 7162 /*!< USB configuration */ 7163 #define RCC_CFGR_USBPRE_Pos (22U) 7164 #define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ 7165 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB prescaler */ 7166 7167 /*!< MCO configuration */ 7168 #define RCC_CFGR_MCO_Pos (24U) 7169 #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ 7170 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 7171 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 7172 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 7173 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 7174 #define RCC_CFGR_MCO_3 (0x08000000U) /*!< Bit 3 */ 7175 7176 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ 7177 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */ 7178 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ 7179 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ 7180 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ 7181 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ 7182 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ 7183 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ 7184 #define RCC_CFGR_MCO_HSI48 (0x08000000U) /*!< HSI48 clock selected as MCO source */ 7185 7186 #define RCC_CFGR_MCOPRE_Pos (28U) 7187 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 7188 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 7189 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 7190 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 7191 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 7192 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 7193 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 7194 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */ 7195 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */ 7196 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */ 7197 7198 #define RCC_CFGR_PLLNODIV_Pos (31U) 7199 #define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */ 7200 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */ 7201 7202 /* Reference defines */ 7203 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 7204 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 7205 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 7206 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 7207 #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3 7208 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 7209 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14 7210 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI 7211 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE 7212 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 7213 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 7214 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 7215 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL 7216 #define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCO_HSI48 7217 7218 /*!<****************** Bit definition for RCC_CIR register *****************/ 7219 #define RCC_CIR_LSIRDYF_Pos (0U) 7220 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 7221 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 7222 #define RCC_CIR_LSERDYF_Pos (1U) 7223 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 7224 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 7225 #define RCC_CIR_HSIRDYF_Pos (2U) 7226 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 7227 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 7228 #define RCC_CIR_HSERDYF_Pos (3U) 7229 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 7230 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 7231 #define RCC_CIR_PLLRDYF_Pos (4U) 7232 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 7233 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 7234 #define RCC_CIR_HSI14RDYF_Pos (5U) 7235 #define RCC_CIR_HSI14RDYF_Msk (0x1UL << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */ 7236 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */ 7237 #define RCC_CIR_HSI48RDYF_Pos (6U) 7238 #define RCC_CIR_HSI48RDYF_Msk (0x1UL << RCC_CIR_HSI48RDYF_Pos) /*!< 0x00000040 */ 7239 #define RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */ 7240 #define RCC_CIR_CSSF_Pos (7U) 7241 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 7242 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 7243 #define RCC_CIR_LSIRDYIE_Pos (8U) 7244 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 7245 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 7246 #define RCC_CIR_LSERDYIE_Pos (9U) 7247 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 7248 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 7249 #define RCC_CIR_HSIRDYIE_Pos (10U) 7250 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 7251 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 7252 #define RCC_CIR_HSERDYIE_Pos (11U) 7253 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 7254 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 7255 #define RCC_CIR_PLLRDYIE_Pos (12U) 7256 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 7257 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 7258 #define RCC_CIR_HSI14RDYIE_Pos (13U) 7259 #define RCC_CIR_HSI14RDYIE_Msk (0x1UL << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */ 7260 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */ 7261 #define RCC_CIR_HSI48RDYIE_Pos (14U) 7262 #define RCC_CIR_HSI48RDYIE_Msk (0x1UL << RCC_CIR_HSI48RDYIE_Pos) /*!< 0x00004000 */ 7263 #define RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */ 7264 #define RCC_CIR_LSIRDYC_Pos (16U) 7265 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 7266 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 7267 #define RCC_CIR_LSERDYC_Pos (17U) 7268 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 7269 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 7270 #define RCC_CIR_HSIRDYC_Pos (18U) 7271 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 7272 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 7273 #define RCC_CIR_HSERDYC_Pos (19U) 7274 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 7275 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 7276 #define RCC_CIR_PLLRDYC_Pos (20U) 7277 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 7278 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 7279 #define RCC_CIR_HSI14RDYC_Pos (21U) 7280 #define RCC_CIR_HSI14RDYC_Msk (0x1UL << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */ 7281 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */ 7282 #define RCC_CIR_HSI48RDYC_Pos (22U) 7283 #define RCC_CIR_HSI48RDYC_Msk (0x1UL << RCC_CIR_HSI48RDYC_Pos) /*!< 0x00400000 */ 7284 #define RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */ 7285 #define RCC_CIR_CSSC_Pos (23U) 7286 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 7287 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 7288 7289 /***************** Bit definition for RCC_APB2RSTR register ****************/ 7290 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 7291 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 7292 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 7293 #define RCC_APB2RSTR_ADCRST_Pos (9U) 7294 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 7295 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ 7296 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 7297 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 7298 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ 7299 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 7300 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 7301 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 7302 #define RCC_APB2RSTR_USART1RST_Pos (14U) 7303 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 7304 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 7305 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 7306 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 7307 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ 7308 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 7309 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 7310 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ 7311 #define RCC_APB2RSTR_DBGMCURST_Pos (22U) 7312 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ 7313 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ 7314 7315 /*!< Old ADC1 reset bit definition maintained for legacy purpose */ 7316 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST 7317 7318 /***************** Bit definition for RCC_APB1RSTR register ****************/ 7319 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 7320 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 7321 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 7322 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 7323 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 7324 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 7325 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 7326 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ 7327 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ 7328 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 7329 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 7330 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 7331 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 7332 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 7333 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ 7334 #define RCC_APB1RSTR_USART2RST_Pos (17U) 7335 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 7336 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 7337 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 7338 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 7339 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 7340 #define RCC_APB1RSTR_USBRST_Pos (23U) 7341 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ 7342 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ 7343 #define RCC_APB1RSTR_CANRST_Pos (25U) 7344 #define RCC_APB1RSTR_CANRST_Msk (0x1UL << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ 7345 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ 7346 #define RCC_APB1RSTR_CRSRST_Pos (27U) 7347 #define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ 7348 #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ 7349 #define RCC_APB1RSTR_PWRRST_Pos (28U) 7350 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 7351 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 7352 #define RCC_APB1RSTR_CECRST_Pos (30U) 7353 #define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ 7354 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ 7355 7356 /****************** Bit definition for RCC_AHBENR register *****************/ 7357 #define RCC_AHBENR_DMAEN_Pos (0U) 7358 #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 7359 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 7360 #define RCC_AHBENR_SRAMEN_Pos (2U) 7361 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 7362 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 7363 #define RCC_AHBENR_FLITFEN_Pos (4U) 7364 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 7365 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 7366 #define RCC_AHBENR_CRCEN_Pos (6U) 7367 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 7368 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 7369 #define RCC_AHBENR_GPIOAEN_Pos (17U) 7370 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ 7371 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ 7372 #define RCC_AHBENR_GPIOBEN_Pos (18U) 7373 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ 7374 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ 7375 #define RCC_AHBENR_GPIOCEN_Pos (19U) 7376 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ 7377 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ 7378 #define RCC_AHBENR_GPIOFEN_Pos (22U) 7379 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ 7380 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ 7381 #define RCC_AHBENR_TSCEN_Pos (24U) 7382 #define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */ 7383 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller clock enable */ 7384 7385 /* Old Bit definition maintained for legacy purpose */ 7386 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 7387 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */ 7388 7389 /***************** Bit definition for RCC_APB2ENR register *****************/ 7390 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U) 7391 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */ 7392 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */ 7393 #define RCC_APB2ENR_ADCEN_Pos (9U) 7394 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 7395 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 7396 #define RCC_APB2ENR_TIM1EN_Pos (11U) 7397 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 7398 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ 7399 #define RCC_APB2ENR_SPI1EN_Pos (12U) 7400 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 7401 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 7402 #define RCC_APB2ENR_USART1EN_Pos (14U) 7403 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 7404 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 7405 #define RCC_APB2ENR_TIM16EN_Pos (17U) 7406 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 7407 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ 7408 #define RCC_APB2ENR_TIM17EN_Pos (18U) 7409 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 7410 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ 7411 #define RCC_APB2ENR_DBGMCUEN_Pos (22U) 7412 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */ 7413 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */ 7414 7415 /* Old Bit definition maintained for legacy purpose */ 7416 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */ 7417 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 7418 7419 /***************** Bit definition for RCC_APB1ENR register *****************/ 7420 #define RCC_APB1ENR_TIM2EN_Pos (0U) 7421 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 7422 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 7423 #define RCC_APB1ENR_TIM3EN_Pos (1U) 7424 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 7425 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 7426 #define RCC_APB1ENR_TIM14EN_Pos (8U) 7427 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ 7428 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */ 7429 #define RCC_APB1ENR_WWDGEN_Pos (11U) 7430 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 7431 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 7432 #define RCC_APB1ENR_SPI2EN_Pos (14U) 7433 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 7434 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 7435 #define RCC_APB1ENR_USART2EN_Pos (17U) 7436 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 7437 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 7438 #define RCC_APB1ENR_I2C1EN_Pos (21U) 7439 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 7440 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 7441 #define RCC_APB1ENR_USBEN_Pos (23U) 7442 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ 7443 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ 7444 #define RCC_APB1ENR_CANEN_Pos (25U) 7445 #define RCC_APB1ENR_CANEN_Msk (0x1UL << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */ 7446 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */ 7447 #define RCC_APB1ENR_CRSEN_Pos (27U) 7448 #define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */ 7449 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */ 7450 #define RCC_APB1ENR_PWREN_Pos (28U) 7451 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 7452 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 7453 #define RCC_APB1ENR_CECEN_Pos (30U) 7454 #define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */ 7455 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enable */ 7456 7457 /******************* Bit definition for RCC_BDCR register ******************/ 7458 #define RCC_BDCR_LSEON_Pos (0U) 7459 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 7460 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 7461 #define RCC_BDCR_LSERDY_Pos (1U) 7462 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 7463 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 7464 #define RCC_BDCR_LSEBYP_Pos (2U) 7465 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 7466 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 7467 7468 #define RCC_BDCR_LSEDRV_Pos (3U) 7469 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 7470 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 7471 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 7472 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 7473 7474 #define RCC_BDCR_RTCSEL_Pos (8U) 7475 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 7476 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 7477 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 7478 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 7479 7480 /*!< RTC configuration */ 7481 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 7482 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ 7483 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ 7484 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */ 7485 7486 #define RCC_BDCR_RTCEN_Pos (15U) 7487 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 7488 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 7489 #define RCC_BDCR_BDRST_Pos (16U) 7490 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 7491 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 7492 7493 /******************* Bit definition for RCC_CSR register *******************/ 7494 #define RCC_CSR_LSION_Pos (0U) 7495 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 7496 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 7497 #define RCC_CSR_LSIRDY_Pos (1U) 7498 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 7499 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 7500 #define RCC_CSR_RMVF_Pos (24U) 7501 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 7502 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 7503 #define RCC_CSR_OBLRSTF_Pos (25U) 7504 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 7505 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 7506 #define RCC_CSR_PINRSTF_Pos (26U) 7507 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 7508 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 7509 #define RCC_CSR_PORRSTF_Pos (27U) 7510 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 7511 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 7512 #define RCC_CSR_SFTRSTF_Pos (28U) 7513 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 7514 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 7515 #define RCC_CSR_IWDGRSTF_Pos (29U) 7516 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 7517 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 7518 #define RCC_CSR_WWDGRSTF_Pos (30U) 7519 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 7520 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 7521 #define RCC_CSR_LPWRRSTF_Pos (31U) 7522 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 7523 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 7524 7525 /* Old Bit definition maintained for legacy purpose */ 7526 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 7527 7528 /******************* Bit definition for RCC_AHBRSTR register ***************/ 7529 #define RCC_AHBRSTR_GPIOARST_Pos (17U) 7530 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ 7531 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ 7532 #define RCC_AHBRSTR_GPIOBRST_Pos (18U) 7533 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ 7534 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ 7535 #define RCC_AHBRSTR_GPIOCRST_Pos (19U) 7536 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ 7537 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ 7538 #define RCC_AHBRSTR_GPIOFRST_Pos (22U) 7539 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ 7540 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ 7541 #define RCC_AHBRSTR_TSCRST_Pos (24U) 7542 #define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ 7543 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ 7544 7545 /* Old Bit definition maintained for legacy purpose */ 7546 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ 7547 7548 /******************* Bit definition for RCC_CFGR2 register *****************/ 7549 /*!< PREDIV configuration */ 7550 #define RCC_CFGR2_PREDIV_Pos (0U) 7551 #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ 7552 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ 7553 #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ 7554 #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ 7555 #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ 7556 #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ 7557 7558 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ 7559 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ 7560 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ 7561 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ 7562 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ 7563 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ 7564 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ 7565 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ 7566 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ 7567 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ 7568 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ 7569 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ 7570 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ 7571 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ 7572 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ 7573 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ 7574 7575 /******************* Bit definition for RCC_CFGR3 register *****************/ 7576 /*!< USART1 Clock source selection */ 7577 #define RCC_CFGR3_USART1SW_Pos (0U) 7578 #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ 7579 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ 7580 #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ 7581 #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ 7582 7583 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */ 7584 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ 7585 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ 7586 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ 7587 7588 /*!< I2C1 Clock source selection */ 7589 #define RCC_CFGR3_I2C1SW_Pos (4U) 7590 #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ 7591 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ 7592 7593 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ 7594 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) 7595 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ 7596 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ 7597 7598 /*!< CEC Clock source selection */ 7599 #define RCC_CFGR3_CECSW_Pos (6U) 7600 #define RCC_CFGR3_CECSW_Msk (0x1UL << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */ 7601 #define RCC_CFGR3_CECSW RCC_CFGR3_CECSW_Msk /*!< CECSW bits */ 7602 7603 #define RCC_CFGR3_CECSW_HSI_DIV244 (0x00000000U) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ 7604 #define RCC_CFGR3_CECSW_LSE_Pos (6U) 7605 #define RCC_CFGR3_CECSW_LSE_Msk (0x1UL << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */ 7606 #define RCC_CFGR3_CECSW_LSE RCC_CFGR3_CECSW_LSE_Msk /*!< LSE clock selected as HDMI CEC entry clock source */ 7607 7608 /*!< USB Clock source selection */ 7609 #define RCC_CFGR3_USBSW_Pos (7U) 7610 #define RCC_CFGR3_USBSW_Msk (0x1UL << RCC_CFGR3_USBSW_Pos) /*!< 0x00000080 */ 7611 #define RCC_CFGR3_USBSW RCC_CFGR3_USBSW_Msk /*!< USBSW bits */ 7612 7613 #define RCC_CFGR3_USBSW_HSI48 (0x00000000U) /*!< HSI48 oscillator clock used as USB clock source */ 7614 #define RCC_CFGR3_USBSW_PLLCLK_Pos (7U) 7615 #define RCC_CFGR3_USBSW_PLLCLK_Msk (0x1UL << RCC_CFGR3_USBSW_PLLCLK_Pos) /*!< 0x00000080 */ 7616 #define RCC_CFGR3_USBSW_PLLCLK RCC_CFGR3_USBSW_PLLCLK_Msk /*!< PLLCLK selected as USB clock source */ 7617 7618 /******************* Bit definition for RCC_CR2 register *******************/ 7619 #define RCC_CR2_HSI14ON_Pos (0U) 7620 #define RCC_CR2_HSI14ON_Msk (0x1UL << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */ 7621 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */ 7622 #define RCC_CR2_HSI14RDY_Pos (1U) 7623 #define RCC_CR2_HSI14RDY_Msk (0x1UL << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */ 7624 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */ 7625 #define RCC_CR2_HSI14DIS_Pos (2U) 7626 #define RCC_CR2_HSI14DIS_Msk (0x1UL << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */ 7627 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */ 7628 #define RCC_CR2_HSI14TRIM_Pos (3U) 7629 #define RCC_CR2_HSI14TRIM_Msk (0x1FUL << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */ 7630 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */ 7631 #define RCC_CR2_HSI14CAL_Pos (8U) 7632 #define RCC_CR2_HSI14CAL_Msk (0xFFUL << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */ 7633 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */ 7634 #define RCC_CR2_HSI48ON_Pos (16U) 7635 #define RCC_CR2_HSI48ON_Msk (0x1UL << RCC_CR2_HSI48ON_Pos) /*!< 0x00010000 */ 7636 #define RCC_CR2_HSI48ON RCC_CR2_HSI48ON_Msk /*!< Internal High Speed 48MHz clock enable */ 7637 #define RCC_CR2_HSI48RDY_Pos (17U) 7638 #define RCC_CR2_HSI48RDY_Msk (0x1UL << RCC_CR2_HSI48RDY_Pos) /*!< 0x00020000 */ 7639 #define RCC_CR2_HSI48RDY RCC_CR2_HSI48RDY_Msk /*!< Internal High Speed 48MHz clock ready flag */ 7640 #define RCC_CR2_HSI48CAL_Pos (24U) 7641 #define RCC_CR2_HSI48CAL_Msk (0xFFUL << RCC_CR2_HSI48CAL_Pos) /*!< 0xFF000000 */ 7642 #define RCC_CR2_HSI48CAL RCC_CR2_HSI48CAL_Msk /*!< Internal High Speed 48MHz clock Calibration */ 7643 7644 /*****************************************************************************/ 7645 /* */ 7646 /* Real-Time Clock (RTC) */ 7647 /* */ 7648 /*****************************************************************************/ 7649 /* 7650 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 7651 */ 7652 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 7653 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 7654 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 7655 7656 /******************** Bits definition for RTC_TR register ******************/ 7657 #define RTC_TR_PM_Pos (22U) 7658 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 7659 #define RTC_TR_PM RTC_TR_PM_Msk 7660 #define RTC_TR_HT_Pos (20U) 7661 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 7662 #define RTC_TR_HT RTC_TR_HT_Msk 7663 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 7664 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 7665 #define RTC_TR_HU_Pos (16U) 7666 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 7667 #define RTC_TR_HU RTC_TR_HU_Msk 7668 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 7669 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 7670 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 7671 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 7672 #define RTC_TR_MNT_Pos (12U) 7673 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 7674 #define RTC_TR_MNT RTC_TR_MNT_Msk 7675 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 7676 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 7677 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 7678 #define RTC_TR_MNU_Pos (8U) 7679 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 7680 #define RTC_TR_MNU RTC_TR_MNU_Msk 7681 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 7682 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 7683 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 7684 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 7685 #define RTC_TR_ST_Pos (4U) 7686 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 7687 #define RTC_TR_ST RTC_TR_ST_Msk 7688 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 7689 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 7690 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 7691 #define RTC_TR_SU_Pos (0U) 7692 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 7693 #define RTC_TR_SU RTC_TR_SU_Msk 7694 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 7695 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 7696 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 7697 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 7698 7699 /******************** Bits definition for RTC_DR register ******************/ 7700 #define RTC_DR_YT_Pos (20U) 7701 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 7702 #define RTC_DR_YT RTC_DR_YT_Msk 7703 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 7704 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 7705 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 7706 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 7707 #define RTC_DR_YU_Pos (16U) 7708 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 7709 #define RTC_DR_YU RTC_DR_YU_Msk 7710 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 7711 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 7712 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 7713 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 7714 #define RTC_DR_WDU_Pos (13U) 7715 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 7716 #define RTC_DR_WDU RTC_DR_WDU_Msk 7717 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 7718 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 7719 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 7720 #define RTC_DR_MT_Pos (12U) 7721 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 7722 #define RTC_DR_MT RTC_DR_MT_Msk 7723 #define RTC_DR_MU_Pos (8U) 7724 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 7725 #define RTC_DR_MU RTC_DR_MU_Msk 7726 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 7727 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 7728 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 7729 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 7730 #define RTC_DR_DT_Pos (4U) 7731 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 7732 #define RTC_DR_DT RTC_DR_DT_Msk 7733 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 7734 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 7735 #define RTC_DR_DU_Pos (0U) 7736 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 7737 #define RTC_DR_DU RTC_DR_DU_Msk 7738 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 7739 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 7740 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 7741 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 7742 7743 /******************** Bits definition for RTC_CR register ******************/ 7744 #define RTC_CR_COE_Pos (23U) 7745 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 7746 #define RTC_CR_COE RTC_CR_COE_Msk 7747 #define RTC_CR_OSEL_Pos (21U) 7748 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 7749 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 7750 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 7751 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 7752 #define RTC_CR_POL_Pos (20U) 7753 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 7754 #define RTC_CR_POL RTC_CR_POL_Msk 7755 #define RTC_CR_COSEL_Pos (19U) 7756 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 7757 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 7758 #define RTC_CR_BKP_Pos (18U) 7759 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 7760 #define RTC_CR_BKP RTC_CR_BKP_Msk 7761 #define RTC_CR_SUB1H_Pos (17U) 7762 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 7763 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 7764 #define RTC_CR_ADD1H_Pos (16U) 7765 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 7766 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 7767 #define RTC_CR_TSIE_Pos (15U) 7768 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 7769 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 7770 #define RTC_CR_ALRAIE_Pos (12U) 7771 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 7772 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 7773 #define RTC_CR_TSE_Pos (11U) 7774 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 7775 #define RTC_CR_TSE RTC_CR_TSE_Msk 7776 #define RTC_CR_ALRAE_Pos (8U) 7777 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 7778 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 7779 #define RTC_CR_FMT_Pos (6U) 7780 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 7781 #define RTC_CR_FMT RTC_CR_FMT_Msk 7782 #define RTC_CR_BYPSHAD_Pos (5U) 7783 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 7784 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 7785 #define RTC_CR_REFCKON_Pos (4U) 7786 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 7787 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 7788 #define RTC_CR_TSEDGE_Pos (3U) 7789 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 7790 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 7791 7792 /* Legacy defines */ 7793 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 7794 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 7795 #define RTC_CR_BCK RTC_CR_BKP 7796 7797 /******************** Bits definition for RTC_ISR register *****************/ 7798 #define RTC_ISR_RECALPF_Pos (16U) 7799 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 7800 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 7801 #define RTC_ISR_TAMP2F_Pos (14U) 7802 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 7803 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 7804 #define RTC_ISR_TAMP1F_Pos (13U) 7805 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 7806 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 7807 #define RTC_ISR_TSOVF_Pos (12U) 7808 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 7809 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 7810 #define RTC_ISR_TSF_Pos (11U) 7811 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 7812 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 7813 #define RTC_ISR_ALRAF_Pos (8U) 7814 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 7815 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 7816 #define RTC_ISR_INIT_Pos (7U) 7817 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 7818 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 7819 #define RTC_ISR_INITF_Pos (6U) 7820 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 7821 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 7822 #define RTC_ISR_RSF_Pos (5U) 7823 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 7824 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 7825 #define RTC_ISR_INITS_Pos (4U) 7826 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 7827 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 7828 #define RTC_ISR_SHPF_Pos (3U) 7829 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 7830 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 7831 #define RTC_ISR_ALRAWF_Pos (0U) 7832 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 7833 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 7834 7835 /******************** Bits definition for RTC_PRER register ****************/ 7836 #define RTC_PRER_PREDIV_A_Pos (16U) 7837 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 7838 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 7839 #define RTC_PRER_PREDIV_S_Pos (0U) 7840 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 7841 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 7842 7843 /******************** Bits definition for RTC_ALRMAR register **************/ 7844 #define RTC_ALRMAR_MSK4_Pos (31U) 7845 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 7846 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 7847 #define RTC_ALRMAR_WDSEL_Pos (30U) 7848 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 7849 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 7850 #define RTC_ALRMAR_DT_Pos (28U) 7851 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 7852 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 7853 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 7854 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 7855 #define RTC_ALRMAR_DU_Pos (24U) 7856 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 7857 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 7858 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 7859 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 7860 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 7861 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 7862 #define RTC_ALRMAR_MSK3_Pos (23U) 7863 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 7864 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 7865 #define RTC_ALRMAR_PM_Pos (22U) 7866 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 7867 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 7868 #define RTC_ALRMAR_HT_Pos (20U) 7869 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 7870 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 7871 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 7872 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 7873 #define RTC_ALRMAR_HU_Pos (16U) 7874 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 7875 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 7876 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 7877 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 7878 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 7879 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 7880 #define RTC_ALRMAR_MSK2_Pos (15U) 7881 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 7882 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 7883 #define RTC_ALRMAR_MNT_Pos (12U) 7884 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 7885 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 7886 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 7887 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 7888 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 7889 #define RTC_ALRMAR_MNU_Pos (8U) 7890 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 7891 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 7892 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 7893 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 7894 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 7895 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 7896 #define RTC_ALRMAR_MSK1_Pos (7U) 7897 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 7898 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 7899 #define RTC_ALRMAR_ST_Pos (4U) 7900 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 7901 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 7902 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 7903 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 7904 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 7905 #define RTC_ALRMAR_SU_Pos (0U) 7906 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 7907 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 7908 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 7909 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 7910 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 7911 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 7912 7913 /******************** Bits definition for RTC_WPR register *****************/ 7914 #define RTC_WPR_KEY_Pos (0U) 7915 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 7916 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 7917 7918 /******************** Bits definition for RTC_SSR register *****************/ 7919 #define RTC_SSR_SS_Pos (0U) 7920 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 7921 #define RTC_SSR_SS RTC_SSR_SS_Msk 7922 7923 /******************** Bits definition for RTC_SHIFTR register **************/ 7924 #define RTC_SHIFTR_SUBFS_Pos (0U) 7925 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 7926 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 7927 #define RTC_SHIFTR_ADD1S_Pos (31U) 7928 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 7929 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 7930 7931 /******************** Bits definition for RTC_TSTR register ****************/ 7932 #define RTC_TSTR_PM_Pos (22U) 7933 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 7934 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 7935 #define RTC_TSTR_HT_Pos (20U) 7936 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 7937 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 7938 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 7939 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 7940 #define RTC_TSTR_HU_Pos (16U) 7941 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 7942 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 7943 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 7944 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 7945 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 7946 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 7947 #define RTC_TSTR_MNT_Pos (12U) 7948 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 7949 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 7950 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 7951 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 7952 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 7953 #define RTC_TSTR_MNU_Pos (8U) 7954 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 7955 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 7956 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 7957 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 7958 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 7959 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 7960 #define RTC_TSTR_ST_Pos (4U) 7961 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 7962 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 7963 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 7964 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 7965 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 7966 #define RTC_TSTR_SU_Pos (0U) 7967 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 7968 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 7969 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 7970 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 7971 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 7972 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 7973 7974 /******************** Bits definition for RTC_TSDR register ****************/ 7975 #define RTC_TSDR_WDU_Pos (13U) 7976 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 7977 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 7978 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 7979 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 7980 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 7981 #define RTC_TSDR_MT_Pos (12U) 7982 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 7983 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 7984 #define RTC_TSDR_MU_Pos (8U) 7985 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 7986 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 7987 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 7988 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 7989 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 7990 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 7991 #define RTC_TSDR_DT_Pos (4U) 7992 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 7993 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 7994 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 7995 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 7996 #define RTC_TSDR_DU_Pos (0U) 7997 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 7998 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 7999 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 8000 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 8001 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 8002 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 8003 8004 /******************** Bits definition for RTC_TSSSR register ***************/ 8005 #define RTC_TSSSR_SS_Pos (0U) 8006 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 8007 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 8008 8009 /******************** Bits definition for RTC_CALR register ****************/ 8010 #define RTC_CALR_CALP_Pos (15U) 8011 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 8012 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 8013 #define RTC_CALR_CALW8_Pos (14U) 8014 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 8015 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 8016 #define RTC_CALR_CALW16_Pos (13U) 8017 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 8018 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 8019 #define RTC_CALR_CALM_Pos (0U) 8020 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 8021 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 8022 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 8023 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 8024 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 8025 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 8026 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 8027 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 8028 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 8029 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 8030 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 8031 8032 /******************** Bits definition for RTC_TAFCR register ***************/ 8033 #define RTC_TAFCR_PC15MODE_Pos (23U) 8034 #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ 8035 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk 8036 #define RTC_TAFCR_PC15VALUE_Pos (22U) 8037 #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ 8038 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk 8039 #define RTC_TAFCR_PC14MODE_Pos (21U) 8040 #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ 8041 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk 8042 #define RTC_TAFCR_PC14VALUE_Pos (20U) 8043 #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ 8044 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk 8045 #define RTC_TAFCR_PC13MODE_Pos (19U) 8046 #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ 8047 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk 8048 #define RTC_TAFCR_PC13VALUE_Pos (18U) 8049 #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ 8050 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk 8051 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 8052 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 8053 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 8054 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 8055 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 8056 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 8057 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 8058 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 8059 #define RTC_TAFCR_TAMPFLT_Pos (11U) 8060 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 8061 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 8062 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 8063 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 8064 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 8065 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 8066 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 8067 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 8068 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 8069 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 8070 #define RTC_TAFCR_TAMPTS_Pos (7U) 8071 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 8072 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 8073 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 8074 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 8075 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 8076 #define RTC_TAFCR_TAMP2E_Pos (3U) 8077 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 8078 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 8079 #define RTC_TAFCR_TAMPIE_Pos (2U) 8080 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 8081 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 8082 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 8083 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 8084 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 8085 #define RTC_TAFCR_TAMP1E_Pos (0U) 8086 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 8087 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 8088 8089 /* Reference defines */ 8090 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 8091 8092 /******************** Bits definition for RTC_ALRMASSR register ************/ 8093 #define RTC_ALRMASSR_MASKSS_Pos (24U) 8094 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 8095 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 8096 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 8097 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 8098 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 8099 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 8100 #define RTC_ALRMASSR_SS_Pos (0U) 8101 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 8102 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 8103 8104 /******************** Bits definition for RTC_BKP0R register ***************/ 8105 #define RTC_BKP0R_Pos (0U) 8106 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 8107 #define RTC_BKP0R RTC_BKP0R_Msk 8108 8109 /******************** Bits definition for RTC_BKP1R register ***************/ 8110 #define RTC_BKP1R_Pos (0U) 8111 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 8112 #define RTC_BKP1R RTC_BKP1R_Msk 8113 8114 /******************** Bits definition for RTC_BKP2R register ***************/ 8115 #define RTC_BKP2R_Pos (0U) 8116 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 8117 #define RTC_BKP2R RTC_BKP2R_Msk 8118 8119 /******************** Bits definition for RTC_BKP3R register ***************/ 8120 #define RTC_BKP3R_Pos (0U) 8121 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 8122 #define RTC_BKP3R RTC_BKP3R_Msk 8123 8124 /******************** Bits definition for RTC_BKP4R register ***************/ 8125 #define RTC_BKP4R_Pos (0U) 8126 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 8127 #define RTC_BKP4R RTC_BKP4R_Msk 8128 8129 /******************** Number of backup registers ******************************/ 8130 #define RTC_BKP_NUMBER 0x00000005U 8131 8132 /*****************************************************************************/ 8133 /* */ 8134 /* Serial Peripheral Interface (SPI) */ 8135 /* */ 8136 /*****************************************************************************/ 8137 8138 /* 8139 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 8140 */ 8141 #define SPI_I2S_SUPPORT /*!< I2S support */ 8142 8143 /******************* Bit definition for SPI_CR1 register *******************/ 8144 #define SPI_CR1_CPHA_Pos (0U) 8145 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 8146 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 8147 #define SPI_CR1_CPOL_Pos (1U) 8148 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 8149 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 8150 #define SPI_CR1_MSTR_Pos (2U) 8151 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 8152 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 8153 #define SPI_CR1_BR_Pos (3U) 8154 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 8155 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 8156 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 8157 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 8158 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 8159 #define SPI_CR1_SPE_Pos (6U) 8160 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 8161 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 8162 #define SPI_CR1_LSBFIRST_Pos (7U) 8163 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 8164 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 8165 #define SPI_CR1_SSI_Pos (8U) 8166 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 8167 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 8168 #define SPI_CR1_SSM_Pos (9U) 8169 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 8170 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 8171 #define SPI_CR1_RXONLY_Pos (10U) 8172 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 8173 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 8174 #define SPI_CR1_CRCL_Pos (11U) 8175 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 8176 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 8177 #define SPI_CR1_CRCNEXT_Pos (12U) 8178 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 8179 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 8180 #define SPI_CR1_CRCEN_Pos (13U) 8181 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 8182 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 8183 #define SPI_CR1_BIDIOE_Pos (14U) 8184 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 8185 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 8186 #define SPI_CR1_BIDIMODE_Pos (15U) 8187 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 8188 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 8189 8190 /******************* Bit definition for SPI_CR2 register *******************/ 8191 #define SPI_CR2_RXDMAEN_Pos (0U) 8192 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 8193 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 8194 #define SPI_CR2_TXDMAEN_Pos (1U) 8195 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 8196 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 8197 #define SPI_CR2_SSOE_Pos (2U) 8198 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 8199 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 8200 #define SPI_CR2_NSSP_Pos (3U) 8201 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 8202 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 8203 #define SPI_CR2_FRF_Pos (4U) 8204 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 8205 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 8206 #define SPI_CR2_ERRIE_Pos (5U) 8207 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 8208 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 8209 #define SPI_CR2_RXNEIE_Pos (6U) 8210 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 8211 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 8212 #define SPI_CR2_TXEIE_Pos (7U) 8213 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 8214 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 8215 #define SPI_CR2_DS_Pos (8U) 8216 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 8217 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 8218 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 8219 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 8220 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 8221 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 8222 #define SPI_CR2_FRXTH_Pos (12U) 8223 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 8224 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 8225 #define SPI_CR2_LDMARX_Pos (13U) 8226 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 8227 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 8228 #define SPI_CR2_LDMATX_Pos (14U) 8229 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 8230 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 8231 8232 /******************** Bit definition for SPI_SR register *******************/ 8233 #define SPI_SR_RXNE_Pos (0U) 8234 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 8235 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 8236 #define SPI_SR_TXE_Pos (1U) 8237 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 8238 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 8239 #define SPI_SR_CHSIDE_Pos (2U) 8240 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 8241 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 8242 #define SPI_SR_UDR_Pos (3U) 8243 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 8244 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 8245 #define SPI_SR_CRCERR_Pos (4U) 8246 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 8247 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 8248 #define SPI_SR_MODF_Pos (5U) 8249 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 8250 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 8251 #define SPI_SR_OVR_Pos (6U) 8252 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 8253 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 8254 #define SPI_SR_BSY_Pos (7U) 8255 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 8256 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 8257 #define SPI_SR_FRE_Pos (8U) 8258 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 8259 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 8260 #define SPI_SR_FRLVL_Pos (9U) 8261 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 8262 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 8263 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 8264 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 8265 #define SPI_SR_FTLVL_Pos (11U) 8266 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 8267 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 8268 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 8269 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 8270 8271 /******************** Bit definition for SPI_DR register *******************/ 8272 #define SPI_DR_DR_Pos (0U) 8273 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ 8274 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 8275 8276 /******************* Bit definition for SPI_CRCPR register *****************/ 8277 #define SPI_CRCPR_CRCPOLY_Pos (0U) 8278 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */ 8279 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 8280 8281 /****************** Bit definition for SPI_RXCRCR register *****************/ 8282 #define SPI_RXCRCR_RXCRC_Pos (0U) 8283 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */ 8284 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 8285 8286 /****************** Bit definition for SPI_TXCRCR register *****************/ 8287 #define SPI_TXCRCR_TXCRC_Pos (0U) 8288 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */ 8289 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 8290 8291 /****************** Bit definition for SPI_I2SCFGR register ****************/ 8292 #define SPI_I2SCFGR_CHLEN_Pos (0U) 8293 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 8294 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 8295 #define SPI_I2SCFGR_DATLEN_Pos (1U) 8296 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 8297 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 8298 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 8299 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 8300 #define SPI_I2SCFGR_CKPOL_Pos (3U) 8301 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 8302 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 8303 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 8304 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 8305 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 8306 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 8307 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 8308 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 8309 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 8310 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 8311 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 8312 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 8313 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 8314 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 8315 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 8316 #define SPI_I2SCFGR_I2SE_Pos (10U) 8317 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 8318 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 8319 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 8320 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 8321 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 8322 8323 /****************** Bit definition for SPI_I2SPR register ******************/ 8324 #define SPI_I2SPR_I2SDIV_Pos (0U) 8325 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 8326 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 8327 #define SPI_I2SPR_ODD_Pos (8U) 8328 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 8329 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 8330 #define SPI_I2SPR_MCKOE_Pos (9U) 8331 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 8332 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 8333 8334 /*****************************************************************************/ 8335 /* */ 8336 /* System Configuration (SYSCFG) */ 8337 /* */ 8338 /*****************************************************************************/ 8339 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 8340 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 8341 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 8342 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 8343 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 8344 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 8345 #define SYSCFG_CFGR1_PA11_PA12_RMP_Pos (4U) 8346 #define SYSCFG_CFGR1_PA11_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_PA12_RMP_Pos) /*!< 0x00000010 */ 8347 #define SYSCFG_CFGR1_PA11_PA12_RMP SYSCFG_CFGR1_PA11_PA12_RMP_Msk /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages */ 8348 8349 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U) 8350 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */ 8351 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ 8352 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U) 8353 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */ 8354 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */ 8355 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U) 8356 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */ 8357 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */ 8358 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U) 8359 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */ 8360 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */ 8361 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) 8362 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ 8363 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ 8364 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) 8365 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ 8366 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ 8367 8368 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U) 8369 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */ 8370 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */ 8371 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U) 8372 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */ 8373 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */ 8374 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U) 8375 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */ 8376 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */ 8377 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U) 8378 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */ 8379 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */ 8380 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U) 8381 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */ 8382 #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ 8383 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Pos (21U) 8384 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C2_Pos) /*!< 0x00200000 */ 8385 #define SYSCFG_CFGR1_I2C_FMP_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2_Msk /*!< Enable I2C2 Fast mode plus */ 8386 #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U) 8387 #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */ 8388 #define SYSCFG_CFGR1_I2C_FMP_PA9 SYSCFG_CFGR1_I2C_FMP_PA9_Msk /*!< Enable Fast Mode Plus on PA9 */ 8389 #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U) 8390 #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */ 8391 #define SYSCFG_CFGR1_I2C_FMP_PA10 SYSCFG_CFGR1_I2C_FMP_PA10_Msk /*!< Enable Fast Mode Plus on PA10 */ 8392 8393 /***************** Bit definition for SYSCFG_EXTICR1 register **************/ 8394 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 8395 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 8396 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 8397 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 8398 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 8399 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 8400 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 8401 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 8402 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 8403 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 8404 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 8405 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 8406 8407 /** 8408 * @brief EXTI0 configuration 8409 */ 8410 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 8411 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 8412 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 8413 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 8414 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ 8415 8416 /** 8417 * @brief EXTI1 configuration 8418 */ 8419 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 8420 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 8421 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 8422 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 8423 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ 8424 8425 /** 8426 * @brief EXTI2 configuration 8427 */ 8428 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 8429 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 8430 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 8431 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 8432 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ 8433 8434 /** 8435 * @brief EXTI3 configuration 8436 */ 8437 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 8438 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 8439 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 8440 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 8441 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */ 8442 8443 /***************** Bit definition for SYSCFG_EXTICR2 register **************/ 8444 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 8445 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 8446 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 8447 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 8448 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 8449 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 8450 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 8451 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 8452 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 8453 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 8454 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 8455 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 8456 8457 /** 8458 * @brief EXTI4 configuration 8459 */ 8460 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 8461 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 8462 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 8463 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 8464 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ 8465 8466 /** 8467 * @brief EXTI5 configuration 8468 */ 8469 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 8470 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 8471 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 8472 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 8473 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ 8474 8475 /** 8476 * @brief EXTI6 configuration 8477 */ 8478 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 8479 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 8480 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 8481 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 8482 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ 8483 8484 /** 8485 * @brief EXTI7 configuration 8486 */ 8487 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 8488 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 8489 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 8490 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 8491 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */ 8492 8493 /***************** Bit definition for SYSCFG_EXTICR3 register **************/ 8494 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 8495 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 8496 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 8497 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 8498 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 8499 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 8500 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 8501 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 8502 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 8503 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 8504 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 8505 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 8506 8507 /** 8508 * @brief EXTI8 configuration 8509 */ 8510 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 8511 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 8512 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 8513 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 8514 8515 8516 /** 8517 * @brief EXTI9 configuration 8518 */ 8519 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 8520 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 8521 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 8522 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 8523 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ 8524 8525 /** 8526 * @brief EXTI10 configuration 8527 */ 8528 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 8529 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 8530 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 8531 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 8532 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ 8533 8534 /** 8535 * @brief EXTI11 configuration 8536 */ 8537 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 8538 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 8539 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 8540 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 8541 8542 /***************** Bit definition for SYSCFG_EXTICR4 register **************/ 8543 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 8544 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 8545 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 8546 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 8547 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 8548 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 8549 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 8550 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 8551 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 8552 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 8553 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 8554 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 8555 8556 /** 8557 * @brief EXTI12 configuration 8558 */ 8559 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 8560 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 8561 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 8562 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 8563 8564 /** 8565 * @brief EXTI13 configuration 8566 */ 8567 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 8568 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 8569 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 8570 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 8571 8572 /** 8573 * @brief EXTI14 configuration 8574 */ 8575 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 8576 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 8577 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 8578 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 8579 8580 /** 8581 * @brief EXTI15 configuration 8582 */ 8583 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 8584 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 8585 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 8586 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 8587 8588 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 8589 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) 8590 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ 8591 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ 8592 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) 8593 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ 8594 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ 8595 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U) 8596 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */ 8597 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */ 8598 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ 8599 8600 /*****************************************************************************/ 8601 /* */ 8602 /* Timers (TIM) */ 8603 /* */ 8604 /*****************************************************************************/ 8605 /******************* Bit definition for TIM_CR1 register *******************/ 8606 #define TIM_CR1_CEN_Pos (0U) 8607 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 8608 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 8609 #define TIM_CR1_UDIS_Pos (1U) 8610 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 8611 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 8612 #define TIM_CR1_URS_Pos (2U) 8613 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 8614 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 8615 #define TIM_CR1_OPM_Pos (3U) 8616 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 8617 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 8618 #define TIM_CR1_DIR_Pos (4U) 8619 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 8620 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 8621 8622 #define TIM_CR1_CMS_Pos (5U) 8623 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 8624 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 8625 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 8626 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 8627 8628 #define TIM_CR1_ARPE_Pos (7U) 8629 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 8630 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 8631 8632 #define TIM_CR1_CKD_Pos (8U) 8633 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 8634 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 8635 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 8636 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 8637 8638 /******************* Bit definition for TIM_CR2 register *******************/ 8639 #define TIM_CR2_CCPC_Pos (0U) 8640 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 8641 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 8642 #define TIM_CR2_CCUS_Pos (2U) 8643 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 8644 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 8645 #define TIM_CR2_CCDS_Pos (3U) 8646 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 8647 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 8648 8649 #define TIM_CR2_MMS_Pos (4U) 8650 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 8651 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 8652 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 8653 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 8654 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 8655 8656 #define TIM_CR2_TI1S_Pos (7U) 8657 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 8658 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 8659 #define TIM_CR2_OIS1_Pos (8U) 8660 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 8661 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 8662 #define TIM_CR2_OIS1N_Pos (9U) 8663 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 8664 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 8665 #define TIM_CR2_OIS2_Pos (10U) 8666 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 8667 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 8668 #define TIM_CR2_OIS2N_Pos (11U) 8669 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 8670 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 8671 #define TIM_CR2_OIS3_Pos (12U) 8672 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 8673 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 8674 #define TIM_CR2_OIS3N_Pos (13U) 8675 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 8676 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 8677 #define TIM_CR2_OIS4_Pos (14U) 8678 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 8679 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 8680 8681 /******************* Bit definition for TIM_SMCR register ******************/ 8682 #define TIM_SMCR_SMS_Pos (0U) 8683 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 8684 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 8685 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 8686 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 8687 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 8688 8689 #define TIM_SMCR_OCCS_Pos (3U) 8690 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 8691 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 8692 8693 #define TIM_SMCR_TS_Pos (4U) 8694 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 8695 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 8696 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 8697 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 8698 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 8699 8700 #define TIM_SMCR_MSM_Pos (7U) 8701 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 8702 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 8703 8704 #define TIM_SMCR_ETF_Pos (8U) 8705 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 8706 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 8707 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 8708 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 8709 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 8710 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 8711 8712 #define TIM_SMCR_ETPS_Pos (12U) 8713 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 8714 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 8715 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 8716 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 8717 8718 #define TIM_SMCR_ECE_Pos (14U) 8719 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 8720 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 8721 #define TIM_SMCR_ETP_Pos (15U) 8722 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 8723 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 8724 8725 /******************* Bit definition for TIM_DIER register ******************/ 8726 #define TIM_DIER_UIE_Pos (0U) 8727 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 8728 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 8729 #define TIM_DIER_CC1IE_Pos (1U) 8730 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 8731 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 8732 #define TIM_DIER_CC2IE_Pos (2U) 8733 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 8734 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 8735 #define TIM_DIER_CC3IE_Pos (3U) 8736 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 8737 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 8738 #define TIM_DIER_CC4IE_Pos (4U) 8739 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 8740 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 8741 #define TIM_DIER_COMIE_Pos (5U) 8742 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 8743 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 8744 #define TIM_DIER_TIE_Pos (6U) 8745 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 8746 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 8747 #define TIM_DIER_BIE_Pos (7U) 8748 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 8749 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 8750 #define TIM_DIER_UDE_Pos (8U) 8751 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 8752 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 8753 #define TIM_DIER_CC1DE_Pos (9U) 8754 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 8755 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 8756 #define TIM_DIER_CC2DE_Pos (10U) 8757 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 8758 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 8759 #define TIM_DIER_CC3DE_Pos (11U) 8760 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 8761 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 8762 #define TIM_DIER_CC4DE_Pos (12U) 8763 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 8764 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 8765 #define TIM_DIER_COMDE_Pos (13U) 8766 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 8767 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 8768 #define TIM_DIER_TDE_Pos (14U) 8769 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 8770 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 8771 8772 /******************** Bit definition for TIM_SR register *******************/ 8773 #define TIM_SR_UIF_Pos (0U) 8774 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 8775 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 8776 #define TIM_SR_CC1IF_Pos (1U) 8777 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 8778 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 8779 #define TIM_SR_CC2IF_Pos (2U) 8780 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 8781 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 8782 #define TIM_SR_CC3IF_Pos (3U) 8783 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 8784 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 8785 #define TIM_SR_CC4IF_Pos (4U) 8786 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 8787 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 8788 #define TIM_SR_COMIF_Pos (5U) 8789 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 8790 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 8791 #define TIM_SR_TIF_Pos (6U) 8792 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 8793 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 8794 #define TIM_SR_BIF_Pos (7U) 8795 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 8796 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 8797 #define TIM_SR_CC1OF_Pos (9U) 8798 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 8799 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 8800 #define TIM_SR_CC2OF_Pos (10U) 8801 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 8802 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 8803 #define TIM_SR_CC3OF_Pos (11U) 8804 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 8805 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 8806 #define TIM_SR_CC4OF_Pos (12U) 8807 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 8808 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 8809 8810 /******************* Bit definition for TIM_EGR register *******************/ 8811 #define TIM_EGR_UG_Pos (0U) 8812 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 8813 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 8814 #define TIM_EGR_CC1G_Pos (1U) 8815 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 8816 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 8817 #define TIM_EGR_CC2G_Pos (2U) 8818 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 8819 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 8820 #define TIM_EGR_CC3G_Pos (3U) 8821 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 8822 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 8823 #define TIM_EGR_CC4G_Pos (4U) 8824 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 8825 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 8826 #define TIM_EGR_COMG_Pos (5U) 8827 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 8828 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 8829 #define TIM_EGR_TG_Pos (6U) 8830 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 8831 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 8832 #define TIM_EGR_BG_Pos (7U) 8833 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 8834 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 8835 8836 /****************** Bit definition for TIM_CCMR1 register ******************/ 8837 #define TIM_CCMR1_CC1S_Pos (0U) 8838 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 8839 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 8840 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 8841 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 8842 8843 #define TIM_CCMR1_OC1FE_Pos (2U) 8844 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 8845 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 8846 #define TIM_CCMR1_OC1PE_Pos (3U) 8847 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 8848 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 8849 8850 #define TIM_CCMR1_OC1M_Pos (4U) 8851 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 8852 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 8853 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 8854 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 8855 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 8856 8857 #define TIM_CCMR1_OC1CE_Pos (7U) 8858 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 8859 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 8860 8861 #define TIM_CCMR1_CC2S_Pos (8U) 8862 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 8863 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 8864 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 8865 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 8866 8867 #define TIM_CCMR1_OC2FE_Pos (10U) 8868 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 8869 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 8870 #define TIM_CCMR1_OC2PE_Pos (11U) 8871 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 8872 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 8873 8874 #define TIM_CCMR1_OC2M_Pos (12U) 8875 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 8876 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 8877 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 8878 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 8879 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 8880 8881 #define TIM_CCMR1_OC2CE_Pos (15U) 8882 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 8883 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 8884 8885 /*---------------------------------------------------------------------------*/ 8886 8887 #define TIM_CCMR1_IC1PSC_Pos (2U) 8888 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 8889 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 8890 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 8891 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 8892 8893 #define TIM_CCMR1_IC1F_Pos (4U) 8894 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 8895 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 8896 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 8897 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 8898 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 8899 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 8900 8901 #define TIM_CCMR1_IC2PSC_Pos (10U) 8902 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 8903 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 8904 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 8905 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 8906 8907 #define TIM_CCMR1_IC2F_Pos (12U) 8908 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 8909 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 8910 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 8911 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 8912 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 8913 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 8914 8915 /****************** Bit definition for TIM_CCMR2 register ******************/ 8916 #define TIM_CCMR2_CC3S_Pos (0U) 8917 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 8918 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 8919 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 8920 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 8921 8922 #define TIM_CCMR2_OC3FE_Pos (2U) 8923 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 8924 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 8925 #define TIM_CCMR2_OC3PE_Pos (3U) 8926 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 8927 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 8928 8929 #define TIM_CCMR2_OC3M_Pos (4U) 8930 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 8931 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 8932 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 8933 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 8934 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 8935 8936 #define TIM_CCMR2_OC3CE_Pos (7U) 8937 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 8938 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 8939 8940 #define TIM_CCMR2_CC4S_Pos (8U) 8941 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 8942 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 8943 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 8944 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 8945 8946 #define TIM_CCMR2_OC4FE_Pos (10U) 8947 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 8948 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 8949 #define TIM_CCMR2_OC4PE_Pos (11U) 8950 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 8951 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 8952 8953 #define TIM_CCMR2_OC4M_Pos (12U) 8954 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 8955 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 8956 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 8957 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 8958 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 8959 8960 #define TIM_CCMR2_OC4CE_Pos (15U) 8961 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 8962 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 8963 8964 /*---------------------------------------------------------------------------*/ 8965 8966 #define TIM_CCMR2_IC3PSC_Pos (2U) 8967 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 8968 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 8969 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 8970 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 8971 8972 #define TIM_CCMR2_IC3F_Pos (4U) 8973 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 8974 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 8975 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 8976 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 8977 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 8978 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 8979 8980 #define TIM_CCMR2_IC4PSC_Pos (10U) 8981 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 8982 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 8983 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 8984 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 8985 8986 #define TIM_CCMR2_IC4F_Pos (12U) 8987 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 8988 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 8989 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 8990 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 8991 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 8992 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 8993 8994 /******************* Bit definition for TIM_CCER register ******************/ 8995 #define TIM_CCER_CC1E_Pos (0U) 8996 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 8997 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 8998 #define TIM_CCER_CC1P_Pos (1U) 8999 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 9000 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 9001 #define TIM_CCER_CC1NE_Pos (2U) 9002 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 9003 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 9004 #define TIM_CCER_CC1NP_Pos (3U) 9005 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 9006 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 9007 #define TIM_CCER_CC2E_Pos (4U) 9008 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 9009 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 9010 #define TIM_CCER_CC2P_Pos (5U) 9011 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 9012 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 9013 #define TIM_CCER_CC2NE_Pos (6U) 9014 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 9015 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 9016 #define TIM_CCER_CC2NP_Pos (7U) 9017 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 9018 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 9019 #define TIM_CCER_CC3E_Pos (8U) 9020 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 9021 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 9022 #define TIM_CCER_CC3P_Pos (9U) 9023 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 9024 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 9025 #define TIM_CCER_CC3NE_Pos (10U) 9026 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 9027 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 9028 #define TIM_CCER_CC3NP_Pos (11U) 9029 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 9030 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 9031 #define TIM_CCER_CC4E_Pos (12U) 9032 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 9033 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 9034 #define TIM_CCER_CC4P_Pos (13U) 9035 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 9036 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 9037 #define TIM_CCER_CC4NP_Pos (15U) 9038 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 9039 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 9040 9041 /******************* Bit definition for TIM_CNT register *******************/ 9042 #define TIM_CNT_CNT_Pos (0U) 9043 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 9044 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 9045 9046 /******************* Bit definition for TIM_PSC register *******************/ 9047 #define TIM_PSC_PSC_Pos (0U) 9048 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 9049 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 9050 9051 /******************* Bit definition for TIM_ARR register *******************/ 9052 #define TIM_ARR_ARR_Pos (0U) 9053 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 9054 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 9055 9056 /******************* Bit definition for TIM_RCR register *******************/ 9057 #define TIM_RCR_REP_Pos (0U) 9058 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 9059 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 9060 9061 /******************* Bit definition for TIM_CCR1 register ******************/ 9062 #define TIM_CCR1_CCR1_Pos (0U) 9063 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 9064 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 9065 9066 /******************* Bit definition for TIM_CCR2 register ******************/ 9067 #define TIM_CCR2_CCR2_Pos (0U) 9068 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 9069 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 9070 9071 /******************* Bit definition for TIM_CCR3 register ******************/ 9072 #define TIM_CCR3_CCR3_Pos (0U) 9073 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 9074 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 9075 9076 /******************* Bit definition for TIM_CCR4 register ******************/ 9077 #define TIM_CCR4_CCR4_Pos (0U) 9078 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 9079 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 9080 9081 /******************* Bit definition for TIM_BDTR register ******************/ 9082 #define TIM_BDTR_DTG_Pos (0U) 9083 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 9084 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 9085 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 9086 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 9087 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 9088 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 9089 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 9090 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 9091 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 9092 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 9093 9094 #define TIM_BDTR_LOCK_Pos (8U) 9095 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 9096 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 9097 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 9098 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 9099 9100 #define TIM_BDTR_OSSI_Pos (10U) 9101 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 9102 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 9103 #define TIM_BDTR_OSSR_Pos (11U) 9104 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 9105 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 9106 #define TIM_BDTR_BKE_Pos (12U) 9107 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 9108 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 9109 #define TIM_BDTR_BKP_Pos (13U) 9110 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 9111 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 9112 #define TIM_BDTR_AOE_Pos (14U) 9113 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 9114 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 9115 #define TIM_BDTR_MOE_Pos (15U) 9116 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 9117 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 9118 9119 /******************* Bit definition for TIM_DCR register *******************/ 9120 #define TIM_DCR_DBA_Pos (0U) 9121 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 9122 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 9123 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 9124 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 9125 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 9126 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 9127 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 9128 9129 #define TIM_DCR_DBL_Pos (8U) 9130 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 9131 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 9132 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 9133 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 9134 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 9135 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 9136 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 9137 9138 /******************* Bit definition for TIM_DMAR register ******************/ 9139 #define TIM_DMAR_DMAB_Pos (0U) 9140 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 9141 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 9142 9143 /******************* Bit definition for TIM14_OR register ********************/ 9144 #define TIM14_OR_TI1_RMP_Pos (0U) 9145 #define TIM14_OR_TI1_RMP_Msk (0x3UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 9146 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */ 9147 #define TIM14_OR_TI1_RMP_0 (0x1UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 9148 #define TIM14_OR_TI1_RMP_1 (0x2UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 9149 9150 /******************************************************************************/ 9151 /* */ 9152 /* Touch Sensing Controller (TSC) */ 9153 /* */ 9154 /******************************************************************************/ 9155 /******************* Bit definition for TSC_CR register *********************/ 9156 #define TSC_CR_TSCE_Pos (0U) 9157 #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ 9158 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ 9159 #define TSC_CR_START_Pos (1U) 9160 #define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */ 9161 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ 9162 #define TSC_CR_AM_Pos (2U) 9163 #define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */ 9164 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ 9165 #define TSC_CR_SYNCPOL_Pos (3U) 9166 #define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ 9167 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ 9168 #define TSC_CR_IODEF_Pos (4U) 9169 #define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ 9170 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ 9171 9172 #define TSC_CR_MCV_Pos (5U) 9173 #define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ 9174 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ 9175 #define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */ 9176 #define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */ 9177 #define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */ 9178 9179 #define TSC_CR_PGPSC_Pos (12U) 9180 #define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ 9181 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ 9182 #define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ 9183 #define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ 9184 #define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ 9185 9186 #define TSC_CR_SSPSC_Pos (15U) 9187 #define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ 9188 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ 9189 #define TSC_CR_SSE_Pos (16U) 9190 #define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */ 9191 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ 9192 9193 #define TSC_CR_SSD_Pos (17U) 9194 #define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ 9195 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ 9196 #define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */ 9197 #define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */ 9198 #define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */ 9199 #define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */ 9200 #define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */ 9201 #define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */ 9202 #define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */ 9203 9204 #define TSC_CR_CTPL_Pos (24U) 9205 #define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ 9206 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ 9207 #define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ 9208 #define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ 9209 #define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ 9210 #define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ 9211 9212 #define TSC_CR_CTPH_Pos (28U) 9213 #define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ 9214 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ 9215 #define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ 9216 #define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ 9217 #define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ 9218 #define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ 9219 9220 /******************* Bit definition for TSC_IER register ********************/ 9221 #define TSC_IER_EOAIE_Pos (0U) 9222 #define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ 9223 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ 9224 #define TSC_IER_MCEIE_Pos (1U) 9225 #define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ 9226 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ 9227 9228 /******************* Bit definition for TSC_ICR register ********************/ 9229 #define TSC_ICR_EOAIC_Pos (0U) 9230 #define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ 9231 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ 9232 #define TSC_ICR_MCEIC_Pos (1U) 9233 #define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ 9234 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ 9235 9236 /******************* Bit definition for TSC_ISR register ********************/ 9237 #define TSC_ISR_EOAF_Pos (0U) 9238 #define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ 9239 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ 9240 #define TSC_ISR_MCEF_Pos (1U) 9241 #define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ 9242 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ 9243 9244 /******************* Bit definition for TSC_IOHCR register ******************/ 9245 #define TSC_IOHCR_G1_IO1_Pos (0U) 9246 #define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ 9247 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ 9248 #define TSC_IOHCR_G1_IO2_Pos (1U) 9249 #define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ 9250 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ 9251 #define TSC_IOHCR_G1_IO3_Pos (2U) 9252 #define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ 9253 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ 9254 #define TSC_IOHCR_G1_IO4_Pos (3U) 9255 #define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ 9256 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ 9257 #define TSC_IOHCR_G2_IO1_Pos (4U) 9258 #define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ 9259 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ 9260 #define TSC_IOHCR_G2_IO2_Pos (5U) 9261 #define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ 9262 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ 9263 #define TSC_IOHCR_G2_IO3_Pos (6U) 9264 #define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ 9265 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ 9266 #define TSC_IOHCR_G2_IO4_Pos (7U) 9267 #define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ 9268 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ 9269 #define TSC_IOHCR_G3_IO1_Pos (8U) 9270 #define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ 9271 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ 9272 #define TSC_IOHCR_G3_IO2_Pos (9U) 9273 #define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ 9274 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ 9275 #define TSC_IOHCR_G3_IO3_Pos (10U) 9276 #define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ 9277 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ 9278 #define TSC_IOHCR_G3_IO4_Pos (11U) 9279 #define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ 9280 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ 9281 #define TSC_IOHCR_G4_IO1_Pos (12U) 9282 #define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ 9283 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ 9284 #define TSC_IOHCR_G4_IO2_Pos (13U) 9285 #define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ 9286 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ 9287 #define TSC_IOHCR_G4_IO3_Pos (14U) 9288 #define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ 9289 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ 9290 #define TSC_IOHCR_G4_IO4_Pos (15U) 9291 #define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ 9292 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ 9293 #define TSC_IOHCR_G5_IO1_Pos (16U) 9294 #define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ 9295 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ 9296 #define TSC_IOHCR_G5_IO2_Pos (17U) 9297 #define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ 9298 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ 9299 #define TSC_IOHCR_G5_IO3_Pos (18U) 9300 #define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ 9301 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ 9302 #define TSC_IOHCR_G5_IO4_Pos (19U) 9303 #define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ 9304 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ 9305 #define TSC_IOHCR_G6_IO1_Pos (20U) 9306 #define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ 9307 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ 9308 #define TSC_IOHCR_G6_IO2_Pos (21U) 9309 #define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ 9310 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ 9311 #define TSC_IOHCR_G6_IO3_Pos (22U) 9312 #define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ 9313 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ 9314 #define TSC_IOHCR_G6_IO4_Pos (23U) 9315 #define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ 9316 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ 9317 #define TSC_IOHCR_G7_IO1_Pos (24U) 9318 #define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ 9319 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ 9320 #define TSC_IOHCR_G7_IO2_Pos (25U) 9321 #define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ 9322 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ 9323 #define TSC_IOHCR_G7_IO3_Pos (26U) 9324 #define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ 9325 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ 9326 #define TSC_IOHCR_G7_IO4_Pos (27U) 9327 #define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ 9328 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ 9329 #define TSC_IOHCR_G8_IO1_Pos (28U) 9330 #define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */ 9331 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ 9332 #define TSC_IOHCR_G8_IO2_Pos (29U) 9333 #define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */ 9334 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ 9335 #define TSC_IOHCR_G8_IO3_Pos (30U) 9336 #define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */ 9337 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ 9338 #define TSC_IOHCR_G8_IO4_Pos (31U) 9339 #define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */ 9340 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ 9341 9342 /******************* Bit definition for TSC_IOASCR register *****************/ 9343 #define TSC_IOASCR_G1_IO1_Pos (0U) 9344 #define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ 9345 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ 9346 #define TSC_IOASCR_G1_IO2_Pos (1U) 9347 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ 9348 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ 9349 #define TSC_IOASCR_G1_IO3_Pos (2U) 9350 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ 9351 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ 9352 #define TSC_IOASCR_G1_IO4_Pos (3U) 9353 #define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ 9354 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ 9355 #define TSC_IOASCR_G2_IO1_Pos (4U) 9356 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ 9357 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ 9358 #define TSC_IOASCR_G2_IO2_Pos (5U) 9359 #define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ 9360 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ 9361 #define TSC_IOASCR_G2_IO3_Pos (6U) 9362 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ 9363 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ 9364 #define TSC_IOASCR_G2_IO4_Pos (7U) 9365 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ 9366 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ 9367 #define TSC_IOASCR_G3_IO1_Pos (8U) 9368 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ 9369 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ 9370 #define TSC_IOASCR_G3_IO2_Pos (9U) 9371 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ 9372 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ 9373 #define TSC_IOASCR_G3_IO3_Pos (10U) 9374 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ 9375 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ 9376 #define TSC_IOASCR_G3_IO4_Pos (11U) 9377 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ 9378 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ 9379 #define TSC_IOASCR_G4_IO1_Pos (12U) 9380 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ 9381 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ 9382 #define TSC_IOASCR_G4_IO2_Pos (13U) 9383 #define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ 9384 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ 9385 #define TSC_IOASCR_G4_IO3_Pos (14U) 9386 #define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ 9387 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ 9388 #define TSC_IOASCR_G4_IO4_Pos (15U) 9389 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ 9390 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ 9391 #define TSC_IOASCR_G5_IO1_Pos (16U) 9392 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ 9393 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ 9394 #define TSC_IOASCR_G5_IO2_Pos (17U) 9395 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ 9396 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ 9397 #define TSC_IOASCR_G5_IO3_Pos (18U) 9398 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ 9399 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ 9400 #define TSC_IOASCR_G5_IO4_Pos (19U) 9401 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ 9402 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ 9403 #define TSC_IOASCR_G6_IO1_Pos (20U) 9404 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ 9405 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ 9406 #define TSC_IOASCR_G6_IO2_Pos (21U) 9407 #define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ 9408 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ 9409 #define TSC_IOASCR_G6_IO3_Pos (22U) 9410 #define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ 9411 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ 9412 #define TSC_IOASCR_G6_IO4_Pos (23U) 9413 #define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ 9414 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ 9415 #define TSC_IOASCR_G7_IO1_Pos (24U) 9416 #define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ 9417 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ 9418 #define TSC_IOASCR_G7_IO2_Pos (25U) 9419 #define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ 9420 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ 9421 #define TSC_IOASCR_G7_IO3_Pos (26U) 9422 #define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ 9423 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ 9424 #define TSC_IOASCR_G7_IO4_Pos (27U) 9425 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ 9426 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ 9427 #define TSC_IOASCR_G8_IO1_Pos (28U) 9428 #define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */ 9429 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */ 9430 #define TSC_IOASCR_G8_IO2_Pos (29U) 9431 #define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */ 9432 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */ 9433 #define TSC_IOASCR_G8_IO3_Pos (30U) 9434 #define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */ 9435 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */ 9436 #define TSC_IOASCR_G8_IO4_Pos (31U) 9437 #define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */ 9438 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */ 9439 9440 /******************* Bit definition for TSC_IOSCR register ******************/ 9441 #define TSC_IOSCR_G1_IO1_Pos (0U) 9442 #define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ 9443 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ 9444 #define TSC_IOSCR_G1_IO2_Pos (1U) 9445 #define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ 9446 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ 9447 #define TSC_IOSCR_G1_IO3_Pos (2U) 9448 #define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ 9449 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ 9450 #define TSC_IOSCR_G1_IO4_Pos (3U) 9451 #define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ 9452 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ 9453 #define TSC_IOSCR_G2_IO1_Pos (4U) 9454 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ 9455 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ 9456 #define TSC_IOSCR_G2_IO2_Pos (5U) 9457 #define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ 9458 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ 9459 #define TSC_IOSCR_G2_IO3_Pos (6U) 9460 #define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ 9461 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ 9462 #define TSC_IOSCR_G2_IO4_Pos (7U) 9463 #define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ 9464 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ 9465 #define TSC_IOSCR_G3_IO1_Pos (8U) 9466 #define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ 9467 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ 9468 #define TSC_IOSCR_G3_IO2_Pos (9U) 9469 #define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ 9470 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ 9471 #define TSC_IOSCR_G3_IO3_Pos (10U) 9472 #define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ 9473 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ 9474 #define TSC_IOSCR_G3_IO4_Pos (11U) 9475 #define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ 9476 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ 9477 #define TSC_IOSCR_G4_IO1_Pos (12U) 9478 #define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ 9479 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ 9480 #define TSC_IOSCR_G4_IO2_Pos (13U) 9481 #define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ 9482 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ 9483 #define TSC_IOSCR_G4_IO3_Pos (14U) 9484 #define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ 9485 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ 9486 #define TSC_IOSCR_G4_IO4_Pos (15U) 9487 #define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ 9488 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ 9489 #define TSC_IOSCR_G5_IO1_Pos (16U) 9490 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ 9491 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ 9492 #define TSC_IOSCR_G5_IO2_Pos (17U) 9493 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ 9494 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ 9495 #define TSC_IOSCR_G5_IO3_Pos (18U) 9496 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ 9497 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ 9498 #define TSC_IOSCR_G5_IO4_Pos (19U) 9499 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ 9500 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ 9501 #define TSC_IOSCR_G6_IO1_Pos (20U) 9502 #define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ 9503 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ 9504 #define TSC_IOSCR_G6_IO2_Pos (21U) 9505 #define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ 9506 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ 9507 #define TSC_IOSCR_G6_IO3_Pos (22U) 9508 #define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ 9509 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ 9510 #define TSC_IOSCR_G6_IO4_Pos (23U) 9511 #define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ 9512 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ 9513 #define TSC_IOSCR_G7_IO1_Pos (24U) 9514 #define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ 9515 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ 9516 #define TSC_IOSCR_G7_IO2_Pos (25U) 9517 #define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ 9518 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ 9519 #define TSC_IOSCR_G7_IO3_Pos (26U) 9520 #define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ 9521 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ 9522 #define TSC_IOSCR_G7_IO4_Pos (27U) 9523 #define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ 9524 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ 9525 #define TSC_IOSCR_G8_IO1_Pos (28U) 9526 #define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */ 9527 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */ 9528 #define TSC_IOSCR_G8_IO2_Pos (29U) 9529 #define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */ 9530 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */ 9531 #define TSC_IOSCR_G8_IO3_Pos (30U) 9532 #define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */ 9533 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */ 9534 #define TSC_IOSCR_G8_IO4_Pos (31U) 9535 #define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */ 9536 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */ 9537 9538 /******************* Bit definition for TSC_IOCCR register ******************/ 9539 #define TSC_IOCCR_G1_IO1_Pos (0U) 9540 #define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ 9541 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ 9542 #define TSC_IOCCR_G1_IO2_Pos (1U) 9543 #define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ 9544 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ 9545 #define TSC_IOCCR_G1_IO3_Pos (2U) 9546 #define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ 9547 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ 9548 #define TSC_IOCCR_G1_IO4_Pos (3U) 9549 #define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ 9550 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ 9551 #define TSC_IOCCR_G2_IO1_Pos (4U) 9552 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ 9553 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ 9554 #define TSC_IOCCR_G2_IO2_Pos (5U) 9555 #define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ 9556 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ 9557 #define TSC_IOCCR_G2_IO3_Pos (6U) 9558 #define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ 9559 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ 9560 #define TSC_IOCCR_G2_IO4_Pos (7U) 9561 #define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ 9562 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ 9563 #define TSC_IOCCR_G3_IO1_Pos (8U) 9564 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ 9565 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ 9566 #define TSC_IOCCR_G3_IO2_Pos (9U) 9567 #define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ 9568 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ 9569 #define TSC_IOCCR_G3_IO3_Pos (10U) 9570 #define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ 9571 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ 9572 #define TSC_IOCCR_G3_IO4_Pos (11U) 9573 #define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ 9574 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ 9575 #define TSC_IOCCR_G4_IO1_Pos (12U) 9576 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ 9577 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ 9578 #define TSC_IOCCR_G4_IO2_Pos (13U) 9579 #define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ 9580 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ 9581 #define TSC_IOCCR_G4_IO3_Pos (14U) 9582 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ 9583 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ 9584 #define TSC_IOCCR_G4_IO4_Pos (15U) 9585 #define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ 9586 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ 9587 #define TSC_IOCCR_G5_IO1_Pos (16U) 9588 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ 9589 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ 9590 #define TSC_IOCCR_G5_IO2_Pos (17U) 9591 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ 9592 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ 9593 #define TSC_IOCCR_G5_IO3_Pos (18U) 9594 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ 9595 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ 9596 #define TSC_IOCCR_G5_IO4_Pos (19U) 9597 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ 9598 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ 9599 #define TSC_IOCCR_G6_IO1_Pos (20U) 9600 #define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ 9601 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ 9602 #define TSC_IOCCR_G6_IO2_Pos (21U) 9603 #define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ 9604 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ 9605 #define TSC_IOCCR_G6_IO3_Pos (22U) 9606 #define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ 9607 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ 9608 #define TSC_IOCCR_G6_IO4_Pos (23U) 9609 #define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ 9610 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ 9611 #define TSC_IOCCR_G7_IO1_Pos (24U) 9612 #define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ 9613 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ 9614 #define TSC_IOCCR_G7_IO2_Pos (25U) 9615 #define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ 9616 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ 9617 #define TSC_IOCCR_G7_IO3_Pos (26U) 9618 #define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ 9619 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ 9620 #define TSC_IOCCR_G7_IO4_Pos (27U) 9621 #define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ 9622 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ 9623 #define TSC_IOCCR_G8_IO1_Pos (28U) 9624 #define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */ 9625 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */ 9626 #define TSC_IOCCR_G8_IO2_Pos (29U) 9627 #define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */ 9628 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */ 9629 #define TSC_IOCCR_G8_IO3_Pos (30U) 9630 #define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */ 9631 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */ 9632 #define TSC_IOCCR_G8_IO4_Pos (31U) 9633 #define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */ 9634 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */ 9635 9636 /******************* Bit definition for TSC_IOGCSR register *****************/ 9637 #define TSC_IOGCSR_G1E_Pos (0U) 9638 #define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ 9639 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ 9640 #define TSC_IOGCSR_G2E_Pos (1U) 9641 #define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ 9642 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ 9643 #define TSC_IOGCSR_G3E_Pos (2U) 9644 #define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ 9645 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ 9646 #define TSC_IOGCSR_G4E_Pos (3U) 9647 #define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ 9648 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ 9649 #define TSC_IOGCSR_G5E_Pos (4U) 9650 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ 9651 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ 9652 #define TSC_IOGCSR_G6E_Pos (5U) 9653 #define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ 9654 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ 9655 #define TSC_IOGCSR_G7E_Pos (6U) 9656 #define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ 9657 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ 9658 #define TSC_IOGCSR_G8E_Pos (7U) 9659 #define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */ 9660 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */ 9661 #define TSC_IOGCSR_G1S_Pos (16U) 9662 #define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ 9663 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ 9664 #define TSC_IOGCSR_G2S_Pos (17U) 9665 #define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ 9666 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ 9667 #define TSC_IOGCSR_G3S_Pos (18U) 9668 #define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ 9669 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ 9670 #define TSC_IOGCSR_G4S_Pos (19U) 9671 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ 9672 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ 9673 #define TSC_IOGCSR_G5S_Pos (20U) 9674 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ 9675 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ 9676 #define TSC_IOGCSR_G6S_Pos (21U) 9677 #define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ 9678 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ 9679 #define TSC_IOGCSR_G7S_Pos (22U) 9680 #define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ 9681 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ 9682 #define TSC_IOGCSR_G8S_Pos (23U) 9683 #define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */ 9684 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */ 9685 9686 /******************* Bit definition for TSC_IOGXCR register *****************/ 9687 #define TSC_IOGXCR_CNT_Pos (0U) 9688 #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ 9689 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ 9690 9691 /******************************************************************************/ 9692 /* */ 9693 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 9694 /* */ 9695 /******************************************************************************/ 9696 9697 /* 9698 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 9699 */ 9700 9701 /* Support of 7 bits data length feature */ 9702 #define USART_7BITS_SUPPORT 9703 9704 /* Support of LIN feature */ 9705 #define USART_LIN_SUPPORT 9706 9707 /* Support of Smartcard feature */ 9708 #define USART_SMARTCARD_SUPPORT 9709 9710 /* Support of Irda feature */ 9711 #define USART_IRDA_SUPPORT 9712 9713 /* Support of Wake Up from Stop Mode feature */ 9714 #define USART_WUSM_SUPPORT 9715 9716 /* Support of Full Auto Baud rate feature (4 modes) activation */ 9717 #define USART_FABR_SUPPORT 9718 9719 /****************** Bit definition for USART_CR1 register *******************/ 9720 #define USART_CR1_UE_Pos (0U) 9721 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 9722 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 9723 #define USART_CR1_UESM_Pos (1U) 9724 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 9725 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 9726 #define USART_CR1_RE_Pos (2U) 9727 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 9728 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 9729 #define USART_CR1_TE_Pos (3U) 9730 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 9731 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 9732 #define USART_CR1_IDLEIE_Pos (4U) 9733 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 9734 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 9735 #define USART_CR1_RXNEIE_Pos (5U) 9736 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 9737 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 9738 #define USART_CR1_TCIE_Pos (6U) 9739 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 9740 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 9741 #define USART_CR1_TXEIE_Pos (7U) 9742 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 9743 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 9744 #define USART_CR1_PEIE_Pos (8U) 9745 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 9746 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 9747 #define USART_CR1_PS_Pos (9U) 9748 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 9749 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 9750 #define USART_CR1_PCE_Pos (10U) 9751 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 9752 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 9753 #define USART_CR1_WAKE_Pos (11U) 9754 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 9755 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 9756 #define USART_CR1_M0_Pos (12U) 9757 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 9758 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */ 9759 #define USART_CR1_MME_Pos (13U) 9760 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 9761 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 9762 #define USART_CR1_CMIE_Pos (14U) 9763 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 9764 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 9765 #define USART_CR1_OVER8_Pos (15U) 9766 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 9767 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 9768 #define USART_CR1_DEDT_Pos (16U) 9769 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 9770 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 9771 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 9772 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 9773 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 9774 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 9775 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 9776 #define USART_CR1_DEAT_Pos (21U) 9777 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 9778 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 9779 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 9780 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 9781 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 9782 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 9783 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 9784 #define USART_CR1_RTOIE_Pos (26U) 9785 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 9786 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 9787 #define USART_CR1_EOBIE_Pos (27U) 9788 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 9789 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 9790 #define USART_CR1_M1_Pos (28U) 9791 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 9792 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */ 9793 #define USART_CR1_M_Pos (12U) 9794 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 9795 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */ 9796 9797 /****************** Bit definition for USART_CR2 register *******************/ 9798 #define USART_CR2_ADDM7_Pos (4U) 9799 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 9800 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 9801 #define USART_CR2_LBDL_Pos (5U) 9802 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 9803 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 9804 #define USART_CR2_LBDIE_Pos (6U) 9805 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 9806 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 9807 #define USART_CR2_LBCL_Pos (8U) 9808 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 9809 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 9810 #define USART_CR2_CPHA_Pos (9U) 9811 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 9812 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 9813 #define USART_CR2_CPOL_Pos (10U) 9814 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 9815 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 9816 #define USART_CR2_CLKEN_Pos (11U) 9817 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 9818 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 9819 #define USART_CR2_STOP_Pos (12U) 9820 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 9821 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 9822 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 9823 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 9824 #define USART_CR2_LINEN_Pos (14U) 9825 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 9826 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 9827 #define USART_CR2_SWAP_Pos (15U) 9828 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 9829 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 9830 #define USART_CR2_RXINV_Pos (16U) 9831 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 9832 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 9833 #define USART_CR2_TXINV_Pos (17U) 9834 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 9835 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 9836 #define USART_CR2_DATAINV_Pos (18U) 9837 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 9838 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 9839 #define USART_CR2_MSBFIRST_Pos (19U) 9840 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 9841 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 9842 #define USART_CR2_ABREN_Pos (20U) 9843 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 9844 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 9845 #define USART_CR2_ABRMODE_Pos (21U) 9846 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 9847 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 9848 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 9849 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 9850 #define USART_CR2_RTOEN_Pos (23U) 9851 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 9852 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 9853 #define USART_CR2_ADD_Pos (24U) 9854 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 9855 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 9856 9857 /****************** Bit definition for USART_CR3 register *******************/ 9858 #define USART_CR3_EIE_Pos (0U) 9859 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 9860 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 9861 #define USART_CR3_IREN_Pos (1U) 9862 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 9863 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 9864 #define USART_CR3_IRLP_Pos (2U) 9865 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 9866 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 9867 #define USART_CR3_HDSEL_Pos (3U) 9868 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 9869 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 9870 #define USART_CR3_NACK_Pos (4U) 9871 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 9872 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 9873 #define USART_CR3_SCEN_Pos (5U) 9874 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 9875 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 9876 #define USART_CR3_DMAR_Pos (6U) 9877 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 9878 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 9879 #define USART_CR3_DMAT_Pos (7U) 9880 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 9881 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 9882 #define USART_CR3_RTSE_Pos (8U) 9883 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 9884 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 9885 #define USART_CR3_CTSE_Pos (9U) 9886 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 9887 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 9888 #define USART_CR3_CTSIE_Pos (10U) 9889 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 9890 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 9891 #define USART_CR3_ONEBIT_Pos (11U) 9892 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 9893 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 9894 #define USART_CR3_OVRDIS_Pos (12U) 9895 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 9896 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 9897 #define USART_CR3_DDRE_Pos (13U) 9898 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 9899 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 9900 #define USART_CR3_DEM_Pos (14U) 9901 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 9902 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 9903 #define USART_CR3_DEP_Pos (15U) 9904 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 9905 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 9906 #define USART_CR3_SCARCNT_Pos (17U) 9907 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 9908 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 9909 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 9910 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 9911 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 9912 #define USART_CR3_WUS_Pos (20U) 9913 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 9914 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 9915 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 9916 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 9917 #define USART_CR3_WUFIE_Pos (22U) 9918 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 9919 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 9920 9921 /****************** Bit definition for USART_BRR register *******************/ 9922 #define USART_BRR_DIV_FRACTION_Pos (0U) 9923 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 9924 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 9925 #define USART_BRR_DIV_MANTISSA_Pos (4U) 9926 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 9927 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 9928 9929 /****************** Bit definition for USART_GTPR register ******************/ 9930 #define USART_GTPR_PSC_Pos (0U) 9931 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 9932 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 9933 #define USART_GTPR_GT_Pos (8U) 9934 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 9935 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 9936 9937 9938 /******************* Bit definition for USART_RTOR register *****************/ 9939 #define USART_RTOR_RTO_Pos (0U) 9940 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 9941 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 9942 #define USART_RTOR_BLEN_Pos (24U) 9943 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 9944 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 9945 9946 /******************* Bit definition for USART_RQR register ******************/ 9947 #define USART_RQR_ABRRQ_Pos (0U) 9948 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 9949 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 9950 #define USART_RQR_SBKRQ_Pos (1U) 9951 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 9952 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 9953 #define USART_RQR_MMRQ_Pos (2U) 9954 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 9955 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 9956 #define USART_RQR_RXFRQ_Pos (3U) 9957 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 9958 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 9959 #define USART_RQR_TXFRQ_Pos (4U) 9960 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 9961 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 9962 9963 /******************* Bit definition for USART_ISR register ******************/ 9964 #define USART_ISR_PE_Pos (0U) 9965 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 9966 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 9967 #define USART_ISR_FE_Pos (1U) 9968 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 9969 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 9970 #define USART_ISR_NE_Pos (2U) 9971 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 9972 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 9973 #define USART_ISR_ORE_Pos (3U) 9974 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 9975 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 9976 #define USART_ISR_IDLE_Pos (4U) 9977 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 9978 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 9979 #define USART_ISR_RXNE_Pos (5U) 9980 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 9981 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 9982 #define USART_ISR_TC_Pos (6U) 9983 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 9984 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 9985 #define USART_ISR_TXE_Pos (7U) 9986 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 9987 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 9988 #define USART_ISR_LBDF_Pos (8U) 9989 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 9990 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 9991 #define USART_ISR_CTSIF_Pos (9U) 9992 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 9993 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 9994 #define USART_ISR_CTS_Pos (10U) 9995 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 9996 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 9997 #define USART_ISR_RTOF_Pos (11U) 9998 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 9999 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 10000 #define USART_ISR_EOBF_Pos (12U) 10001 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 10002 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 10003 #define USART_ISR_ABRE_Pos (14U) 10004 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 10005 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 10006 #define USART_ISR_ABRF_Pos (15U) 10007 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 10008 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 10009 #define USART_ISR_BUSY_Pos (16U) 10010 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 10011 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 10012 #define USART_ISR_CMF_Pos (17U) 10013 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 10014 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 10015 #define USART_ISR_SBKF_Pos (18U) 10016 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 10017 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 10018 #define USART_ISR_RWU_Pos (19U) 10019 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 10020 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 10021 #define USART_ISR_WUF_Pos (20U) 10022 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 10023 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 10024 #define USART_ISR_TEACK_Pos (21U) 10025 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 10026 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 10027 #define USART_ISR_REACK_Pos (22U) 10028 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 10029 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 10030 10031 /******************* Bit definition for USART_ICR register ******************/ 10032 #define USART_ICR_PECF_Pos (0U) 10033 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 10034 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 10035 #define USART_ICR_FECF_Pos (1U) 10036 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 10037 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 10038 #define USART_ICR_NCF_Pos (2U) 10039 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 10040 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 10041 #define USART_ICR_ORECF_Pos (3U) 10042 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 10043 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 10044 #define USART_ICR_IDLECF_Pos (4U) 10045 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 10046 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 10047 #define USART_ICR_TCCF_Pos (6U) 10048 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 10049 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 10050 #define USART_ICR_LBDCF_Pos (8U) 10051 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 10052 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 10053 #define USART_ICR_CTSCF_Pos (9U) 10054 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 10055 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 10056 #define USART_ICR_RTOCF_Pos (11U) 10057 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 10058 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 10059 #define USART_ICR_EOBCF_Pos (12U) 10060 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 10061 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 10062 #define USART_ICR_CMCF_Pos (17U) 10063 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 10064 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 10065 #define USART_ICR_WUCF_Pos (20U) 10066 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 10067 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 10068 10069 /******************* Bit definition for USART_RDR register ******************/ 10070 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */ 10071 10072 /******************* Bit definition for USART_TDR register ******************/ 10073 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */ 10074 10075 /******************************************************************************/ 10076 /* */ 10077 /* USB Device General registers */ 10078 /* */ 10079 /******************************************************************************/ 10080 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */ 10081 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */ 10082 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */ 10083 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */ 10084 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */ 10085 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */ 10086 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/ 10087 10088 /**************************** ISTR interrupt events *************************/ 10089 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ 10090 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ 10091 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ 10092 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ 10093 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ 10094 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ 10095 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ 10096 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ 10097 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */ 10098 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ 10099 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ 10100 10101 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 10102 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 10103 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 10104 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 10105 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 10106 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 10107 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 10108 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 10109 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */ 10110 10111 /************************* CNTR control register bits definitions ***********/ 10112 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ 10113 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ 10114 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ 10115 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ 10116 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ 10117 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ 10118 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ 10119 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ 10120 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */ 10121 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */ 10122 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ 10123 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ 10124 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ 10125 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ 10126 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ 10127 10128 /************************* BCDR control register bits definitions ***********/ 10129 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ 10130 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ 10131 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ 10132 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ 10133 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ 10134 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ 10135 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ 10136 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ 10137 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ 10138 10139 /*************************** LPM register bits definitions ******************/ 10140 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ 10141 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ 10142 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ 10143 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ 10144 10145 /******************** FNR Frame Number Register bit definitions ************/ 10146 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ 10147 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ 10148 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ 10149 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ 10150 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ 10151 10152 /******************** DADDR Device ADDRess bit definitions ****************/ 10153 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */ 10154 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */ 10155 10156 /****************************** Endpoint register *************************/ 10157 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 10158 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */ 10159 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */ 10160 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */ 10161 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */ 10162 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */ 10163 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */ 10164 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */ 10165 /* bit positions */ 10166 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ 10167 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ 10168 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ 10169 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ 10170 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ 10171 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ 10172 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ 10173 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ 10174 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ 10175 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ 10176 10177 /* EndPoint REGister MASK (no toggle fields) */ 10178 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 10179 /*!< EP_TYPE[1:0] EndPoint TYPE */ 10180 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ 10181 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ 10182 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ 10183 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ 10184 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ 10185 #define USB_EP_T_MASK (((uint16_t)(~USB_EP_T_FIELD)) & USB_EPREG_MASK) 10186 10187 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 10188 /*!< STAT_TX[1:0] STATus for TX transfer */ 10189 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ 10190 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ 10191 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ 10192 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ 10193 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ 10194 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ 10195 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 10196 /*!< STAT_RX[1:0] STATus for RX transfer */ 10197 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ 10198 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ 10199 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ 10200 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ 10201 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ 10202 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ 10203 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 10204 10205 /******************************************************************************/ 10206 /* */ 10207 /* Window WATCHDOG (WWDG) */ 10208 /* */ 10209 /******************************************************************************/ 10210 10211 /******************* Bit definition for WWDG_CR register ********************/ 10212 #define WWDG_CR_T_Pos (0U) 10213 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 10214 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 10215 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 10216 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 10217 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 10218 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 10219 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 10220 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 10221 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 10222 10223 /* Legacy defines */ 10224 #define WWDG_CR_T0 WWDG_CR_T_0 10225 #define WWDG_CR_T1 WWDG_CR_T_1 10226 #define WWDG_CR_T2 WWDG_CR_T_2 10227 #define WWDG_CR_T3 WWDG_CR_T_3 10228 #define WWDG_CR_T4 WWDG_CR_T_4 10229 #define WWDG_CR_T5 WWDG_CR_T_5 10230 #define WWDG_CR_T6 WWDG_CR_T_6 10231 10232 #define WWDG_CR_WDGA_Pos (7U) 10233 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 10234 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 10235 10236 /******************* Bit definition for WWDG_CFR register *******************/ 10237 #define WWDG_CFR_W_Pos (0U) 10238 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 10239 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 10240 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 10241 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 10242 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 10243 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 10244 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 10245 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 10246 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 10247 10248 /* Legacy defines */ 10249 #define WWDG_CFR_W0 WWDG_CFR_W_0 10250 #define WWDG_CFR_W1 WWDG_CFR_W_1 10251 #define WWDG_CFR_W2 WWDG_CFR_W_2 10252 #define WWDG_CFR_W3 WWDG_CFR_W_3 10253 #define WWDG_CFR_W4 WWDG_CFR_W_4 10254 #define WWDG_CFR_W5 WWDG_CFR_W_5 10255 #define WWDG_CFR_W6 WWDG_CFR_W_6 10256 10257 #define WWDG_CFR_WDGTB_Pos (7U) 10258 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 10259 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 10260 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 10261 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 10262 10263 /* Legacy defines */ 10264 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 10265 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 10266 10267 #define WWDG_CFR_EWI_Pos (9U) 10268 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 10269 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 10270 10271 /******************* Bit definition for WWDG_SR register ********************/ 10272 #define WWDG_SR_EWIF_Pos (0U) 10273 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 10274 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 10275 10276 /** 10277 * @} 10278 */ 10279 10280 /** 10281 * @} 10282 */ 10283 10284 10285 /** @addtogroup Exported_macro 10286 * @{ 10287 */ 10288 10289 /****************************** ADC Instances *********************************/ 10290 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 10291 10292 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC) 10293 10294 /******************************* CAN Instances ********************************/ 10295 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN) 10296 10297 /****************************** CEC Instances *********************************/ 10298 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC) 10299 10300 /****************************** CRC Instances *********************************/ 10301 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 10302 10303 /******************************* DMA Instances ********************************/ 10304 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 10305 ((INSTANCE) == DMA1_Channel2) || \ 10306 ((INSTANCE) == DMA1_Channel3) || \ 10307 ((INSTANCE) == DMA1_Channel4) || \ 10308 ((INSTANCE) == DMA1_Channel5)) 10309 10310 /****************************** GPIO Instances ********************************/ 10311 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 10312 ((INSTANCE) == GPIOB) || \ 10313 ((INSTANCE) == GPIOC) || \ 10314 ((INSTANCE) == GPIOF)) 10315 10316 /**************************** GPIO Alternate Function Instances ***************/ 10317 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 10318 ((INSTANCE) == GPIOB) || \ 10319 ((INSTANCE) == GPIOF)) 10320 10321 /****************************** GPIO Lock Instances ***************************/ 10322 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 10323 ((INSTANCE) == GPIOB)) 10324 10325 /****************************** I2C Instances *********************************/ 10326 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 10327 10328 /****************** I2C Instances : wakeup capability from stop modes *********/ 10329 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 10330 10331 /****************************** I2S Instances *********************************/ 10332 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 10333 10334 /****************************** IWDG Instances ********************************/ 10335 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 10336 10337 /****************************** RTC Instances *********************************/ 10338 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 10339 10340 /****************************** SMBUS Instances *********************************/ 10341 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 10342 10343 /****************************** SPI Instances *********************************/ 10344 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 10345 ((INSTANCE) == SPI2)) 10346 10347 /****************************** TIM Instances *********************************/ 10348 #define IS_TIM_INSTANCE(INSTANCE)\ 10349 (((INSTANCE) == TIM1) || \ 10350 ((INSTANCE) == TIM2) || \ 10351 ((INSTANCE) == TIM3) || \ 10352 ((INSTANCE) == TIM14) || \ 10353 ((INSTANCE) == TIM16) || \ 10354 ((INSTANCE) == TIM17)) 10355 10356 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 10357 (((INSTANCE) == TIM1) || \ 10358 ((INSTANCE) == TIM2) || \ 10359 ((INSTANCE) == TIM3) || \ 10360 ((INSTANCE) == TIM14) || \ 10361 ((INSTANCE) == TIM16) || \ 10362 ((INSTANCE) == TIM17)) 10363 10364 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 10365 (((INSTANCE) == TIM1) || \ 10366 ((INSTANCE) == TIM2) || \ 10367 ((INSTANCE) == TIM3)) 10368 10369 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 10370 (((INSTANCE) == TIM1) || \ 10371 ((INSTANCE) == TIM2) || \ 10372 ((INSTANCE) == TIM3)) 10373 10374 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 10375 (((INSTANCE) == TIM1) || \ 10376 ((INSTANCE) == TIM2) || \ 10377 ((INSTANCE) == TIM3)) 10378 10379 #define IS_TIM_CC5_INSTANCE(INSTANCE)\ 10380 (((INSTANCE) == TIM1)) 10381 10382 #define IS_TIM_CC6_INSTANCE(INSTANCE)\ 10383 (((INSTANCE) == TIM1)) 10384 10385 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\ 10386 (((INSTANCE) == TIM1) || \ 10387 ((INSTANCE) == TIM2) || \ 10388 ((INSTANCE) == TIM3)) 10389 10390 10391 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 10392 (((INSTANCE) == TIM1) || \ 10393 ((INSTANCE) == TIM2) || \ 10394 ((INSTANCE) == TIM3)) 10395 10396 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 10397 (((INSTANCE) == TIM1) || \ 10398 ((INSTANCE) == TIM2) || \ 10399 ((INSTANCE) == TIM3)) 10400 10401 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 10402 (((INSTANCE) == TIM1) || \ 10403 ((INSTANCE) == TIM2) || \ 10404 ((INSTANCE) == TIM3)) 10405 10406 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 10407 (((INSTANCE) == TIM1) || \ 10408 ((INSTANCE) == TIM2) || \ 10409 ((INSTANCE) == TIM3)) 10410 10411 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 10412 (((INSTANCE) == TIM1) || \ 10413 ((INSTANCE) == TIM2) || \ 10414 ((INSTANCE) == TIM3)) 10415 10416 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 10417 (((INSTANCE) == TIM1) || \ 10418 ((INSTANCE) == TIM2) || \ 10419 ((INSTANCE) == TIM3)) 10420 10421 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ 10422 (((INSTANCE) == TIM1)) 10423 10424 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ 10425 (((INSTANCE) == TIM1)) 10426 10427 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 10428 (((INSTANCE) == TIM1) || \ 10429 ((INSTANCE) == TIM2) || \ 10430 ((INSTANCE) == TIM3)) 10431 10432 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 10433 (((INSTANCE) == TIM1) || \ 10434 ((INSTANCE) == TIM2) || \ 10435 ((INSTANCE) == TIM3)) 10436 10437 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 10438 (((INSTANCE) == TIM1) || \ 10439 ((INSTANCE) == TIM2) || \ 10440 ((INSTANCE) == TIM3)) 10441 10442 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ 10443 ((INSTANCE) == TIM2) 10444 10445 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 10446 (((INSTANCE) == TIM1) || \ 10447 ((INSTANCE) == TIM2) || \ 10448 ((INSTANCE) == TIM3) || \ 10449 ((INSTANCE) == TIM16) || \ 10450 ((INSTANCE) == TIM17)) 10451 10452 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 10453 (((INSTANCE) == TIM1) || \ 10454 ((INSTANCE) == TIM16) || \ 10455 ((INSTANCE) == TIM17)) 10456 10457 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 10458 ((((INSTANCE) == TIM1) && \ 10459 (((CHANNEL) == TIM_CHANNEL_1) || \ 10460 ((CHANNEL) == TIM_CHANNEL_2) || \ 10461 ((CHANNEL) == TIM_CHANNEL_3) || \ 10462 ((CHANNEL) == TIM_CHANNEL_4))) \ 10463 || \ 10464 (((INSTANCE) == TIM2) && \ 10465 (((CHANNEL) == TIM_CHANNEL_1) || \ 10466 ((CHANNEL) == TIM_CHANNEL_2) || \ 10467 ((CHANNEL) == TIM_CHANNEL_3) || \ 10468 ((CHANNEL) == TIM_CHANNEL_4))) \ 10469 || \ 10470 (((INSTANCE) == TIM3) && \ 10471 (((CHANNEL) == TIM_CHANNEL_1) || \ 10472 ((CHANNEL) == TIM_CHANNEL_2) || \ 10473 ((CHANNEL) == TIM_CHANNEL_3) || \ 10474 ((CHANNEL) == TIM_CHANNEL_4))) \ 10475 || \ 10476 (((INSTANCE) == TIM14) && \ 10477 (((CHANNEL) == TIM_CHANNEL_1))) \ 10478 || \ 10479 (((INSTANCE) == TIM16) && \ 10480 (((CHANNEL) == TIM_CHANNEL_1))) \ 10481 || \ 10482 (((INSTANCE) == TIM17) && \ 10483 (((CHANNEL) == TIM_CHANNEL_1)))) 10484 10485 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 10486 ((((INSTANCE) == TIM1) && \ 10487 (((CHANNEL) == TIM_CHANNEL_1) || \ 10488 ((CHANNEL) == TIM_CHANNEL_2) || \ 10489 ((CHANNEL) == TIM_CHANNEL_3))) \ 10490 || \ 10491 (((INSTANCE) == TIM16) && \ 10492 ((CHANNEL) == TIM_CHANNEL_1)) \ 10493 || \ 10494 (((INSTANCE) == TIM17) && \ 10495 ((CHANNEL) == TIM_CHANNEL_1))) 10496 10497 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 10498 (((INSTANCE) == TIM1) || \ 10499 ((INSTANCE) == TIM2) || \ 10500 ((INSTANCE) == TIM3)) 10501 10502 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 10503 (((INSTANCE) == TIM1) || \ 10504 ((INSTANCE) == TIM16) || \ 10505 ((INSTANCE) == TIM17)) 10506 10507 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 10508 (((INSTANCE) == TIM1) || \ 10509 ((INSTANCE) == TIM2) || \ 10510 ((INSTANCE) == TIM3) || \ 10511 ((INSTANCE) == TIM14) || \ 10512 ((INSTANCE) == TIM16) || \ 10513 ((INSTANCE) == TIM17)) 10514 10515 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\ 10516 (((INSTANCE) == TIM1)) 10517 10518 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\ 10519 (((INSTANCE) == TIM1)) 10520 10521 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 10522 (((INSTANCE) == TIM1) || \ 10523 ((INSTANCE) == TIM2) || \ 10524 ((INSTANCE) == TIM3) || \ 10525 ((INSTANCE) == TIM16) || \ 10526 ((INSTANCE) == TIM17)) 10527 10528 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 10529 (((INSTANCE) == TIM1) || \ 10530 ((INSTANCE) == TIM2) || \ 10531 ((INSTANCE) == TIM3) || \ 10532 ((INSTANCE) == TIM16) || \ 10533 ((INSTANCE) == TIM17)) 10534 10535 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 10536 (((INSTANCE) == TIM1) || \ 10537 ((INSTANCE) == TIM16) || \ 10538 ((INSTANCE) == TIM17)) 10539 10540 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ 10541 (((INSTANCE) == TIM1) || \ 10542 ((INSTANCE) == TIM14)) 10543 10544 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ 10545 ((INSTANCE) == TIM1) 10546 10547 /****************************** TSC Instances *********************************/ 10548 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) 10549 10550 /*********************** UART Instances : IRDA mode ***************************/ 10551 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10552 10553 /********************* UART Instances : Smard card mode ***********************/ 10554 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10555 10556 /******************** USART Instances : Synchronous mode **********************/ 10557 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10558 ((INSTANCE) == USART2)) 10559 10560 /******************** USART Instances : auto Baud rate detection **************/ 10561 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10562 10563 /******************** UART Instances : Asynchronous mode **********************/ 10564 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10565 ((INSTANCE) == USART2)) 10566 10567 /******************** UART Instances : Half-Duplex mode **********************/ 10568 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10569 ((INSTANCE) == USART2)) 10570 10571 /****************** UART Instances : Hardware Flow control ********************/ 10572 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10573 ((INSTANCE) == USART2)) 10574 10575 /****************** UART Instances : LIN mode ********************/ 10576 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10577 10578 /****************** UART Instances : wakeup from stop mode ********************/ 10579 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10580 /* Old macro definition maintained for legacy purpose */ 10581 #define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE 10582 10583 /****************** UART Instances : Driver enable detection ********************/ 10584 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10585 ((INSTANCE) == USART2)) 10586 10587 /****************************** USB Instances ********************************/ 10588 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 10589 10590 /****************************** WWDG Instances ********************************/ 10591 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 10592 10593 /** 10594 * @} 10595 */ 10596 10597 10598 /******************************************************************************/ 10599 /* For a painless codes migration between the STM32F0xx device product */ 10600 /* lines, the aliases defined below are put in place to overcome the */ 10601 /* differences in the interrupt handlers and IRQn definitions. */ 10602 /* No need to update developed interrupt code when moving across */ 10603 /* product lines within the same STM32F0 Family */ 10604 /******************************************************************************/ 10605 10606 /* Aliases for __IRQn */ 10607 #define ADC1_COMP_IRQn ADC1_IRQn 10608 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 10609 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 10610 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 10611 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 10612 #define RCC_IRQn RCC_CRS_IRQn 10613 #define PVD_VDDIO2_IRQn VDDIO2_IRQn 10614 #define PVD_IRQn VDDIO2_IRQn 10615 10616 #define SVC_IRQn SVCall_IRQn 10617 10618 /* Aliases for __IRQHandler */ 10619 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 10620 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 10621 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 10622 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 10623 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 10624 #define RCC_IRQHandler RCC_CRS_IRQHandler 10625 #define PVD_VDDIO2_IRQHandler VDDIO2_IRQHandler 10626 #define PVD_IRQHandler VDDIO2_IRQHandler 10627 10628 #ifdef __cplusplus 10629 } 10630 #endif /* __cplusplus */ 10631 10632 #endif /* __STM32F048xx_H */ 10633 10634 /** 10635 * @} 10636 */ 10637 10638 /** 10639 * @} 10640 */ 10641 10642
