1 /** 2 ****************************************************************************** 3 * @file stm32f051x8.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F0xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2016 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 /** @addtogroup CMSIS 27 * @{ 28 */ 29 30 /** @addtogroup stm32f051x8 31 * @{ 32 */ 33 34 #ifndef __STM32F051x8_H 35 #define __STM32F051x8_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** @addtogroup Configuration_section_for_CMSIS 42 * @{ 43 */ 44 /** 45 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals 46 */ 47 #define __CM0_REV 0 /*!< Core Revision r0p0 */ 48 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ 49 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 51 52 /** 53 * @} 54 */ 55 56 /** @addtogroup Peripheral_interrupt_number_definition 57 * @{ 58 */ 59 60 /** 61 * @brief STM32F0xx Interrupt Number Definition, according to the selected device 62 * in @ref Library_configuration_section 63 */ 64 65 /*!< Interrupt Number Definition */ 66 typedef enum 67 { 68 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ 69 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 70 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 71 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 72 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 73 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 74 75 /****** STM32F0 specific Interrupt Numbers ******************************************************************/ 76 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 77 PVD_IRQn = 1, /*!< PVD Interrupt through EXTI Lines 16 */ 78 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 79 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 80 RCC_IRQn = 4, /*!< RCC global Interrupt */ 81 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ 82 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ 83 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ 84 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ 85 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 86 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ 87 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ 88 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ 89 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ 90 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 91 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ 92 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 93 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */ 94 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 95 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 96 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 97 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 98 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 99 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ 100 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 101 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 102 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 103 USART2_IRQn = 28, /*!< USART2 global Interrupt */ 104 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ 105 } IRQn_Type; 106 107 /** 108 * @} 109 */ 110 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ 112 #include "system_stm32f0xx.h" /* STM32F0xx System Header */ 113 #include <stdint.h> 114 115 /** @addtogroup Peripheral_registers_structures 116 * @{ 117 */ 118 119 /** 120 * @brief Analog to Digital Converter 121 */ 122 123 typedef struct 124 { 125 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 126 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 127 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 128 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 129 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 130 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 131 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 132 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 133 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 134 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 135 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 136 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 137 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 138 } ADC_TypeDef; 139 140 typedef struct 141 { 142 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 143 } ADC_Common_TypeDef; 144 145 /** 146 * @brief HDMI-CEC 147 */ 148 149 typedef struct 150 { 151 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ 152 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ 153 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ 154 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ 155 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ 156 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ 157 }CEC_TypeDef; 158 159 /** 160 * @brief Comparator 161 */ 162 163 typedef struct 164 { 165 __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 166 } COMP_TypeDef; 167 168 typedef struct 169 { 170 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 171 } COMP_Common_TypeDef; 172 173 /* Legacy defines */ 174 typedef struct 175 { 176 __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */ 177 }COMP1_2_TypeDef; 178 179 /** 180 * @brief CRC calculation unit 181 */ 182 183 typedef struct 184 { 185 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 186 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 187 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 188 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 189 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 190 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 191 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 192 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ 193 } CRC_TypeDef; 194 195 /** 196 * @brief Digital to Analog Converter 197 */ 198 199 typedef struct 200 { 201 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 202 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 203 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 204 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 205 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 206 uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x14 to 0x28 */ 207 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 208 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ 209 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 210 } DAC_TypeDef; 211 212 /** 213 * @brief Debug MCU 214 */ 215 216 typedef struct 217 { 218 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 219 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 220 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 221 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 222 }DBGMCU_TypeDef; 223 224 /** 225 * @brief DMA Controller 226 */ 227 228 typedef struct 229 { 230 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 231 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 232 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 233 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 234 } DMA_Channel_TypeDef; 235 236 typedef struct 237 { 238 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 239 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 240 } DMA_TypeDef; 241 242 /** 243 * @brief External Interrupt/Event Controller 244 */ 245 246 typedef struct 247 { 248 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 249 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 250 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 251 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 252 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 253 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 254 } EXTI_TypeDef; 255 256 /** 257 * @brief FLASH Registers 258 */ 259 typedef struct 260 { 261 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ 262 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ 263 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ 264 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ 265 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ 266 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ 267 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ 268 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ 269 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ 270 } FLASH_TypeDef; 271 272 /** 273 * @brief Option Bytes Registers 274 */ 275 typedef struct 276 { 277 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ 278 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ 279 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ 280 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ 281 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ 282 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ 283 } OB_TypeDef; 284 285 /** 286 * @brief General Purpose I/O 287 */ 288 289 typedef struct 290 { 291 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 292 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 293 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 294 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 295 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 296 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 297 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ 298 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 299 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ 300 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 301 } GPIO_TypeDef; 302 303 /** 304 * @brief SysTem Configuration 305 */ 306 307 typedef struct 308 { 309 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 310 uint32_t RESERVED; /*!< Reserved, 0x04 */ 311 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 312 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 313 } SYSCFG_TypeDef; 314 315 /** 316 * @brief Inter-integrated Circuit Interface 317 */ 318 319 typedef struct 320 { 321 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 322 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 323 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 324 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 325 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 326 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 327 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 328 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 329 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 330 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 331 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 332 } I2C_TypeDef; 333 334 /** 335 * @brief Independent WATCHDOG 336 */ 337 338 typedef struct 339 { 340 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 341 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 342 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 343 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 344 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 345 } IWDG_TypeDef; 346 347 /** 348 * @brief Power Control 349 */ 350 351 typedef struct 352 { 353 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 354 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 355 } PWR_TypeDef; 356 357 /** 358 * @brief Reset and Clock Control 359 */ 360 361 typedef struct 362 { 363 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 364 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 365 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 366 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 367 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 368 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 369 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 370 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 371 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 372 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 373 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 374 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 375 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 376 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ 377 } RCC_TypeDef; 378 379 /** 380 * @brief Real-Time Clock 381 */ 382 typedef struct 383 { 384 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 385 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 386 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 387 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 388 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 389 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 390 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ 391 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 392 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ 393 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 394 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 395 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 396 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 397 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 398 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 399 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 400 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 401 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 402 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */ 403 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */ 404 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 405 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 406 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 407 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 408 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 409 } RTC_TypeDef; 410 411 /** 412 * @brief Serial Peripheral Interface 413 */ 414 415 typedef struct 416 { 417 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 418 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 419 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 420 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 421 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 422 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 423 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 424 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 425 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 426 } SPI_TypeDef; 427 428 /** 429 * @brief TIM 430 */ 431 typedef struct 432 { 433 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 434 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 435 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 436 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 437 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 438 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 439 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 440 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 441 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 442 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 443 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 444 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 445 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 446 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 447 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 448 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 449 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 450 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 451 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 452 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 453 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 454 } TIM_TypeDef; 455 456 /** 457 * @brief Touch Sensing Controller (TSC) 458 */ 459 typedef struct 460 { 461 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 462 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 463 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 464 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 465 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 466 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 467 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 468 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 469 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 470 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 471 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 472 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 473 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 474 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ 475 }TSC_TypeDef; 476 477 /** 478 * @brief Universal Synchronous Asynchronous Receiver Transmitter 479 */ 480 481 typedef struct 482 { 483 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 484 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 485 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 486 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 487 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 488 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 489 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 490 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 491 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 492 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 493 uint16_t RESERVED1; /*!< Reserved, 0x26 */ 494 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 495 uint16_t RESERVED2; /*!< Reserved, 0x2A */ 496 } USART_TypeDef; 497 498 /** 499 * @brief Window WATCHDOG 500 */ 501 typedef struct 502 { 503 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 504 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 505 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 506 } WWDG_TypeDef; 507 508 /** 509 * @} 510 */ 511 512 /** @addtogroup Peripheral_memory_map 513 * @{ 514 */ 515 516 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 517 #define FLASH_BANK1_END 0x0800FFFFUL /*!< FLASH END address of bank1 */ 518 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 519 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 520 521 /*!< Peripheral memory map */ 522 #define APBPERIPH_BASE PERIPH_BASE 523 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 524 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 525 526 /*!< APB peripherals */ 527 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) 528 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 529 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) 530 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) 531 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 532 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 533 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 534 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) 535 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 536 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 537 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) 538 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 539 #define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) 540 541 #define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) 542 543 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 544 #define COMP_BASE (APBPERIPH_BASE + 0x0001001CUL) 545 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) 546 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 547 #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) 548 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) 549 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 550 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 551 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) 552 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) 553 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) 554 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) 555 556 /*!< AHB peripherals */ 557 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 558 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 559 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 560 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 561 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 562 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 563 564 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 565 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ 566 #define OB_BASE 0x1FFFF800UL /*!< FLASH Option Bytes base address */ 567 #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ 568 #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ 569 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 570 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL) 571 572 /*!< AHB2 peripherals */ 573 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) 574 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) 575 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) 576 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) 577 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) 578 579 /** 580 * @} 581 */ 582 583 /** @addtogroup Peripheral_declaration 584 * @{ 585 */ 586 587 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 588 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 589 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 590 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 591 #define RTC ((RTC_TypeDef *) RTC_BASE) 592 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 593 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 594 #define USART2 ((USART_TypeDef *) USART2_BASE) 595 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 596 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 597 #define PWR ((PWR_TypeDef *) PWR_BASE) 598 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 599 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ 600 #define CEC ((CEC_TypeDef *) CEC_BASE) 601 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 602 #define COMP1 ((COMP_TypeDef *) COMP_BASE) 603 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002)) 604 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) 605 #define COMP ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */ 606 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 607 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 608 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 609 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ 610 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 611 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 612 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 613 #define USART1 ((USART_TypeDef *) USART1_BASE) 614 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 615 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 616 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 617 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 618 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 619 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 620 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 621 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 622 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 623 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 624 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 625 #define OB ((OB_TypeDef *) OB_BASE) 626 #define RCC ((RCC_TypeDef *) RCC_BASE) 627 #define CRC ((CRC_TypeDef *) CRC_BASE) 628 #define TSC ((TSC_TypeDef *) TSC_BASE) 629 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 630 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 631 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 632 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 633 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 634 /** 635 * @} 636 */ 637 638 /** @addtogroup Exported_constants 639 * @{ 640 */ 641 642 /** @addtogroup Hardware_Constant_Definition 643 * @{ 644 */ 645 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 646 647 /** 648 * @} 649 */ 650 651 /** @addtogroup Peripheral_Registers_Bits_Definition 652 * @{ 653 */ 654 655 /******************************************************************************/ 656 /* Peripheral Registers Bits Definition */ 657 /******************************************************************************/ 658 659 /******************************************************************************/ 660 /* */ 661 /* Analog to Digital Converter (ADC) */ 662 /* */ 663 /******************************************************************************/ 664 665 /* 666 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 667 */ 668 #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ 669 670 /******************** Bits definition for ADC_ISR register ******************/ 671 #define ADC_ISR_ADRDY_Pos (0U) 672 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 673 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 674 #define ADC_ISR_EOSMP_Pos (1U) 675 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 676 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 677 #define ADC_ISR_EOC_Pos (2U) 678 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 679 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 680 #define ADC_ISR_EOS_Pos (3U) 681 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 682 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 683 #define ADC_ISR_OVR_Pos (4U) 684 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 685 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 686 #define ADC_ISR_AWD1_Pos (7U) 687 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 688 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 689 690 /* Legacy defines */ 691 #define ADC_ISR_AWD (ADC_ISR_AWD1) 692 #define ADC_ISR_EOSEQ (ADC_ISR_EOS) 693 694 /******************** Bits definition for ADC_IER register ******************/ 695 #define ADC_IER_ADRDYIE_Pos (0U) 696 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 697 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 698 #define ADC_IER_EOSMPIE_Pos (1U) 699 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 700 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 701 #define ADC_IER_EOCIE_Pos (2U) 702 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 703 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 704 #define ADC_IER_EOSIE_Pos (3U) 705 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 706 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 707 #define ADC_IER_OVRIE_Pos (4U) 708 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 709 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 710 #define ADC_IER_AWD1IE_Pos (7U) 711 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 712 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 713 714 /* Legacy defines */ 715 #define ADC_IER_AWDIE (ADC_IER_AWD1IE) 716 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) 717 718 /******************** Bits definition for ADC_CR register *******************/ 719 #define ADC_CR_ADEN_Pos (0U) 720 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 721 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 722 #define ADC_CR_ADDIS_Pos (1U) 723 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 724 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 725 #define ADC_CR_ADSTART_Pos (2U) 726 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 727 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 728 #define ADC_CR_ADSTP_Pos (4U) 729 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 730 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 731 #define ADC_CR_ADCAL_Pos (31U) 732 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 733 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 734 735 /******************* Bits definition for ADC_CFGR1 register *****************/ 736 #define ADC_CFGR1_DMAEN_Pos (0U) 737 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 738 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 739 #define ADC_CFGR1_DMACFG_Pos (1U) 740 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 741 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 742 #define ADC_CFGR1_SCANDIR_Pos (2U) 743 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 744 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 745 746 #define ADC_CFGR1_RES_Pos (3U) 747 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 748 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 749 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 750 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 751 752 #define ADC_CFGR1_ALIGN_Pos (5U) 753 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 754 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 755 756 #define ADC_CFGR1_EXTSEL_Pos (6U) 757 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 758 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 759 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 760 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 761 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 762 763 #define ADC_CFGR1_EXTEN_Pos (10U) 764 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 765 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 766 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 767 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 768 769 #define ADC_CFGR1_OVRMOD_Pos (12U) 770 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 771 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 772 #define ADC_CFGR1_CONT_Pos (13U) 773 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 774 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 775 #define ADC_CFGR1_WAIT_Pos (14U) 776 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 777 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 778 #define ADC_CFGR1_AUTOFF_Pos (15U) 779 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 780 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 781 #define ADC_CFGR1_DISCEN_Pos (16U) 782 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 783 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 784 785 #define ADC_CFGR1_AWD1SGL_Pos (22U) 786 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 787 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 788 #define ADC_CFGR1_AWD1EN_Pos (23U) 789 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 790 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 791 792 #define ADC_CFGR1_AWD1CH_Pos (26U) 793 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 794 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 795 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 796 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 797 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 798 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 799 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 800 801 /* Legacy defines */ 802 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) 803 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) 804 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) 805 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) 806 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) 807 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) 808 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) 809 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) 810 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) 811 812 /******************* Bits definition for ADC_CFGR2 register *****************/ 813 #define ADC_CFGR2_CKMODE_Pos (30U) 814 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 815 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 816 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 817 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 818 819 /* Legacy defines */ 820 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ 821 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ 822 823 /****************** Bit definition for ADC_SMPR register ********************/ 824 #define ADC_SMPR_SMP_Pos (0U) 825 #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 826 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ 827 #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 828 #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 829 #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 830 831 /* Legacy defines */ 832 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ 833 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ 834 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ 835 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ 836 837 /******************* Bit definition for ADC_TR register ********************/ 838 #define ADC_TR1_LT1_Pos (0U) 839 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 840 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 841 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 842 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 843 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 844 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 845 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 846 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 847 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 848 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 849 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 850 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 851 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 852 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 853 854 #define ADC_TR1_HT1_Pos (16U) 855 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 856 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 857 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 858 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 859 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 860 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 861 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 862 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 863 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 864 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 865 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 866 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 867 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 868 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 869 870 /* Legacy defines */ 871 #define ADC_TR_HT (ADC_TR1_HT1) 872 #define ADC_TR_LT (ADC_TR1_LT1) 873 #define ADC_HTR_HT (ADC_TR1_HT1) 874 #define ADC_LTR_LT (ADC_TR1_LT1) 875 876 /****************** Bit definition for ADC_CHSELR register ******************/ 877 #define ADC_CHSELR_CHSEL_Pos (0U) 878 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 879 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 880 #define ADC_CHSELR_CHSEL18_Pos (18U) 881 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 882 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ 883 #define ADC_CHSELR_CHSEL17_Pos (17U) 884 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 885 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 886 #define ADC_CHSELR_CHSEL16_Pos (16U) 887 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 888 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 889 #define ADC_CHSELR_CHSEL15_Pos (15U) 890 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 891 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 892 #define ADC_CHSELR_CHSEL14_Pos (14U) 893 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 894 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 895 #define ADC_CHSELR_CHSEL13_Pos (13U) 896 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 897 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 898 #define ADC_CHSELR_CHSEL12_Pos (12U) 899 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 900 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 901 #define ADC_CHSELR_CHSEL11_Pos (11U) 902 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 903 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 904 #define ADC_CHSELR_CHSEL10_Pos (10U) 905 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 906 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 907 #define ADC_CHSELR_CHSEL9_Pos (9U) 908 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 909 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 910 #define ADC_CHSELR_CHSEL8_Pos (8U) 911 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 912 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 913 #define ADC_CHSELR_CHSEL7_Pos (7U) 914 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 915 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 916 #define ADC_CHSELR_CHSEL6_Pos (6U) 917 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 918 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 919 #define ADC_CHSELR_CHSEL5_Pos (5U) 920 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 921 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 922 #define ADC_CHSELR_CHSEL4_Pos (4U) 923 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 924 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 925 #define ADC_CHSELR_CHSEL3_Pos (3U) 926 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 927 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 928 #define ADC_CHSELR_CHSEL2_Pos (2U) 929 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 930 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 931 #define ADC_CHSELR_CHSEL1_Pos (1U) 932 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 933 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 934 #define ADC_CHSELR_CHSEL0_Pos (0U) 935 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 936 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 937 938 /******************** Bit definition for ADC_DR register ********************/ 939 #define ADC_DR_DATA_Pos (0U) 940 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 941 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 942 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 943 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 944 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 945 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 946 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 947 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 948 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 949 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 950 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 951 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 952 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 953 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 954 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 955 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 956 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 957 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 958 959 /************************* ADC Common registers *****************************/ 960 /******************* Bit definition for ADC_CCR register ********************/ 961 #define ADC_CCR_VREFEN_Pos (22U) 962 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 963 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 964 #define ADC_CCR_TSEN_Pos (23U) 965 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 966 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 967 968 #define ADC_CCR_VBATEN_Pos (24U) 969 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 970 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 971 972 /******************************************************************************/ 973 /* */ 974 /* HDMI-CEC (CEC) */ 975 /* */ 976 /******************************************************************************/ 977 978 /******************* Bit definition for CEC_CR register *********************/ 979 #define CEC_CR_CECEN_Pos (0U) 980 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ 981 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ 982 #define CEC_CR_TXSOM_Pos (1U) 983 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ 984 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ 985 #define CEC_CR_TXEOM_Pos (2U) 986 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ 987 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ 988 989 /******************* Bit definition for CEC_CFGR register *******************/ 990 #define CEC_CFGR_SFT_Pos (0U) 991 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ 992 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ 993 #define CEC_CFGR_RXTOL_Pos (3U) 994 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ 995 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ 996 #define CEC_CFGR_BRESTP_Pos (4U) 997 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ 998 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ 999 #define CEC_CFGR_BREGEN_Pos (5U) 1000 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ 1001 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ 1002 #define CEC_CFGR_LBPEGEN_Pos (6U) 1003 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ 1004 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ 1005 #define CEC_CFGR_BRDNOGEN_Pos (7U) 1006 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ 1007 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ 1008 #define CEC_CFGR_SFTOPT_Pos (8U) 1009 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ 1010 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ 1011 #define CEC_CFGR_OAR_Pos (16U) 1012 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ 1013 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ 1014 #define CEC_CFGR_LSTN_Pos (31U) 1015 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ 1016 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ 1017 1018 /******************* Bit definition for CEC_TXDR register *******************/ 1019 #define CEC_TXDR_TXD_Pos (0U) 1020 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ 1021 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ 1022 1023 /******************* Bit definition for CEC_RXDR register *******************/ 1024 #define CEC_RXDR_RXD_Pos (0U) 1025 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ 1026 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ 1027 /* Legacy aliases */ 1028 #define CEC_TXDR_RXD_Pos CEC_RXDR_RXD_Pos 1029 #define CEC_TXDR_RXD_Msk CEC_RXDR_RXD_Msk 1030 #define CEC_TXDR_RXD CEC_RXDR_RXD 1031 /******************* Bit definition for CEC_ISR register ********************/ 1032 #define CEC_ISR_RXBR_Pos (0U) 1033 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ 1034 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ 1035 #define CEC_ISR_RXEND_Pos (1U) 1036 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ 1037 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ 1038 #define CEC_ISR_RXOVR_Pos (2U) 1039 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ 1040 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ 1041 #define CEC_ISR_BRE_Pos (3U) 1042 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ 1043 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ 1044 #define CEC_ISR_SBPE_Pos (4U) 1045 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ 1046 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ 1047 #define CEC_ISR_LBPE_Pos (5U) 1048 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ 1049 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ 1050 #define CEC_ISR_RXACKE_Pos (6U) 1051 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ 1052 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ 1053 #define CEC_ISR_ARBLST_Pos (7U) 1054 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ 1055 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ 1056 #define CEC_ISR_TXBR_Pos (8U) 1057 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ 1058 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ 1059 #define CEC_ISR_TXEND_Pos (9U) 1060 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ 1061 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ 1062 #define CEC_ISR_TXUDR_Pos (10U) 1063 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ 1064 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ 1065 #define CEC_ISR_TXERR_Pos (11U) 1066 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ 1067 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ 1068 #define CEC_ISR_TXACKE_Pos (12U) 1069 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ 1070 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ 1071 1072 /******************* Bit definition for CEC_IER register ********************/ 1073 #define CEC_IER_RXBRIE_Pos (0U) 1074 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ 1075 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ 1076 #define CEC_IER_RXENDIE_Pos (1U) 1077 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ 1078 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ 1079 #define CEC_IER_RXOVRIE_Pos (2U) 1080 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ 1081 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ 1082 #define CEC_IER_BREIE_Pos (3U) 1083 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ 1084 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ 1085 #define CEC_IER_SBPEIE_Pos (4U) 1086 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ 1087 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ 1088 #define CEC_IER_LBPEIE_Pos (5U) 1089 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ 1090 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ 1091 #define CEC_IER_RXACKEIE_Pos (6U) 1092 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ 1093 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ 1094 #define CEC_IER_ARBLSTIE_Pos (7U) 1095 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ 1096 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ 1097 #define CEC_IER_TXBRIE_Pos (8U) 1098 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ 1099 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ 1100 #define CEC_IER_TXENDIE_Pos (9U) 1101 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ 1102 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ 1103 #define CEC_IER_TXUDRIE_Pos (10U) 1104 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ 1105 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ 1106 #define CEC_IER_TXERRIE_Pos (11U) 1107 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ 1108 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ 1109 #define CEC_IER_TXACKEIE_Pos (12U) 1110 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ 1111 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ 1112 1113 /******************************************************************************/ 1114 /* */ 1115 /* Analog Comparators (COMP) */ 1116 /* */ 1117 /******************************************************************************/ 1118 /*********************** Bit definition for COMP_CSR register ***************/ 1119 /* COMP1 bits definition */ 1120 #define COMP_CSR_COMP1EN_Pos (0U) 1121 #define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ 1122 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ 1123 #define COMP_CSR_COMP1SW1_Pos (1U) 1124 #define COMP_CSR_COMP1SW1_Msk (0x1UL << COMP_CSR_COMP1SW1_Pos) /*!< 0x00000002 */ 1125 #define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */ 1126 #define COMP_CSR_COMP1MODE_Pos (2U) 1127 #define COMP_CSR_COMP1MODE_Msk (0x3UL << COMP_CSR_COMP1MODE_Pos) /*!< 0x0000000C */ 1128 #define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /*!< COMP1 power mode */ 1129 #define COMP_CSR_COMP1MODE_0 (0x1UL << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000004 */ 1130 #define COMP_CSR_COMP1MODE_1 (0x2UL << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000008 */ 1131 #define COMP_CSR_COMP1INSEL_Pos (4U) 1132 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */ 1133 #define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */ 1134 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */ 1135 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */ 1136 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */ 1137 #define COMP_CSR_COMP1OUTSEL_Pos (8U) 1138 #define COMP_CSR_COMP1OUTSEL_Msk (0x7UL << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000700 */ 1139 #define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */ 1140 #define COMP_CSR_COMP1OUTSEL_0 (0x1UL << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000100 */ 1141 #define COMP_CSR_COMP1OUTSEL_1 (0x2UL << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000200 */ 1142 #define COMP_CSR_COMP1OUTSEL_2 (0x4UL << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */ 1143 #define COMP_CSR_COMP1POL_Pos (11U) 1144 #define COMP_CSR_COMP1POL_Msk (0x1UL << COMP_CSR_COMP1POL_Pos) /*!< 0x00000800 */ 1145 #define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /*!< COMP1 output polarity */ 1146 #define COMP_CSR_COMP1HYST_Pos (12U) 1147 #define COMP_CSR_COMP1HYST_Msk (0x3UL << COMP_CSR_COMP1HYST_Pos) /*!< 0x00003000 */ 1148 #define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */ 1149 #define COMP_CSR_COMP1HYST_0 (0x1UL << COMP_CSR_COMP1HYST_Pos) /*!< 0x00001000 */ 1150 #define COMP_CSR_COMP1HYST_1 (0x2UL << COMP_CSR_COMP1HYST_Pos) /*!< 0x00002000 */ 1151 #define COMP_CSR_COMP1OUT_Pos (14U) 1152 #define COMP_CSR_COMP1OUT_Msk (0x1UL << COMP_CSR_COMP1OUT_Pos) /*!< 0x00004000 */ 1153 #define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /*!< COMP1 output level */ 1154 #define COMP_CSR_COMP1LOCK_Pos (15U) 1155 #define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x00008000 */ 1156 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ 1157 /* COMP2 bits definition */ 1158 #define COMP_CSR_COMP2EN_Pos (16U) 1159 #define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00010000 */ 1160 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ 1161 #define COMP_CSR_COMP2MODE_Pos (18U) 1162 #define COMP_CSR_COMP2MODE_Msk (0x3UL << COMP_CSR_COMP2MODE_Pos) /*!< 0x000C0000 */ 1163 #define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /*!< COMP2 power mode */ 1164 #define COMP_CSR_COMP2MODE_0 (0x1UL << COMP_CSR_COMP2MODE_Pos) /*!< 0x00040000 */ 1165 #define COMP_CSR_COMP2MODE_1 (0x2UL << COMP_CSR_COMP2MODE_Pos) /*!< 0x00080000 */ 1166 #define COMP_CSR_COMP2INSEL_Pos (20U) 1167 #define COMP_CSR_COMP2INSEL_Msk (0x7UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */ 1168 #define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */ 1169 #define COMP_CSR_COMP2INSEL_0 (0x1UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */ 1170 #define COMP_CSR_COMP2INSEL_1 (0x2UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */ 1171 #define COMP_CSR_COMP2INSEL_2 (0x4UL << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */ 1172 #define COMP_CSR_WNDWEN_Pos (23U) 1173 #define COMP_CSR_WNDWEN_Msk (0x1UL << COMP_CSR_WNDWEN_Pos) /*!< 0x00800000 */ 1174 #define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1175 #define COMP_CSR_COMP2OUTSEL_Pos (24U) 1176 #define COMP_CSR_COMP2OUTSEL_Msk (0x7UL << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x07000000 */ 1177 #define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */ 1178 #define COMP_CSR_COMP2OUTSEL_0 (0x1UL << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x01000000 */ 1179 #define COMP_CSR_COMP2OUTSEL_1 (0x2UL << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x02000000 */ 1180 #define COMP_CSR_COMP2OUTSEL_2 (0x4UL << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x04000000 */ 1181 #define COMP_CSR_COMP2POL_Pos (27U) 1182 #define COMP_CSR_COMP2POL_Msk (0x1UL << COMP_CSR_COMP2POL_Pos) /*!< 0x08000000 */ 1183 #define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /*!< COMP2 output polarity */ 1184 #define COMP_CSR_COMP2HYST_Pos (28U) 1185 #define COMP_CSR_COMP2HYST_Msk (0x3UL << COMP_CSR_COMP2HYST_Pos) /*!< 0x30000000 */ 1186 #define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */ 1187 #define COMP_CSR_COMP2HYST_0 (0x1UL << COMP_CSR_COMP2HYST_Pos) /*!< 0x10000000 */ 1188 #define COMP_CSR_COMP2HYST_1 (0x2UL << COMP_CSR_COMP2HYST_Pos) /*!< 0x20000000 */ 1189 #define COMP_CSR_COMP2OUT_Pos (30U) 1190 #define COMP_CSR_COMP2OUT_Msk (0x1UL << COMP_CSR_COMP2OUT_Pos) /*!< 0x40000000 */ 1191 #define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /*!< COMP2 output level */ 1192 #define COMP_CSR_COMP2LOCK_Pos (31U) 1193 #define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ 1194 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ 1195 /* COMPx bits definition */ 1196 #define COMP_CSR_COMPxEN_Pos (0U) 1197 #define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ 1198 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ 1199 #define COMP_CSR_COMPxMODE_Pos (2U) 1200 #define COMP_CSR_COMPxMODE_Msk (0x3UL << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */ 1201 #define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */ 1202 #define COMP_CSR_COMPxMODE_0 (0x1UL << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */ 1203 #define COMP_CSR_COMPxMODE_1 (0x2UL << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */ 1204 #define COMP_CSR_COMPxINSEL_Pos (4U) 1205 #define COMP_CSR_COMPxINSEL_Msk (0x7UL << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */ 1206 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */ 1207 #define COMP_CSR_COMPxINSEL_0 (0x1UL << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000010 */ 1208 #define COMP_CSR_COMPxINSEL_1 (0x2UL << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000020 */ 1209 #define COMP_CSR_COMPxINSEL_2 (0x4UL << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000040 */ 1210 #define COMP_CSR_COMPxOUTSEL_Pos (8U) 1211 #define COMP_CSR_COMPxOUTSEL_Msk (0x7UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000700 */ 1212 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */ 1213 #define COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000100 */ 1214 #define COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000200 */ 1215 #define COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */ 1216 #define COMP_CSR_COMPxPOL_Pos (11U) 1217 #define COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos) /*!< 0x00000800 */ 1218 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */ 1219 #define COMP_CSR_COMPxHYST_Pos (12U) 1220 #define COMP_CSR_COMPxHYST_Msk (0x3UL << COMP_CSR_COMPxHYST_Pos) /*!< 0x00003000 */ 1221 #define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */ 1222 #define COMP_CSR_COMPxHYST_0 (0x1UL << COMP_CSR_COMPxHYST_Pos) /*!< 0x00001000 */ 1223 #define COMP_CSR_COMPxHYST_1 (0x2UL << COMP_CSR_COMPxHYST_Pos) /*!< 0x00002000 */ 1224 #define COMP_CSR_COMPxOUT_Pos (14U) 1225 #define COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos) /*!< 0x00004000 */ 1226 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */ 1227 #define COMP_CSR_COMPxLOCK_Pos (15U) 1228 #define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x00008000 */ 1229 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ 1230 1231 /******************************************************************************/ 1232 /* */ 1233 /* CRC calculation unit (CRC) */ 1234 /* */ 1235 /******************************************************************************/ 1236 /******************* Bit definition for CRC_DR register *********************/ 1237 #define CRC_DR_DR_Pos (0U) 1238 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1239 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1240 1241 /******************* Bit definition for CRC_IDR register ********************/ 1242 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 1243 1244 /******************** Bit definition for CRC_CR register ********************/ 1245 #define CRC_CR_RESET_Pos (0U) 1246 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1247 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 1248 #define CRC_CR_REV_IN_Pos (5U) 1249 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 1250 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 1251 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 1252 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 1253 #define CRC_CR_REV_OUT_Pos (7U) 1254 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 1255 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 1256 1257 /******************* Bit definition for CRC_INIT register *******************/ 1258 #define CRC_INIT_INIT_Pos (0U) 1259 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 1260 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 1261 1262 /******************************************************************************/ 1263 /* */ 1264 /* Digital to Analog Converter (DAC) */ 1265 /* */ 1266 /******************************************************************************/ 1267 1268 /* 1269 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 1270 */ 1271 /* Note: No specific macro feature on this device */ 1272 1273 /******************** Bit definition for DAC_CR register ********************/ 1274 #define DAC_CR_EN1_Pos (0U) 1275 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 1276 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ 1277 #define DAC_CR_BOFF1_Pos (1U) 1278 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 1279 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ 1280 #define DAC_CR_TEN1_Pos (2U) 1281 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 1282 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ 1283 1284 #define DAC_CR_TSEL1_Pos (3U) 1285 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 1286 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 1287 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 1288 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 1289 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 1290 1291 #define DAC_CR_DMAEN1_Pos (12U) 1292 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 1293 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ 1294 #define DAC_CR_DMAUDRIE1_Pos (13U) 1295 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 1296 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun Interrupt enable */ 1297 1298 1299 /***************** Bit definition for DAC_SWTRIGR register ******************/ 1300 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 1301 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 1302 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ 1303 1304 /***************** Bit definition for DAC_DHR12R1 register ******************/ 1305 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 1306 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 1307 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 1308 1309 /***************** Bit definition for DAC_DHR12L1 register ******************/ 1310 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 1311 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1312 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 1313 1314 /****************** Bit definition for DAC_DHR8R1 register ******************/ 1315 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 1316 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 1317 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 1318 1319 /******************* Bit definition for DAC_DOR1 register *******************/ 1320 #define DAC_DOR1_DACC1DOR_Pos (0U) 1321 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 1322 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ 1323 1324 /******************** Bit definition for DAC_SR register ********************/ 1325 #define DAC_SR_DMAUDR1_Pos (13U) 1326 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 1327 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ 1328 #define DAC_SR_DMAUDR2_Pos (29U) 1329 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 1330 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ 1331 1332 /******************************************************************************/ 1333 /* */ 1334 /* Debug MCU (DBGMCU) */ 1335 /* */ 1336 /******************************************************************************/ 1337 1338 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 1339 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 1340 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 1341 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 1342 1343 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 1344 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 1345 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 1346 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 1347 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 1348 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 1349 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 1350 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 1351 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 1352 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 1353 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 1354 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 1355 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 1356 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 1357 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 1358 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 1359 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 1360 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 1361 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 1362 1363 /****************** Bit definition for DBGMCU_CR register *******************/ 1364 #define DBGMCU_CR_DBG_STOP_Pos (1U) 1365 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 1366 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 1367 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 1368 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 1369 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 1370 1371 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 1372 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 1373 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 1374 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 1375 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 1376 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 1377 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 1378 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 1379 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 1380 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 1381 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) 1382 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ 1383 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ 1384 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 1385 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 1386 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 1387 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 1388 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 1389 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 1390 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 1391 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 1392 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 1393 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 1394 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 1395 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 1396 1397 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 1398 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) 1399 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 1400 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 1401 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) 1402 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ 1403 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */ 1404 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) 1405 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 1406 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ 1407 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) 1408 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 1409 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ 1410 1411 /******************************************************************************/ 1412 /* */ 1413 /* DMA Controller (DMA) */ 1414 /* */ 1415 /******************************************************************************/ 1416 /******************* Bit definition for DMA_ISR register ********************/ 1417 #define DMA_ISR_GIF1_Pos (0U) 1418 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1419 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1420 #define DMA_ISR_TCIF1_Pos (1U) 1421 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1422 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1423 #define DMA_ISR_HTIF1_Pos (2U) 1424 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1425 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1426 #define DMA_ISR_TEIF1_Pos (3U) 1427 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1428 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1429 #define DMA_ISR_GIF2_Pos (4U) 1430 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1431 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1432 #define DMA_ISR_TCIF2_Pos (5U) 1433 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1434 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1435 #define DMA_ISR_HTIF2_Pos (6U) 1436 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1437 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1438 #define DMA_ISR_TEIF2_Pos (7U) 1439 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1440 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1441 #define DMA_ISR_GIF3_Pos (8U) 1442 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1443 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1444 #define DMA_ISR_TCIF3_Pos (9U) 1445 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1446 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1447 #define DMA_ISR_HTIF3_Pos (10U) 1448 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1449 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1450 #define DMA_ISR_TEIF3_Pos (11U) 1451 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1452 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1453 #define DMA_ISR_GIF4_Pos (12U) 1454 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1455 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1456 #define DMA_ISR_TCIF4_Pos (13U) 1457 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1458 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1459 #define DMA_ISR_HTIF4_Pos (14U) 1460 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1461 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1462 #define DMA_ISR_TEIF4_Pos (15U) 1463 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1464 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1465 #define DMA_ISR_GIF5_Pos (16U) 1466 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1467 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1468 #define DMA_ISR_TCIF5_Pos (17U) 1469 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1470 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1471 #define DMA_ISR_HTIF5_Pos (18U) 1472 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1473 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1474 #define DMA_ISR_TEIF5_Pos (19U) 1475 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1476 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1477 1478 /******************* Bit definition for DMA_IFCR register *******************/ 1479 #define DMA_IFCR_CGIF1_Pos (0U) 1480 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1481 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1482 #define DMA_IFCR_CTCIF1_Pos (1U) 1483 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1484 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1485 #define DMA_IFCR_CHTIF1_Pos (2U) 1486 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1487 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1488 #define DMA_IFCR_CTEIF1_Pos (3U) 1489 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1490 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1491 #define DMA_IFCR_CGIF2_Pos (4U) 1492 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1493 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1494 #define DMA_IFCR_CTCIF2_Pos (5U) 1495 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1496 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1497 #define DMA_IFCR_CHTIF2_Pos (6U) 1498 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1499 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1500 #define DMA_IFCR_CTEIF2_Pos (7U) 1501 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1502 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1503 #define DMA_IFCR_CGIF3_Pos (8U) 1504 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1505 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1506 #define DMA_IFCR_CTCIF3_Pos (9U) 1507 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1508 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1509 #define DMA_IFCR_CHTIF3_Pos (10U) 1510 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1511 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1512 #define DMA_IFCR_CTEIF3_Pos (11U) 1513 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1514 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1515 #define DMA_IFCR_CGIF4_Pos (12U) 1516 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1517 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1518 #define DMA_IFCR_CTCIF4_Pos (13U) 1519 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1520 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1521 #define DMA_IFCR_CHTIF4_Pos (14U) 1522 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1523 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1524 #define DMA_IFCR_CTEIF4_Pos (15U) 1525 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1526 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1527 #define DMA_IFCR_CGIF5_Pos (16U) 1528 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1529 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1530 #define DMA_IFCR_CTCIF5_Pos (17U) 1531 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1532 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1533 #define DMA_IFCR_CHTIF5_Pos (18U) 1534 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1535 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1536 #define DMA_IFCR_CTEIF5_Pos (19U) 1537 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1538 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1539 1540 /******************* Bit definition for DMA_CCR register ********************/ 1541 #define DMA_CCR_EN_Pos (0U) 1542 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1543 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1544 #define DMA_CCR_TCIE_Pos (1U) 1545 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1546 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1547 #define DMA_CCR_HTIE_Pos (2U) 1548 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1549 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1550 #define DMA_CCR_TEIE_Pos (3U) 1551 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1552 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1553 #define DMA_CCR_DIR_Pos (4U) 1554 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1555 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1556 #define DMA_CCR_CIRC_Pos (5U) 1557 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1558 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1559 #define DMA_CCR_PINC_Pos (6U) 1560 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1561 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1562 #define DMA_CCR_MINC_Pos (7U) 1563 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1564 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1565 1566 #define DMA_CCR_PSIZE_Pos (8U) 1567 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1568 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1569 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1570 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1571 1572 #define DMA_CCR_MSIZE_Pos (10U) 1573 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1574 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1575 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1576 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1577 1578 #define DMA_CCR_PL_Pos (12U) 1579 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1580 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1581 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1582 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1583 1584 #define DMA_CCR_MEM2MEM_Pos (14U) 1585 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1586 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1587 1588 /****************** Bit definition for DMA_CNDTR register *******************/ 1589 #define DMA_CNDTR_NDT_Pos (0U) 1590 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1591 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1592 1593 /****************** Bit definition for DMA_CPAR register ********************/ 1594 #define DMA_CPAR_PA_Pos (0U) 1595 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1596 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1597 1598 /****************** Bit definition for DMA_CMAR register ********************/ 1599 #define DMA_CMAR_MA_Pos (0U) 1600 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1601 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1602 1603 /******************************************************************************/ 1604 /* */ 1605 /* External Interrupt/Event Controller (EXTI) */ 1606 /* */ 1607 /******************************************************************************/ 1608 /******************* Bit definition for EXTI_IMR register *******************/ 1609 #define EXTI_IMR_MR0_Pos (0U) 1610 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 1611 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 1612 #define EXTI_IMR_MR1_Pos (1U) 1613 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 1614 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 1615 #define EXTI_IMR_MR2_Pos (2U) 1616 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 1617 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 1618 #define EXTI_IMR_MR3_Pos (3U) 1619 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 1620 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 1621 #define EXTI_IMR_MR4_Pos (4U) 1622 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 1623 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 1624 #define EXTI_IMR_MR5_Pos (5U) 1625 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 1626 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 1627 #define EXTI_IMR_MR6_Pos (6U) 1628 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 1629 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 1630 #define EXTI_IMR_MR7_Pos (7U) 1631 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 1632 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 1633 #define EXTI_IMR_MR8_Pos (8U) 1634 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 1635 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 1636 #define EXTI_IMR_MR9_Pos (9U) 1637 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 1638 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 1639 #define EXTI_IMR_MR10_Pos (10U) 1640 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 1641 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 1642 #define EXTI_IMR_MR11_Pos (11U) 1643 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 1644 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 1645 #define EXTI_IMR_MR12_Pos (12U) 1646 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 1647 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 1648 #define EXTI_IMR_MR13_Pos (13U) 1649 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 1650 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 1651 #define EXTI_IMR_MR14_Pos (14U) 1652 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 1653 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 1654 #define EXTI_IMR_MR15_Pos (15U) 1655 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 1656 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 1657 #define EXTI_IMR_MR16_Pos (16U) 1658 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 1659 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 1660 #define EXTI_IMR_MR17_Pos (17U) 1661 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 1662 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 1663 #define EXTI_IMR_MR19_Pos (19U) 1664 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 1665 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 1666 #define EXTI_IMR_MR21_Pos (21U) 1667 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 1668 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 1669 #define EXTI_IMR_MR22_Pos (22U) 1670 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 1671 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 1672 #define EXTI_IMR_MR23_Pos (23U) 1673 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 1674 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 1675 #define EXTI_IMR_MR25_Pos (25U) 1676 #define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ 1677 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ 1678 #define EXTI_IMR_MR27_Pos (27U) 1679 #define EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ 1680 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ 1681 1682 /* References Defines */ 1683 #define EXTI_IMR_IM0 EXTI_IMR_MR0 1684 #define EXTI_IMR_IM1 EXTI_IMR_MR1 1685 #define EXTI_IMR_IM2 EXTI_IMR_MR2 1686 #define EXTI_IMR_IM3 EXTI_IMR_MR3 1687 #define EXTI_IMR_IM4 EXTI_IMR_MR4 1688 #define EXTI_IMR_IM5 EXTI_IMR_MR5 1689 #define EXTI_IMR_IM6 EXTI_IMR_MR6 1690 #define EXTI_IMR_IM7 EXTI_IMR_MR7 1691 #define EXTI_IMR_IM8 EXTI_IMR_MR8 1692 #define EXTI_IMR_IM9 EXTI_IMR_MR9 1693 #define EXTI_IMR_IM10 EXTI_IMR_MR10 1694 #define EXTI_IMR_IM11 EXTI_IMR_MR11 1695 #define EXTI_IMR_IM12 EXTI_IMR_MR12 1696 #define EXTI_IMR_IM13 EXTI_IMR_MR13 1697 #define EXTI_IMR_IM14 EXTI_IMR_MR14 1698 #define EXTI_IMR_IM15 EXTI_IMR_MR15 1699 #define EXTI_IMR_IM16 EXTI_IMR_MR16 1700 #define EXTI_IMR_IM17 EXTI_IMR_MR17 1701 #define EXTI_IMR_IM19 EXTI_IMR_MR19 1702 #define EXTI_IMR_IM21 EXTI_IMR_MR21 1703 #define EXTI_IMR_IM22 EXTI_IMR_MR22 1704 #define EXTI_IMR_IM23 EXTI_IMR_MR23 1705 #define EXTI_IMR_IM25 EXTI_IMR_MR25 1706 #define EXTI_IMR_IM27 EXTI_IMR_MR27 1707 1708 #define EXTI_IMR_IM_Pos (0U) 1709 #define EXTI_IMR_IM_Msk (0xAEFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x0AEFFFFF */ 1710 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 1711 1712 1713 /****************** Bit definition for EXTI_EMR register ********************/ 1714 #define EXTI_EMR_MR0_Pos (0U) 1715 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 1716 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 1717 #define EXTI_EMR_MR1_Pos (1U) 1718 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 1719 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 1720 #define EXTI_EMR_MR2_Pos (2U) 1721 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 1722 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 1723 #define EXTI_EMR_MR3_Pos (3U) 1724 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 1725 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 1726 #define EXTI_EMR_MR4_Pos (4U) 1727 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 1728 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 1729 #define EXTI_EMR_MR5_Pos (5U) 1730 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 1731 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 1732 #define EXTI_EMR_MR6_Pos (6U) 1733 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 1734 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 1735 #define EXTI_EMR_MR7_Pos (7U) 1736 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 1737 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 1738 #define EXTI_EMR_MR8_Pos (8U) 1739 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 1740 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 1741 #define EXTI_EMR_MR9_Pos (9U) 1742 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 1743 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 1744 #define EXTI_EMR_MR10_Pos (10U) 1745 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 1746 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 1747 #define EXTI_EMR_MR11_Pos (11U) 1748 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 1749 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 1750 #define EXTI_EMR_MR12_Pos (12U) 1751 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 1752 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 1753 #define EXTI_EMR_MR13_Pos (13U) 1754 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 1755 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 1756 #define EXTI_EMR_MR14_Pos (14U) 1757 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 1758 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 1759 #define EXTI_EMR_MR15_Pos (15U) 1760 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 1761 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 1762 #define EXTI_EMR_MR16_Pos (16U) 1763 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 1764 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 1765 #define EXTI_EMR_MR17_Pos (17U) 1766 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 1767 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 1768 #define EXTI_EMR_MR19_Pos (19U) 1769 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 1770 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 1771 #define EXTI_EMR_MR21_Pos (21U) 1772 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 1773 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 1774 #define EXTI_EMR_MR22_Pos (22U) 1775 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 1776 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 1777 #define EXTI_EMR_MR23_Pos (23U) 1778 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 1779 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 1780 #define EXTI_EMR_MR25_Pos (25U) 1781 #define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ 1782 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ 1783 #define EXTI_EMR_MR27_Pos (27U) 1784 #define EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ 1785 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ 1786 1787 /* References Defines */ 1788 #define EXTI_EMR_EM0 EXTI_EMR_MR0 1789 #define EXTI_EMR_EM1 EXTI_EMR_MR1 1790 #define EXTI_EMR_EM2 EXTI_EMR_MR2 1791 #define EXTI_EMR_EM3 EXTI_EMR_MR3 1792 #define EXTI_EMR_EM4 EXTI_EMR_MR4 1793 #define EXTI_EMR_EM5 EXTI_EMR_MR5 1794 #define EXTI_EMR_EM6 EXTI_EMR_MR6 1795 #define EXTI_EMR_EM7 EXTI_EMR_MR7 1796 #define EXTI_EMR_EM8 EXTI_EMR_MR8 1797 #define EXTI_EMR_EM9 EXTI_EMR_MR9 1798 #define EXTI_EMR_EM10 EXTI_EMR_MR10 1799 #define EXTI_EMR_EM11 EXTI_EMR_MR11 1800 #define EXTI_EMR_EM12 EXTI_EMR_MR12 1801 #define EXTI_EMR_EM13 EXTI_EMR_MR13 1802 #define EXTI_EMR_EM14 EXTI_EMR_MR14 1803 #define EXTI_EMR_EM15 EXTI_EMR_MR15 1804 #define EXTI_EMR_EM16 EXTI_EMR_MR16 1805 #define EXTI_EMR_EM17 EXTI_EMR_MR17 1806 #define EXTI_EMR_EM19 EXTI_EMR_MR19 1807 #define EXTI_EMR_EM21 EXTI_EMR_MR21 1808 #define EXTI_EMR_EM22 EXTI_EMR_MR22 1809 #define EXTI_EMR_EM23 EXTI_EMR_MR23 1810 #define EXTI_EMR_EM25 EXTI_EMR_MR25 1811 #define EXTI_EMR_EM27 EXTI_EMR_MR27 1812 1813 /******************* Bit definition for EXTI_RTSR register ******************/ 1814 #define EXTI_RTSR_TR0_Pos (0U) 1815 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 1816 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 1817 #define EXTI_RTSR_TR1_Pos (1U) 1818 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 1819 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 1820 #define EXTI_RTSR_TR2_Pos (2U) 1821 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 1822 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 1823 #define EXTI_RTSR_TR3_Pos (3U) 1824 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 1825 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 1826 #define EXTI_RTSR_TR4_Pos (4U) 1827 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 1828 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 1829 #define EXTI_RTSR_TR5_Pos (5U) 1830 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 1831 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 1832 #define EXTI_RTSR_TR6_Pos (6U) 1833 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 1834 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 1835 #define EXTI_RTSR_TR7_Pos (7U) 1836 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 1837 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 1838 #define EXTI_RTSR_TR8_Pos (8U) 1839 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 1840 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 1841 #define EXTI_RTSR_TR9_Pos (9U) 1842 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 1843 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 1844 #define EXTI_RTSR_TR10_Pos (10U) 1845 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 1846 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 1847 #define EXTI_RTSR_TR11_Pos (11U) 1848 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 1849 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 1850 #define EXTI_RTSR_TR12_Pos (12U) 1851 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 1852 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 1853 #define EXTI_RTSR_TR13_Pos (13U) 1854 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 1855 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 1856 #define EXTI_RTSR_TR14_Pos (14U) 1857 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 1858 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 1859 #define EXTI_RTSR_TR15_Pos (15U) 1860 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 1861 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 1862 #define EXTI_RTSR_TR16_Pos (16U) 1863 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 1864 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 1865 #define EXTI_RTSR_TR17_Pos (17U) 1866 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 1867 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 1868 #define EXTI_RTSR_TR19_Pos (19U) 1869 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 1870 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 1871 #define EXTI_RTSR_TR21_Pos (21U) 1872 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 1873 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 1874 #define EXTI_RTSR_TR22_Pos (22U) 1875 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 1876 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 1877 1878 /* References Defines */ 1879 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 1880 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 1881 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 1882 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 1883 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 1884 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 1885 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 1886 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 1887 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 1888 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 1889 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 1890 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 1891 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 1892 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 1893 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 1894 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 1895 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 1896 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 1897 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 1898 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 1899 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 1900 1901 /******************* Bit definition for EXTI_FTSR register *******************/ 1902 #define EXTI_FTSR_TR0_Pos (0U) 1903 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 1904 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 1905 #define EXTI_FTSR_TR1_Pos (1U) 1906 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 1907 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 1908 #define EXTI_FTSR_TR2_Pos (2U) 1909 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 1910 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 1911 #define EXTI_FTSR_TR3_Pos (3U) 1912 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 1913 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 1914 #define EXTI_FTSR_TR4_Pos (4U) 1915 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 1916 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 1917 #define EXTI_FTSR_TR5_Pos (5U) 1918 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 1919 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 1920 #define EXTI_FTSR_TR6_Pos (6U) 1921 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 1922 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 1923 #define EXTI_FTSR_TR7_Pos (7U) 1924 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 1925 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 1926 #define EXTI_FTSR_TR8_Pos (8U) 1927 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 1928 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 1929 #define EXTI_FTSR_TR9_Pos (9U) 1930 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 1931 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 1932 #define EXTI_FTSR_TR10_Pos (10U) 1933 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 1934 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 1935 #define EXTI_FTSR_TR11_Pos (11U) 1936 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 1937 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 1938 #define EXTI_FTSR_TR12_Pos (12U) 1939 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 1940 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 1941 #define EXTI_FTSR_TR13_Pos (13U) 1942 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 1943 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 1944 #define EXTI_FTSR_TR14_Pos (14U) 1945 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 1946 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 1947 #define EXTI_FTSR_TR15_Pos (15U) 1948 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 1949 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 1950 #define EXTI_FTSR_TR16_Pos (16U) 1951 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 1952 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 1953 #define EXTI_FTSR_TR17_Pos (17U) 1954 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 1955 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 1956 #define EXTI_FTSR_TR19_Pos (19U) 1957 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 1958 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 1959 #define EXTI_FTSR_TR21_Pos (21U) 1960 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 1961 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 1962 #define EXTI_FTSR_TR22_Pos (22U) 1963 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 1964 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 1965 1966 /* References Defines */ 1967 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 1968 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 1969 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 1970 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 1971 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 1972 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 1973 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 1974 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 1975 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 1976 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 1977 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 1978 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 1979 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 1980 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 1981 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 1982 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 1983 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 1984 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 1985 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 1986 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 1987 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 1988 1989 /******************* Bit definition for EXTI_SWIER register *******************/ 1990 #define EXTI_SWIER_SWIER0_Pos (0U) 1991 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 1992 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 1993 #define EXTI_SWIER_SWIER1_Pos (1U) 1994 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 1995 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 1996 #define EXTI_SWIER_SWIER2_Pos (2U) 1997 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 1998 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 1999 #define EXTI_SWIER_SWIER3_Pos (3U) 2000 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2001 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2002 #define EXTI_SWIER_SWIER4_Pos (4U) 2003 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2004 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2005 #define EXTI_SWIER_SWIER5_Pos (5U) 2006 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2007 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2008 #define EXTI_SWIER_SWIER6_Pos (6U) 2009 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2010 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2011 #define EXTI_SWIER_SWIER7_Pos (7U) 2012 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2013 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2014 #define EXTI_SWIER_SWIER8_Pos (8U) 2015 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2016 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2017 #define EXTI_SWIER_SWIER9_Pos (9U) 2018 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2019 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2020 #define EXTI_SWIER_SWIER10_Pos (10U) 2021 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 2022 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 2023 #define EXTI_SWIER_SWIER11_Pos (11U) 2024 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 2025 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 2026 #define EXTI_SWIER_SWIER12_Pos (12U) 2027 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 2028 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 2029 #define EXTI_SWIER_SWIER13_Pos (13U) 2030 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 2031 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 2032 #define EXTI_SWIER_SWIER14_Pos (14U) 2033 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 2034 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 2035 #define EXTI_SWIER_SWIER15_Pos (15U) 2036 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 2037 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 2038 #define EXTI_SWIER_SWIER16_Pos (16U) 2039 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 2040 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 2041 #define EXTI_SWIER_SWIER17_Pos (17U) 2042 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 2043 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 2044 #define EXTI_SWIER_SWIER19_Pos (19U) 2045 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 2046 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 2047 #define EXTI_SWIER_SWIER21_Pos (21U) 2048 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 2049 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 2050 #define EXTI_SWIER_SWIER22_Pos (22U) 2051 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 2052 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 2053 2054 /* References Defines */ 2055 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 2056 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 2057 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 2058 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 2059 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 2060 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 2061 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 2062 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 2063 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 2064 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 2065 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 2066 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 2067 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 2068 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 2069 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 2070 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 2071 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 2072 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 2073 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 2074 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 2075 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 2076 2077 /****************** Bit definition for EXTI_PR register *********************/ 2078 #define EXTI_PR_PR0_Pos (0U) 2079 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 2080 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ 2081 #define EXTI_PR_PR1_Pos (1U) 2082 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 2083 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ 2084 #define EXTI_PR_PR2_Pos (2U) 2085 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 2086 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ 2087 #define EXTI_PR_PR3_Pos (3U) 2088 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 2089 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ 2090 #define EXTI_PR_PR4_Pos (4U) 2091 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 2092 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ 2093 #define EXTI_PR_PR5_Pos (5U) 2094 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 2095 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ 2096 #define EXTI_PR_PR6_Pos (6U) 2097 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 2098 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ 2099 #define EXTI_PR_PR7_Pos (7U) 2100 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 2101 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ 2102 #define EXTI_PR_PR8_Pos (8U) 2103 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 2104 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ 2105 #define EXTI_PR_PR9_Pos (9U) 2106 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 2107 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ 2108 #define EXTI_PR_PR10_Pos (10U) 2109 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 2110 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ 2111 #define EXTI_PR_PR11_Pos (11U) 2112 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 2113 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ 2114 #define EXTI_PR_PR12_Pos (12U) 2115 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 2116 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ 2117 #define EXTI_PR_PR13_Pos (13U) 2118 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 2119 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ 2120 #define EXTI_PR_PR14_Pos (14U) 2121 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 2122 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ 2123 #define EXTI_PR_PR15_Pos (15U) 2124 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 2125 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ 2126 #define EXTI_PR_PR16_Pos (16U) 2127 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 2128 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ 2129 #define EXTI_PR_PR17_Pos (17U) 2130 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 2131 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ 2132 #define EXTI_PR_PR19_Pos (19U) 2133 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 2134 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ 2135 #define EXTI_PR_PR21_Pos (21U) 2136 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 2137 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */ 2138 #define EXTI_PR_PR22_Pos (22U) 2139 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 2140 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */ 2141 2142 /* References Defines */ 2143 #define EXTI_PR_PIF0 EXTI_PR_PR0 2144 #define EXTI_PR_PIF1 EXTI_PR_PR1 2145 #define EXTI_PR_PIF2 EXTI_PR_PR2 2146 #define EXTI_PR_PIF3 EXTI_PR_PR3 2147 #define EXTI_PR_PIF4 EXTI_PR_PR4 2148 #define EXTI_PR_PIF5 EXTI_PR_PR5 2149 #define EXTI_PR_PIF6 EXTI_PR_PR6 2150 #define EXTI_PR_PIF7 EXTI_PR_PR7 2151 #define EXTI_PR_PIF8 EXTI_PR_PR8 2152 #define EXTI_PR_PIF9 EXTI_PR_PR9 2153 #define EXTI_PR_PIF10 EXTI_PR_PR10 2154 #define EXTI_PR_PIF11 EXTI_PR_PR11 2155 #define EXTI_PR_PIF12 EXTI_PR_PR12 2156 #define EXTI_PR_PIF13 EXTI_PR_PR13 2157 #define EXTI_PR_PIF14 EXTI_PR_PR14 2158 #define EXTI_PR_PIF15 EXTI_PR_PR15 2159 #define EXTI_PR_PIF16 EXTI_PR_PR16 2160 #define EXTI_PR_PIF17 EXTI_PR_PR17 2161 #define EXTI_PR_PIF19 EXTI_PR_PR19 2162 #define EXTI_PR_PIF21 EXTI_PR_PR21 2163 #define EXTI_PR_PIF22 EXTI_PR_PR22 2164 2165 /******************************************************************************/ 2166 /* */ 2167 /* FLASH and Option Bytes Registers */ 2168 /* */ 2169 /******************************************************************************/ 2170 2171 /******************* Bit definition for FLASH_ACR register ******************/ 2172 #define FLASH_ACR_LATENCY_Pos (0U) 2173 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 2174 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 2175 2176 #define FLASH_ACR_PRFTBE_Pos (4U) 2177 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 2178 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 2179 #define FLASH_ACR_PRFTBS_Pos (5U) 2180 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 2181 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 2182 2183 /****************** Bit definition for FLASH_KEYR register ******************/ 2184 #define FLASH_KEYR_FKEYR_Pos (0U) 2185 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 2186 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 2187 2188 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 2189 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 2190 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 2191 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 2192 2193 /****************** FLASH Keys **********************************************/ 2194 #define FLASH_KEY1_Pos (0U) 2195 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 2196 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ 2197 #define FLASH_KEY2_Pos (0U) 2198 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 2199 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 2200 to unlock the write access to the FPEC. */ 2201 2202 #define FLASH_OPTKEY1_Pos (0U) 2203 #define FLASH_OPTKEY1_Msk (0x45670123UL << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ 2204 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ 2205 #define FLASH_OPTKEY2_Pos (0U) 2206 #define FLASH_OPTKEY2_Msk (0xCDEF89ABUL << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ 2207 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to 2208 unlock the write access to the option byte block */ 2209 2210 /****************** Bit definition for FLASH_SR register *******************/ 2211 #define FLASH_SR_BSY_Pos (0U) 2212 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 2213 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 2214 #define FLASH_SR_PGERR_Pos (2U) 2215 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 2216 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 2217 #define FLASH_SR_WRPRTERR_Pos (4U) 2218 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 2219 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 2220 #define FLASH_SR_EOP_Pos (5U) 2221 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 2222 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 2223 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ 2224 2225 /******************* Bit definition for FLASH_CR register *******************/ 2226 #define FLASH_CR_PG_Pos (0U) 2227 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 2228 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 2229 #define FLASH_CR_PER_Pos (1U) 2230 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 2231 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 2232 #define FLASH_CR_MER_Pos (2U) 2233 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 2234 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 2235 #define FLASH_CR_OPTPG_Pos (4U) 2236 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 2237 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 2238 #define FLASH_CR_OPTER_Pos (5U) 2239 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 2240 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 2241 #define FLASH_CR_STRT_Pos (6U) 2242 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 2243 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 2244 #define FLASH_CR_LOCK_Pos (7U) 2245 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 2246 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 2247 #define FLASH_CR_OPTWRE_Pos (9U) 2248 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 2249 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 2250 #define FLASH_CR_ERRIE_Pos (10U) 2251 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 2252 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 2253 #define FLASH_CR_EOPIE_Pos (12U) 2254 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 2255 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 2256 #define FLASH_CR_OBL_LAUNCH_Pos (13U) 2257 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ 2258 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ 2259 2260 /******************* Bit definition for FLASH_AR register *******************/ 2261 #define FLASH_AR_FAR_Pos (0U) 2262 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 2263 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 2264 2265 /****************** Bit definition for FLASH_OBR register *******************/ 2266 #define FLASH_OBR_OPTERR_Pos (0U) 2267 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 2268 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 2269 #define FLASH_OBR_RDPRT1_Pos (1U) 2270 #define FLASH_OBR_RDPRT1_Msk (0x1UL << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ 2271 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ 2272 #define FLASH_OBR_RDPRT2_Pos (2U) 2273 #define FLASH_OBR_RDPRT2_Msk (0x1UL << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ 2274 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ 2275 2276 #define FLASH_OBR_USER_Pos (8U) 2277 #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ 2278 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 2279 #define FLASH_OBR_IWDG_SW_Pos (8U) 2280 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ 2281 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 2282 #define FLASH_OBR_nRST_STOP_Pos (9U) 2283 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ 2284 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 2285 #define FLASH_OBR_nRST_STDBY_Pos (10U) 2286 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ 2287 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 2288 #define FLASH_OBR_nBOOT1_Pos (12U) 2289 #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ 2290 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ 2291 #define FLASH_OBR_VDDA_MONITOR_Pos (13U) 2292 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ 2293 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ 2294 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) 2295 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ 2296 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ 2297 #define FLASH_OBR_DATA0_Pos (16U) 2298 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ 2299 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 2300 #define FLASH_OBR_DATA1_Pos (24U) 2301 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ 2302 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 2303 2304 /* Old BOOT1 bit definition, maintained for legacy purpose */ 2305 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 2306 2307 /* Old OBR_VDDA bit definition, maintained for legacy purpose */ 2308 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR 2309 2310 /****************** Bit definition for FLASH_WRPR register ******************/ 2311 #define FLASH_WRPR_WRP_Pos (0U) 2312 #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 2313 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 2314 2315 /*----------------------------------------------------------------------------*/ 2316 2317 /****************** Bit definition for OB_RDP register **********************/ 2318 #define OB_RDP_RDP_Pos (0U) 2319 #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ 2320 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ 2321 #define OB_RDP_nRDP_Pos (8U) 2322 #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 2323 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 2324 2325 /****************** Bit definition for OB_USER register *********************/ 2326 #define OB_USER_USER_Pos (16U) 2327 #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ 2328 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ 2329 #define OB_USER_nUSER_Pos (24U) 2330 #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ 2331 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ 2332 2333 /****************** Bit definition for OB_WRP0 register *********************/ 2334 #define OB_WRP0_WRP0_Pos (0U) 2335 #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ 2336 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 2337 #define OB_WRP0_nWRP0_Pos (8U) 2338 #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 2339 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 2340 2341 /****************** Bit definition for OB_WRP1 register *********************/ 2342 #define OB_WRP1_WRP1_Pos (16U) 2343 #define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 2344 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 2345 #define OB_WRP1_nWRP1_Pos (24U) 2346 #define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 2347 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 2348 2349 /******************************************************************************/ 2350 /* */ 2351 /* General Purpose IOs (GPIO) */ 2352 /* */ 2353 /******************************************************************************/ 2354 /******************* Bit definition for GPIO_MODER register *****************/ 2355 #define GPIO_MODER_MODER0_Pos (0U) 2356 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 2357 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 2358 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 2359 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 2360 #define GPIO_MODER_MODER1_Pos (2U) 2361 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 2362 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 2363 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 2364 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 2365 #define GPIO_MODER_MODER2_Pos (4U) 2366 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 2367 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 2368 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 2369 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 2370 #define GPIO_MODER_MODER3_Pos (6U) 2371 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 2372 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 2373 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 2374 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 2375 #define GPIO_MODER_MODER4_Pos (8U) 2376 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 2377 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 2378 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 2379 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 2380 #define GPIO_MODER_MODER5_Pos (10U) 2381 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 2382 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 2383 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 2384 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 2385 #define GPIO_MODER_MODER6_Pos (12U) 2386 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 2387 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 2388 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 2389 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 2390 #define GPIO_MODER_MODER7_Pos (14U) 2391 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 2392 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 2393 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 2394 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 2395 #define GPIO_MODER_MODER8_Pos (16U) 2396 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 2397 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 2398 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 2399 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 2400 #define GPIO_MODER_MODER9_Pos (18U) 2401 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 2402 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 2403 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 2404 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 2405 #define GPIO_MODER_MODER10_Pos (20U) 2406 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 2407 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 2408 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 2409 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 2410 #define GPIO_MODER_MODER11_Pos (22U) 2411 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 2412 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 2413 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 2414 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 2415 #define GPIO_MODER_MODER12_Pos (24U) 2416 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 2417 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 2418 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 2419 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 2420 #define GPIO_MODER_MODER13_Pos (26U) 2421 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 2422 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 2423 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 2424 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 2425 #define GPIO_MODER_MODER14_Pos (28U) 2426 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 2427 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 2428 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 2429 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 2430 #define GPIO_MODER_MODER15_Pos (30U) 2431 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 2432 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 2433 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 2434 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 2435 2436 /****************** Bit definition for GPIO_OTYPER register *****************/ 2437 #define GPIO_OTYPER_OT_0 (0x00000001U) 2438 #define GPIO_OTYPER_OT_1 (0x00000002U) 2439 #define GPIO_OTYPER_OT_2 (0x00000004U) 2440 #define GPIO_OTYPER_OT_3 (0x00000008U) 2441 #define GPIO_OTYPER_OT_4 (0x00000010U) 2442 #define GPIO_OTYPER_OT_5 (0x00000020U) 2443 #define GPIO_OTYPER_OT_6 (0x00000040U) 2444 #define GPIO_OTYPER_OT_7 (0x00000080U) 2445 #define GPIO_OTYPER_OT_8 (0x00000100U) 2446 #define GPIO_OTYPER_OT_9 (0x00000200U) 2447 #define GPIO_OTYPER_OT_10 (0x00000400U) 2448 #define GPIO_OTYPER_OT_11 (0x00000800U) 2449 #define GPIO_OTYPER_OT_12 (0x00001000U) 2450 #define GPIO_OTYPER_OT_13 (0x00002000U) 2451 #define GPIO_OTYPER_OT_14 (0x00004000U) 2452 #define GPIO_OTYPER_OT_15 (0x00008000U) 2453 2454 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 2455 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) 2456 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ 2457 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk 2458 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ 2459 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ 2460 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) 2461 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ 2462 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk 2463 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ 2464 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ 2465 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) 2466 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ 2467 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk 2468 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ 2469 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ 2470 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) 2471 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ 2472 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk 2473 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ 2474 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ 2475 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) 2476 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ 2477 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk 2478 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ 2479 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ 2480 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) 2481 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ 2482 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk 2483 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ 2484 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ 2485 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) 2486 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ 2487 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk 2488 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ 2489 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ 2490 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) 2491 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ 2492 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk 2493 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ 2494 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ 2495 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) 2496 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ 2497 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk 2498 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ 2499 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ 2500 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) 2501 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ 2502 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk 2503 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ 2504 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ 2505 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) 2506 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ 2507 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk 2508 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ 2509 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ 2510 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) 2511 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ 2512 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk 2513 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ 2514 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ 2515 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) 2516 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ 2517 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk 2518 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ 2519 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ 2520 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) 2521 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ 2522 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk 2523 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ 2524 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ 2525 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) 2526 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ 2527 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk 2528 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ 2529 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ 2530 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) 2531 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ 2532 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk 2533 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ 2534 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ 2535 2536 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ 2537 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 2538 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 2539 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 2540 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 2541 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 2542 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 2543 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 2544 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 2545 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 2546 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 2547 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 2548 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 2549 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 2550 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 2551 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 2552 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 2553 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 2554 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 2555 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 2556 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 2557 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 2558 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 2559 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 2560 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 2561 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 2562 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 2563 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 2564 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 2565 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 2566 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 2567 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 2568 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 2569 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 2570 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 2571 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 2572 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 2573 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 2574 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 2575 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 2576 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 2577 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 2578 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 2579 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 2580 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 2581 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 2582 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 2583 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 2584 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 2585 2586 /******************* Bit definition for GPIO_PUPDR register ******************/ 2587 #define GPIO_PUPDR_PUPDR0_Pos (0U) 2588 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 2589 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 2590 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 2591 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 2592 #define GPIO_PUPDR_PUPDR1_Pos (2U) 2593 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 2594 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 2595 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 2596 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 2597 #define GPIO_PUPDR_PUPDR2_Pos (4U) 2598 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 2599 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 2600 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 2601 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 2602 #define GPIO_PUPDR_PUPDR3_Pos (6U) 2603 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 2604 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 2605 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 2606 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 2607 #define GPIO_PUPDR_PUPDR4_Pos (8U) 2608 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 2609 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 2610 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 2611 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 2612 #define GPIO_PUPDR_PUPDR5_Pos (10U) 2613 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 2614 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 2615 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 2616 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 2617 #define GPIO_PUPDR_PUPDR6_Pos (12U) 2618 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 2619 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 2620 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 2621 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 2622 #define GPIO_PUPDR_PUPDR7_Pos (14U) 2623 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 2624 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 2625 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 2626 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 2627 #define GPIO_PUPDR_PUPDR8_Pos (16U) 2628 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 2629 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 2630 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 2631 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 2632 #define GPIO_PUPDR_PUPDR9_Pos (18U) 2633 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 2634 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 2635 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 2636 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 2637 #define GPIO_PUPDR_PUPDR10_Pos (20U) 2638 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 2639 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 2640 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 2641 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 2642 #define GPIO_PUPDR_PUPDR11_Pos (22U) 2643 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 2644 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 2645 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 2646 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 2647 #define GPIO_PUPDR_PUPDR12_Pos (24U) 2648 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 2649 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 2650 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 2651 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 2652 #define GPIO_PUPDR_PUPDR13_Pos (26U) 2653 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 2654 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 2655 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 2656 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 2657 #define GPIO_PUPDR_PUPDR14_Pos (28U) 2658 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 2659 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 2660 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 2661 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 2662 #define GPIO_PUPDR_PUPDR15_Pos (30U) 2663 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 2664 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 2665 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 2666 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 2667 2668 /******************* Bit definition for GPIO_IDR register *******************/ 2669 #define GPIO_IDR_0 (0x00000001U) 2670 #define GPIO_IDR_1 (0x00000002U) 2671 #define GPIO_IDR_2 (0x00000004U) 2672 #define GPIO_IDR_3 (0x00000008U) 2673 #define GPIO_IDR_4 (0x00000010U) 2674 #define GPIO_IDR_5 (0x00000020U) 2675 #define GPIO_IDR_6 (0x00000040U) 2676 #define GPIO_IDR_7 (0x00000080U) 2677 #define GPIO_IDR_8 (0x00000100U) 2678 #define GPIO_IDR_9 (0x00000200U) 2679 #define GPIO_IDR_10 (0x00000400U) 2680 #define GPIO_IDR_11 (0x00000800U) 2681 #define GPIO_IDR_12 (0x00001000U) 2682 #define GPIO_IDR_13 (0x00002000U) 2683 #define GPIO_IDR_14 (0x00004000U) 2684 #define GPIO_IDR_15 (0x00008000U) 2685 2686 /****************** Bit definition for GPIO_ODR register ********************/ 2687 #define GPIO_ODR_0 (0x00000001U) 2688 #define GPIO_ODR_1 (0x00000002U) 2689 #define GPIO_ODR_2 (0x00000004U) 2690 #define GPIO_ODR_3 (0x00000008U) 2691 #define GPIO_ODR_4 (0x00000010U) 2692 #define GPIO_ODR_5 (0x00000020U) 2693 #define GPIO_ODR_6 (0x00000040U) 2694 #define GPIO_ODR_7 (0x00000080U) 2695 #define GPIO_ODR_8 (0x00000100U) 2696 #define GPIO_ODR_9 (0x00000200U) 2697 #define GPIO_ODR_10 (0x00000400U) 2698 #define GPIO_ODR_11 (0x00000800U) 2699 #define GPIO_ODR_12 (0x00001000U) 2700 #define GPIO_ODR_13 (0x00002000U) 2701 #define GPIO_ODR_14 (0x00004000U) 2702 #define GPIO_ODR_15 (0x00008000U) 2703 2704 /****************** Bit definition for GPIO_BSRR register ********************/ 2705 #define GPIO_BSRR_BS_0 (0x00000001U) 2706 #define GPIO_BSRR_BS_1 (0x00000002U) 2707 #define GPIO_BSRR_BS_2 (0x00000004U) 2708 #define GPIO_BSRR_BS_3 (0x00000008U) 2709 #define GPIO_BSRR_BS_4 (0x00000010U) 2710 #define GPIO_BSRR_BS_5 (0x00000020U) 2711 #define GPIO_BSRR_BS_6 (0x00000040U) 2712 #define GPIO_BSRR_BS_7 (0x00000080U) 2713 #define GPIO_BSRR_BS_8 (0x00000100U) 2714 #define GPIO_BSRR_BS_9 (0x00000200U) 2715 #define GPIO_BSRR_BS_10 (0x00000400U) 2716 #define GPIO_BSRR_BS_11 (0x00000800U) 2717 #define GPIO_BSRR_BS_12 (0x00001000U) 2718 #define GPIO_BSRR_BS_13 (0x00002000U) 2719 #define GPIO_BSRR_BS_14 (0x00004000U) 2720 #define GPIO_BSRR_BS_15 (0x00008000U) 2721 #define GPIO_BSRR_BR_0 (0x00010000U) 2722 #define GPIO_BSRR_BR_1 (0x00020000U) 2723 #define GPIO_BSRR_BR_2 (0x00040000U) 2724 #define GPIO_BSRR_BR_3 (0x00080000U) 2725 #define GPIO_BSRR_BR_4 (0x00100000U) 2726 #define GPIO_BSRR_BR_5 (0x00200000U) 2727 #define GPIO_BSRR_BR_6 (0x00400000U) 2728 #define GPIO_BSRR_BR_7 (0x00800000U) 2729 #define GPIO_BSRR_BR_8 (0x01000000U) 2730 #define GPIO_BSRR_BR_9 (0x02000000U) 2731 #define GPIO_BSRR_BR_10 (0x04000000U) 2732 #define GPIO_BSRR_BR_11 (0x08000000U) 2733 #define GPIO_BSRR_BR_12 (0x10000000U) 2734 #define GPIO_BSRR_BR_13 (0x20000000U) 2735 #define GPIO_BSRR_BR_14 (0x40000000U) 2736 #define GPIO_BSRR_BR_15 (0x80000000U) 2737 2738 /****************** Bit definition for GPIO_LCKR register ********************/ 2739 #define GPIO_LCKR_LCK0_Pos (0U) 2740 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2741 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2742 #define GPIO_LCKR_LCK1_Pos (1U) 2743 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2744 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2745 #define GPIO_LCKR_LCK2_Pos (2U) 2746 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2747 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2748 #define GPIO_LCKR_LCK3_Pos (3U) 2749 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2750 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2751 #define GPIO_LCKR_LCK4_Pos (4U) 2752 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2753 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 2754 #define GPIO_LCKR_LCK5_Pos (5U) 2755 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2756 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 2757 #define GPIO_LCKR_LCK6_Pos (6U) 2758 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2759 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 2760 #define GPIO_LCKR_LCK7_Pos (7U) 2761 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2762 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 2763 #define GPIO_LCKR_LCK8_Pos (8U) 2764 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2765 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 2766 #define GPIO_LCKR_LCK9_Pos (9U) 2767 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2768 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 2769 #define GPIO_LCKR_LCK10_Pos (10U) 2770 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2771 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 2772 #define GPIO_LCKR_LCK11_Pos (11U) 2773 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2774 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 2775 #define GPIO_LCKR_LCK12_Pos (12U) 2776 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2777 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 2778 #define GPIO_LCKR_LCK13_Pos (13U) 2779 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2780 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 2781 #define GPIO_LCKR_LCK14_Pos (14U) 2782 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2783 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 2784 #define GPIO_LCKR_LCK15_Pos (15U) 2785 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2786 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 2787 #define GPIO_LCKR_LCKK_Pos (16U) 2788 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2789 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 2790 2791 /****************** Bit definition for GPIO_AFRL register ********************/ 2792 #define GPIO_AFRL_AFSEL0_Pos (0U) 2793 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 2794 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 2795 #define GPIO_AFRL_AFSEL1_Pos (4U) 2796 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 2797 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 2798 #define GPIO_AFRL_AFSEL2_Pos (8U) 2799 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 2800 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 2801 #define GPIO_AFRL_AFSEL3_Pos (12U) 2802 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 2803 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 2804 #define GPIO_AFRL_AFSEL4_Pos (16U) 2805 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 2806 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 2807 #define GPIO_AFRL_AFSEL5_Pos (20U) 2808 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 2809 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 2810 #define GPIO_AFRL_AFSEL6_Pos (24U) 2811 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 2812 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 2813 #define GPIO_AFRL_AFSEL7_Pos (28U) 2814 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 2815 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 2816 2817 /* Legacy aliases */ 2818 #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos 2819 #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk 2820 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 2821 #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos 2822 #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk 2823 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 2824 #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos 2825 #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk 2826 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 2827 #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos 2828 #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk 2829 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 2830 #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos 2831 #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk 2832 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 2833 #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos 2834 #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk 2835 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 2836 #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos 2837 #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk 2838 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 2839 #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos 2840 #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk 2841 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 2842 2843 /****************** Bit definition for GPIO_AFRH register ********************/ 2844 #define GPIO_AFRH_AFSEL8_Pos (0U) 2845 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 2846 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 2847 #define GPIO_AFRH_AFSEL9_Pos (4U) 2848 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 2849 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 2850 #define GPIO_AFRH_AFSEL10_Pos (8U) 2851 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 2852 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 2853 #define GPIO_AFRH_AFSEL11_Pos (12U) 2854 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 2855 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 2856 #define GPIO_AFRH_AFSEL12_Pos (16U) 2857 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 2858 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 2859 #define GPIO_AFRH_AFSEL13_Pos (20U) 2860 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 2861 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 2862 #define GPIO_AFRH_AFSEL14_Pos (24U) 2863 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 2864 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 2865 #define GPIO_AFRH_AFSEL15_Pos (28U) 2866 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 2867 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 2868 2869 /* Legacy aliases */ 2870 #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos 2871 #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk 2872 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 2873 #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos 2874 #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk 2875 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 2876 #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos 2877 #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk 2878 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 2879 #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos 2880 #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk 2881 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 2882 #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos 2883 #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk 2884 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 2885 #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos 2886 #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk 2887 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 2888 #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos 2889 #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk 2890 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 2891 #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos 2892 #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk 2893 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 2894 2895 /****************** Bit definition for GPIO_BRR register *********************/ 2896 #define GPIO_BRR_BR_0 (0x00000001U) 2897 #define GPIO_BRR_BR_1 (0x00000002U) 2898 #define GPIO_BRR_BR_2 (0x00000004U) 2899 #define GPIO_BRR_BR_3 (0x00000008U) 2900 #define GPIO_BRR_BR_4 (0x00000010U) 2901 #define GPIO_BRR_BR_5 (0x00000020U) 2902 #define GPIO_BRR_BR_6 (0x00000040U) 2903 #define GPIO_BRR_BR_7 (0x00000080U) 2904 #define GPIO_BRR_BR_8 (0x00000100U) 2905 #define GPIO_BRR_BR_9 (0x00000200U) 2906 #define GPIO_BRR_BR_10 (0x00000400U) 2907 #define GPIO_BRR_BR_11 (0x00000800U) 2908 #define GPIO_BRR_BR_12 (0x00001000U) 2909 #define GPIO_BRR_BR_13 (0x00002000U) 2910 #define GPIO_BRR_BR_14 (0x00004000U) 2911 #define GPIO_BRR_BR_15 (0x00008000U) 2912 2913 /******************************************************************************/ 2914 /* */ 2915 /* Inter-integrated Circuit Interface (I2C) */ 2916 /* */ 2917 /******************************************************************************/ 2918 2919 /******************* Bit definition for I2C_CR1 register *******************/ 2920 #define I2C_CR1_PE_Pos (0U) 2921 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 2922 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 2923 #define I2C_CR1_TXIE_Pos (1U) 2924 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 2925 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 2926 #define I2C_CR1_RXIE_Pos (2U) 2927 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 2928 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 2929 #define I2C_CR1_ADDRIE_Pos (3U) 2930 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 2931 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 2932 #define I2C_CR1_NACKIE_Pos (4U) 2933 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 2934 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 2935 #define I2C_CR1_STOPIE_Pos (5U) 2936 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 2937 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 2938 #define I2C_CR1_TCIE_Pos (6U) 2939 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 2940 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 2941 #define I2C_CR1_ERRIE_Pos (7U) 2942 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 2943 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 2944 #define I2C_CR1_DNF_Pos (8U) 2945 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 2946 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 2947 #define I2C_CR1_ANFOFF_Pos (12U) 2948 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 2949 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 2950 #define I2C_CR1_SWRST_Pos (13U) 2951 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 2952 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 2953 #define I2C_CR1_TXDMAEN_Pos (14U) 2954 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 2955 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 2956 #define I2C_CR1_RXDMAEN_Pos (15U) 2957 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 2958 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 2959 #define I2C_CR1_SBC_Pos (16U) 2960 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 2961 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 2962 #define I2C_CR1_NOSTRETCH_Pos (17U) 2963 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 2964 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 2965 #define I2C_CR1_WUPEN_Pos (18U) 2966 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 2967 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 2968 #define I2C_CR1_GCEN_Pos (19U) 2969 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 2970 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 2971 #define I2C_CR1_SMBHEN_Pos (20U) 2972 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 2973 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 2974 #define I2C_CR1_SMBDEN_Pos (21U) 2975 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 2976 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 2977 #define I2C_CR1_ALERTEN_Pos (22U) 2978 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 2979 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 2980 #define I2C_CR1_PECEN_Pos (23U) 2981 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 2982 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 2983 2984 /****************** Bit definition for I2C_CR2 register ********************/ 2985 #define I2C_CR2_SADD_Pos (0U) 2986 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 2987 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 2988 #define I2C_CR2_RD_WRN_Pos (10U) 2989 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 2990 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 2991 #define I2C_CR2_ADD10_Pos (11U) 2992 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 2993 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 2994 #define I2C_CR2_HEAD10R_Pos (12U) 2995 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 2996 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 2997 #define I2C_CR2_START_Pos (13U) 2998 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 2999 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 3000 #define I2C_CR2_STOP_Pos (14U) 3001 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 3002 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 3003 #define I2C_CR2_NACK_Pos (15U) 3004 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 3005 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 3006 #define I2C_CR2_NBYTES_Pos (16U) 3007 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 3008 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 3009 #define I2C_CR2_RELOAD_Pos (24U) 3010 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 3011 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 3012 #define I2C_CR2_AUTOEND_Pos (25U) 3013 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 3014 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 3015 #define I2C_CR2_PECBYTE_Pos (26U) 3016 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 3017 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 3018 3019 /******************* Bit definition for I2C_OAR1 register ******************/ 3020 #define I2C_OAR1_OA1_Pos (0U) 3021 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 3022 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 3023 #define I2C_OAR1_OA1MODE_Pos (10U) 3024 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 3025 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 3026 #define I2C_OAR1_OA1EN_Pos (15U) 3027 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 3028 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 3029 3030 /******************* Bit definition for I2C_OAR2 register ******************/ 3031 #define I2C_OAR2_OA2_Pos (1U) 3032 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 3033 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 3034 #define I2C_OAR2_OA2MSK_Pos (8U) 3035 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 3036 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 3037 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 3038 #define I2C_OAR2_OA2MASK01_Pos (8U) 3039 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 3040 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 3041 #define I2C_OAR2_OA2MASK02_Pos (9U) 3042 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 3043 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 3044 #define I2C_OAR2_OA2MASK03_Pos (8U) 3045 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 3046 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 3047 #define I2C_OAR2_OA2MASK04_Pos (10U) 3048 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 3049 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 3050 #define I2C_OAR2_OA2MASK05_Pos (8U) 3051 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 3052 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 3053 #define I2C_OAR2_OA2MASK06_Pos (9U) 3054 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 3055 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 3056 #define I2C_OAR2_OA2MASK07_Pos (8U) 3057 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 3058 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 3059 #define I2C_OAR2_OA2EN_Pos (15U) 3060 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 3061 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 3062 3063 /******************* Bit definition for I2C_TIMINGR register ****************/ 3064 #define I2C_TIMINGR_SCLL_Pos (0U) 3065 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 3066 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 3067 #define I2C_TIMINGR_SCLH_Pos (8U) 3068 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 3069 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 3070 #define I2C_TIMINGR_SDADEL_Pos (16U) 3071 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 3072 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 3073 #define I2C_TIMINGR_SCLDEL_Pos (20U) 3074 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 3075 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 3076 #define I2C_TIMINGR_PRESC_Pos (28U) 3077 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 3078 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 3079 3080 /******************* Bit definition for I2C_TIMEOUTR register ****************/ 3081 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 3082 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 3083 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 3084 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 3085 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 3086 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 3087 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 3088 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 3089 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 3090 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 3091 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 3092 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 3093 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 3094 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 3095 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 3096 3097 /****************** Bit definition for I2C_ISR register ********************/ 3098 #define I2C_ISR_TXE_Pos (0U) 3099 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 3100 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 3101 #define I2C_ISR_TXIS_Pos (1U) 3102 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 3103 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 3104 #define I2C_ISR_RXNE_Pos (2U) 3105 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 3106 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 3107 #define I2C_ISR_ADDR_Pos (3U) 3108 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 3109 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 3110 #define I2C_ISR_NACKF_Pos (4U) 3111 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 3112 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 3113 #define I2C_ISR_STOPF_Pos (5U) 3114 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 3115 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 3116 #define I2C_ISR_TC_Pos (6U) 3117 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 3118 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 3119 #define I2C_ISR_TCR_Pos (7U) 3120 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 3121 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 3122 #define I2C_ISR_BERR_Pos (8U) 3123 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 3124 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 3125 #define I2C_ISR_ARLO_Pos (9U) 3126 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 3127 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 3128 #define I2C_ISR_OVR_Pos (10U) 3129 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 3130 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 3131 #define I2C_ISR_PECERR_Pos (11U) 3132 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 3133 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 3134 #define I2C_ISR_TIMEOUT_Pos (12U) 3135 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 3136 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 3137 #define I2C_ISR_ALERT_Pos (13U) 3138 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 3139 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 3140 #define I2C_ISR_BUSY_Pos (15U) 3141 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 3142 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 3143 #define I2C_ISR_DIR_Pos (16U) 3144 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 3145 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 3146 #define I2C_ISR_ADDCODE_Pos (17U) 3147 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 3148 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 3149 3150 /****************** Bit definition for I2C_ICR register ********************/ 3151 #define I2C_ICR_ADDRCF_Pos (3U) 3152 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 3153 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 3154 #define I2C_ICR_NACKCF_Pos (4U) 3155 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 3156 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 3157 #define I2C_ICR_STOPCF_Pos (5U) 3158 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 3159 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 3160 #define I2C_ICR_BERRCF_Pos (8U) 3161 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 3162 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 3163 #define I2C_ICR_ARLOCF_Pos (9U) 3164 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 3165 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 3166 #define I2C_ICR_OVRCF_Pos (10U) 3167 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 3168 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 3169 #define I2C_ICR_PECCF_Pos (11U) 3170 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 3171 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 3172 #define I2C_ICR_TIMOUTCF_Pos (12U) 3173 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 3174 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 3175 #define I2C_ICR_ALERTCF_Pos (13U) 3176 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 3177 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 3178 3179 /****************** Bit definition for I2C_PECR register *******************/ 3180 #define I2C_PECR_PEC_Pos (0U) 3181 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 3182 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 3183 3184 /****************** Bit definition for I2C_RXDR register *********************/ 3185 #define I2C_RXDR_RXDATA_Pos (0U) 3186 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 3187 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 3188 3189 /****************** Bit definition for I2C_TXDR register *******************/ 3190 #define I2C_TXDR_TXDATA_Pos (0U) 3191 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 3192 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 3193 3194 /*****************************************************************************/ 3195 /* */ 3196 /* Independent WATCHDOG (IWDG) */ 3197 /* */ 3198 /*****************************************************************************/ 3199 /******************* Bit definition for IWDG_KR register *******************/ 3200 #define IWDG_KR_KEY_Pos (0U) 3201 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3202 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 3203 3204 /******************* Bit definition for IWDG_PR register *******************/ 3205 #define IWDG_PR_PR_Pos (0U) 3206 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3207 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 3208 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */ 3209 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */ 3210 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */ 3211 3212 /******************* Bit definition for IWDG_RLR register ******************/ 3213 #define IWDG_RLR_RL_Pos (0U) 3214 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3215 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 3216 3217 /******************* Bit definition for IWDG_SR register *******************/ 3218 #define IWDG_SR_PVU_Pos (0U) 3219 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3220 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3221 #define IWDG_SR_RVU_Pos (1U) 3222 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3223 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3224 #define IWDG_SR_WVU_Pos (2U) 3225 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 3226 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 3227 3228 /******************* Bit definition for IWDG_KR register *******************/ 3229 #define IWDG_WINR_WIN_Pos (0U) 3230 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 3231 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 3232 3233 /*****************************************************************************/ 3234 /* */ 3235 /* Power Control (PWR) */ 3236 /* */ 3237 /*****************************************************************************/ 3238 3239 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ 3240 3241 3242 /******************** Bit definition for PWR_CR register *******************/ 3243 #define PWR_CR_LPDS_Pos (0U) 3244 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 3245 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ 3246 #define PWR_CR_PDDS_Pos (1U) 3247 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 3248 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 3249 #define PWR_CR_CWUF_Pos (2U) 3250 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 3251 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 3252 #define PWR_CR_CSBF_Pos (3U) 3253 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 3254 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 3255 #define PWR_CR_PVDE_Pos (4U) 3256 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 3257 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 3258 3259 #define PWR_CR_PLS_Pos (5U) 3260 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 3261 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 3262 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 3263 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 3264 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 3265 3266 /*!< PVD level configuration */ 3267 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 3268 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 3269 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 3270 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 3271 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 3272 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 3273 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 3274 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 3275 3276 #define PWR_CR_DBP_Pos (8U) 3277 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 3278 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 3279 3280 /******************* Bit definition for PWR_CSR register *******************/ 3281 #define PWR_CSR_WUF_Pos (0U) 3282 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 3283 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 3284 #define PWR_CSR_SBF_Pos (1U) 3285 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 3286 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 3287 #define PWR_CSR_PVDO_Pos (2U) 3288 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 3289 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 3290 #define PWR_CSR_VREFINTRDYF_Pos (3U) 3291 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 3292 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 3293 3294 #define PWR_CSR_EWUP1_Pos (8U) 3295 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 3296 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3297 #define PWR_CSR_EWUP2_Pos (9U) 3298 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 3299 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 3300 3301 /*****************************************************************************/ 3302 /* */ 3303 /* Reset and Clock Control */ 3304 /* */ 3305 /*****************************************************************************/ 3306 /* 3307 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 3308 */ 3309 3310 /******************** Bit definition for RCC_CR register *******************/ 3311 #define RCC_CR_HSION_Pos (0U) 3312 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 3313 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3314 #define RCC_CR_HSIRDY_Pos (1U) 3315 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 3316 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3317 3318 #define RCC_CR_HSITRIM_Pos (3U) 3319 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 3320 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 3321 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 3322 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 3323 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 3324 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 3325 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 3326 3327 #define RCC_CR_HSICAL_Pos (8U) 3328 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 3329 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 3330 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 3331 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 3332 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 3333 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 3334 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 3335 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 3336 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 3337 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 3338 3339 #define RCC_CR_HSEON_Pos (16U) 3340 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3341 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3342 #define RCC_CR_HSERDY_Pos (17U) 3343 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3344 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 3345 #define RCC_CR_HSEBYP_Pos (18U) 3346 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3347 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3348 #define RCC_CR_CSSON_Pos (19U) 3349 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 3350 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 3351 #define RCC_CR_PLLON_Pos (24U) 3352 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 3353 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 3354 #define RCC_CR_PLLRDY_Pos (25U) 3355 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 3356 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 3357 3358 /******************** Bit definition for RCC_CFGR register *****************/ 3359 /*!< SW configuration */ 3360 #define RCC_CFGR_SW_Pos (0U) 3361 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 3362 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 3363 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 3364 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 3365 3366 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ 3367 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ 3368 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ 3369 3370 /*!< SWS configuration */ 3371 #define RCC_CFGR_SWS_Pos (2U) 3372 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 3373 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 3374 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 3375 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 3376 3377 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ 3378 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ 3379 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ 3380 3381 /*!< HPRE configuration */ 3382 #define RCC_CFGR_HPRE_Pos (4U) 3383 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 3384 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 3385 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 3386 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 3387 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 3388 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 3389 3390 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 3391 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 3392 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 3393 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 3394 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 3395 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 3396 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 3397 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 3398 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 3399 3400 /*!< PPRE configuration */ 3401 #define RCC_CFGR_PPRE_Pos (8U) 3402 #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */ 3403 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */ 3404 #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */ 3405 #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */ 3406 #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */ 3407 3408 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */ 3409 #define RCC_CFGR_PPRE_DIV2_Pos (10U) 3410 #define RCC_CFGR_PPRE_DIV2_Msk (0x1UL << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */ 3411 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */ 3412 #define RCC_CFGR_PPRE_DIV4_Pos (8U) 3413 #define RCC_CFGR_PPRE_DIV4_Msk (0x5UL << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */ 3414 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */ 3415 #define RCC_CFGR_PPRE_DIV8_Pos (9U) 3416 #define RCC_CFGR_PPRE_DIV8_Msk (0x3UL << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */ 3417 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ 3418 #define RCC_CFGR_PPRE_DIV16_Pos (8U) 3419 #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ 3420 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ 3421 3422 /*!< ADCPPRE configuration */ 3423 #define RCC_CFGR_ADCPRE_Pos (14U) 3424 #define RCC_CFGR_ADCPRE_Msk (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 3425 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */ 3426 3427 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */ 3428 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */ 3429 3430 #define RCC_CFGR_PLLSRC_Pos (16U) 3431 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 3432 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 3433 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 3434 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ 3435 3436 #define RCC_CFGR_PLLXTPRE_Pos (17U) 3437 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 3438 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 3439 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ 3440 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ 3441 3442 /*!< PLLMUL configuration */ 3443 #define RCC_CFGR_PLLMUL_Pos (18U) 3444 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 3445 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 3446 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 3447 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 3448 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 3449 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 3450 3451 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ 3452 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ 3453 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ 3454 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ 3455 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ 3456 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ 3457 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ 3458 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ 3459 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ 3460 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ 3461 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ 3462 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ 3463 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ 3464 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ 3465 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ 3466 3467 /*!< MCO configuration */ 3468 #define RCC_CFGR_MCO_Pos (24U) 3469 #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ 3470 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 3471 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 3472 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 3473 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 3474 3475 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ 3476 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */ 3477 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ 3478 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ 3479 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ 3480 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ 3481 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ 3482 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ 3483 3484 /* Reference defines */ 3485 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 3486 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 3487 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 3488 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 3489 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 3490 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14 3491 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI 3492 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE 3493 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 3494 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 3495 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 3496 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL 3497 3498 /*!<****************** Bit definition for RCC_CIR register *****************/ 3499 #define RCC_CIR_LSIRDYF_Pos (0U) 3500 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 3501 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 3502 #define RCC_CIR_LSERDYF_Pos (1U) 3503 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 3504 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 3505 #define RCC_CIR_HSIRDYF_Pos (2U) 3506 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 3507 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 3508 #define RCC_CIR_HSERDYF_Pos (3U) 3509 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 3510 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 3511 #define RCC_CIR_PLLRDYF_Pos (4U) 3512 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 3513 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 3514 #define RCC_CIR_HSI14RDYF_Pos (5U) 3515 #define RCC_CIR_HSI14RDYF_Msk (0x1UL << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */ 3516 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */ 3517 #define RCC_CIR_CSSF_Pos (7U) 3518 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 3519 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 3520 #define RCC_CIR_LSIRDYIE_Pos (8U) 3521 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 3522 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 3523 #define RCC_CIR_LSERDYIE_Pos (9U) 3524 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 3525 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 3526 #define RCC_CIR_HSIRDYIE_Pos (10U) 3527 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 3528 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 3529 #define RCC_CIR_HSERDYIE_Pos (11U) 3530 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 3531 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 3532 #define RCC_CIR_PLLRDYIE_Pos (12U) 3533 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 3534 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 3535 #define RCC_CIR_HSI14RDYIE_Pos (13U) 3536 #define RCC_CIR_HSI14RDYIE_Msk (0x1UL << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */ 3537 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */ 3538 #define RCC_CIR_LSIRDYC_Pos (16U) 3539 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 3540 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 3541 #define RCC_CIR_LSERDYC_Pos (17U) 3542 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 3543 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 3544 #define RCC_CIR_HSIRDYC_Pos (18U) 3545 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 3546 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 3547 #define RCC_CIR_HSERDYC_Pos (19U) 3548 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 3549 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 3550 #define RCC_CIR_PLLRDYC_Pos (20U) 3551 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 3552 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 3553 #define RCC_CIR_HSI14RDYC_Pos (21U) 3554 #define RCC_CIR_HSI14RDYC_Msk (0x1UL << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */ 3555 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */ 3556 #define RCC_CIR_CSSC_Pos (23U) 3557 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 3558 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 3559 3560 /***************** Bit definition for RCC_APB2RSTR register ****************/ 3561 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 3562 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 3563 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 3564 #define RCC_APB2RSTR_ADCRST_Pos (9U) 3565 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 3566 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ 3567 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 3568 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 3569 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ 3570 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 3571 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 3572 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 3573 #define RCC_APB2RSTR_USART1RST_Pos (14U) 3574 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 3575 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 3576 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 3577 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 3578 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ 3579 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 3580 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 3581 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ 3582 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 3583 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 3584 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ 3585 #define RCC_APB2RSTR_DBGMCURST_Pos (22U) 3586 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ 3587 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ 3588 3589 /*!< Old ADC1 reset bit definition maintained for legacy purpose */ 3590 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST 3591 3592 /***************** Bit definition for RCC_APB1RSTR register ****************/ 3593 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 3594 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 3595 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 3596 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 3597 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 3598 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 3599 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 3600 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 3601 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 3602 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 3603 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ 3604 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ 3605 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 3606 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 3607 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 3608 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 3609 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 3610 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ 3611 #define RCC_APB1RSTR_USART2RST_Pos (17U) 3612 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 3613 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 3614 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 3615 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 3616 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 3617 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 3618 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 3619 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 3620 #define RCC_APB1RSTR_PWRRST_Pos (28U) 3621 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 3622 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 3623 #define RCC_APB1RSTR_DACRST_Pos (29U) 3624 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 3625 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ 3626 #define RCC_APB1RSTR_CECRST_Pos (30U) 3627 #define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ 3628 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ 3629 3630 /****************** Bit definition for RCC_AHBENR register *****************/ 3631 #define RCC_AHBENR_DMAEN_Pos (0U) 3632 #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 3633 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 3634 #define RCC_AHBENR_SRAMEN_Pos (2U) 3635 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 3636 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 3637 #define RCC_AHBENR_FLITFEN_Pos (4U) 3638 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 3639 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 3640 #define RCC_AHBENR_CRCEN_Pos (6U) 3641 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 3642 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 3643 #define RCC_AHBENR_GPIOAEN_Pos (17U) 3644 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ 3645 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ 3646 #define RCC_AHBENR_GPIOBEN_Pos (18U) 3647 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ 3648 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ 3649 #define RCC_AHBENR_GPIOCEN_Pos (19U) 3650 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ 3651 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ 3652 #define RCC_AHBENR_GPIODEN_Pos (20U) 3653 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ 3654 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ 3655 #define RCC_AHBENR_GPIOFEN_Pos (22U) 3656 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ 3657 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ 3658 #define RCC_AHBENR_TSCEN_Pos (24U) 3659 #define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */ 3660 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller clock enable */ 3661 3662 /* Old Bit definition maintained for legacy purpose */ 3663 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 3664 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */ 3665 3666 /***************** Bit definition for RCC_APB2ENR register *****************/ 3667 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U) 3668 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */ 3669 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */ 3670 #define RCC_APB2ENR_ADCEN_Pos (9U) 3671 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 3672 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 3673 #define RCC_APB2ENR_TIM1EN_Pos (11U) 3674 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 3675 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ 3676 #define RCC_APB2ENR_SPI1EN_Pos (12U) 3677 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 3678 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 3679 #define RCC_APB2ENR_USART1EN_Pos (14U) 3680 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 3681 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 3682 #define RCC_APB2ENR_TIM15EN_Pos (16U) 3683 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 3684 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ 3685 #define RCC_APB2ENR_TIM16EN_Pos (17U) 3686 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 3687 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ 3688 #define RCC_APB2ENR_TIM17EN_Pos (18U) 3689 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 3690 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ 3691 #define RCC_APB2ENR_DBGMCUEN_Pos (22U) 3692 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */ 3693 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */ 3694 3695 /* Old Bit definition maintained for legacy purpose */ 3696 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */ 3697 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 3698 3699 /***************** Bit definition for RCC_APB1ENR register *****************/ 3700 #define RCC_APB1ENR_TIM2EN_Pos (0U) 3701 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 3702 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 3703 #define RCC_APB1ENR_TIM3EN_Pos (1U) 3704 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 3705 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 3706 #define RCC_APB1ENR_TIM6EN_Pos (4U) 3707 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 3708 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 3709 #define RCC_APB1ENR_TIM14EN_Pos (8U) 3710 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ 3711 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */ 3712 #define RCC_APB1ENR_WWDGEN_Pos (11U) 3713 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 3714 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 3715 #define RCC_APB1ENR_SPI2EN_Pos (14U) 3716 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 3717 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 3718 #define RCC_APB1ENR_USART2EN_Pos (17U) 3719 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 3720 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 3721 #define RCC_APB1ENR_I2C1EN_Pos (21U) 3722 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 3723 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 3724 #define RCC_APB1ENR_I2C2EN_Pos (22U) 3725 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 3726 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ 3727 #define RCC_APB1ENR_PWREN_Pos (28U) 3728 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 3729 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 3730 #define RCC_APB1ENR_DACEN_Pos (29U) 3731 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 3732 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */ 3733 #define RCC_APB1ENR_CECEN_Pos (30U) 3734 #define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */ 3735 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enable */ 3736 3737 /******************* Bit definition for RCC_BDCR register ******************/ 3738 #define RCC_BDCR_LSEON_Pos (0U) 3739 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 3740 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 3741 #define RCC_BDCR_LSERDY_Pos (1U) 3742 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 3743 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 3744 #define RCC_BDCR_LSEBYP_Pos (2U) 3745 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 3746 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 3747 3748 #define RCC_BDCR_LSEDRV_Pos (3U) 3749 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 3750 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 3751 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 3752 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 3753 3754 #define RCC_BDCR_RTCSEL_Pos (8U) 3755 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 3756 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 3757 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 3758 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 3759 3760 /*!< RTC configuration */ 3761 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3762 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ 3763 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ 3764 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */ 3765 3766 #define RCC_BDCR_RTCEN_Pos (15U) 3767 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 3768 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 3769 #define RCC_BDCR_BDRST_Pos (16U) 3770 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 3771 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 3772 3773 /******************* Bit definition for RCC_CSR register *******************/ 3774 #define RCC_CSR_LSION_Pos (0U) 3775 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 3776 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 3777 #define RCC_CSR_LSIRDY_Pos (1U) 3778 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 3779 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 3780 #define RCC_CSR_V18PWRRSTF_Pos (23U) 3781 #define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */ 3782 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */ 3783 #define RCC_CSR_RMVF_Pos (24U) 3784 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 3785 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 3786 #define RCC_CSR_OBLRSTF_Pos (25U) 3787 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 3788 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 3789 #define RCC_CSR_PINRSTF_Pos (26U) 3790 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 3791 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 3792 #define RCC_CSR_PORRSTF_Pos (27U) 3793 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 3794 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 3795 #define RCC_CSR_SFTRSTF_Pos (28U) 3796 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 3797 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 3798 #define RCC_CSR_IWDGRSTF_Pos (29U) 3799 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 3800 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 3801 #define RCC_CSR_WWDGRSTF_Pos (30U) 3802 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 3803 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 3804 #define RCC_CSR_LPWRRSTF_Pos (31U) 3805 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 3806 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 3807 3808 /* Old Bit definition maintained for legacy purpose */ 3809 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 3810 3811 /******************* Bit definition for RCC_AHBRSTR register ***************/ 3812 #define RCC_AHBRSTR_GPIOARST_Pos (17U) 3813 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ 3814 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ 3815 #define RCC_AHBRSTR_GPIOBRST_Pos (18U) 3816 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ 3817 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ 3818 #define RCC_AHBRSTR_GPIOCRST_Pos (19U) 3819 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ 3820 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ 3821 #define RCC_AHBRSTR_GPIODRST_Pos (20U) 3822 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ 3823 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ 3824 #define RCC_AHBRSTR_GPIOFRST_Pos (22U) 3825 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ 3826 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ 3827 #define RCC_AHBRSTR_TSCRST_Pos (24U) 3828 #define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ 3829 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ 3830 3831 /* Old Bit definition maintained for legacy purpose */ 3832 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ 3833 3834 /******************* Bit definition for RCC_CFGR2 register *****************/ 3835 /*!< PREDIV configuration */ 3836 #define RCC_CFGR2_PREDIV_Pos (0U) 3837 #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ 3838 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ 3839 #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ 3840 #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ 3841 #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ 3842 #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ 3843 3844 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ 3845 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ 3846 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ 3847 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ 3848 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ 3849 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ 3850 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ 3851 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ 3852 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ 3853 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ 3854 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ 3855 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ 3856 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ 3857 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ 3858 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ 3859 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ 3860 3861 /******************* Bit definition for RCC_CFGR3 register *****************/ 3862 /*!< USART1 Clock source selection */ 3863 #define RCC_CFGR3_USART1SW_Pos (0U) 3864 #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ 3865 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ 3866 #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ 3867 #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ 3868 3869 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */ 3870 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ 3871 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ 3872 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ 3873 3874 /*!< I2C1 Clock source selection */ 3875 #define RCC_CFGR3_I2C1SW_Pos (4U) 3876 #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ 3877 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ 3878 3879 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ 3880 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) 3881 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ 3882 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ 3883 3884 /*!< CEC Clock source selection */ 3885 #define RCC_CFGR3_CECSW_Pos (6U) 3886 #define RCC_CFGR3_CECSW_Msk (0x1UL << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */ 3887 #define RCC_CFGR3_CECSW RCC_CFGR3_CECSW_Msk /*!< CECSW bits */ 3888 3889 #define RCC_CFGR3_CECSW_HSI_DIV244 (0x00000000U) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ 3890 #define RCC_CFGR3_CECSW_LSE_Pos (6U) 3891 #define RCC_CFGR3_CECSW_LSE_Msk (0x1UL << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */ 3892 #define RCC_CFGR3_CECSW_LSE RCC_CFGR3_CECSW_LSE_Msk /*!< LSE clock selected as HDMI CEC entry clock source */ 3893 3894 /******************* Bit definition for RCC_CR2 register *******************/ 3895 #define RCC_CR2_HSI14ON_Pos (0U) 3896 #define RCC_CR2_HSI14ON_Msk (0x1UL << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */ 3897 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */ 3898 #define RCC_CR2_HSI14RDY_Pos (1U) 3899 #define RCC_CR2_HSI14RDY_Msk (0x1UL << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */ 3900 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */ 3901 #define RCC_CR2_HSI14DIS_Pos (2U) 3902 #define RCC_CR2_HSI14DIS_Msk (0x1UL << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */ 3903 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */ 3904 #define RCC_CR2_HSI14TRIM_Pos (3U) 3905 #define RCC_CR2_HSI14TRIM_Msk (0x1FUL << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */ 3906 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */ 3907 #define RCC_CR2_HSI14CAL_Pos (8U) 3908 #define RCC_CR2_HSI14CAL_Msk (0xFFUL << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */ 3909 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */ 3910 3911 /*****************************************************************************/ 3912 /* */ 3913 /* Real-Time Clock (RTC) */ 3914 /* */ 3915 /*****************************************************************************/ 3916 /* 3917 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 3918 */ 3919 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 3920 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 3921 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 3922 3923 /******************** Bits definition for RTC_TR register ******************/ 3924 #define RTC_TR_PM_Pos (22U) 3925 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 3926 #define RTC_TR_PM RTC_TR_PM_Msk 3927 #define RTC_TR_HT_Pos (20U) 3928 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 3929 #define RTC_TR_HT RTC_TR_HT_Msk 3930 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 3931 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 3932 #define RTC_TR_HU_Pos (16U) 3933 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 3934 #define RTC_TR_HU RTC_TR_HU_Msk 3935 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 3936 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 3937 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 3938 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 3939 #define RTC_TR_MNT_Pos (12U) 3940 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 3941 #define RTC_TR_MNT RTC_TR_MNT_Msk 3942 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 3943 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 3944 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 3945 #define RTC_TR_MNU_Pos (8U) 3946 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 3947 #define RTC_TR_MNU RTC_TR_MNU_Msk 3948 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 3949 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 3950 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 3951 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 3952 #define RTC_TR_ST_Pos (4U) 3953 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 3954 #define RTC_TR_ST RTC_TR_ST_Msk 3955 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 3956 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 3957 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 3958 #define RTC_TR_SU_Pos (0U) 3959 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 3960 #define RTC_TR_SU RTC_TR_SU_Msk 3961 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 3962 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 3963 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 3964 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 3965 3966 /******************** Bits definition for RTC_DR register ******************/ 3967 #define RTC_DR_YT_Pos (20U) 3968 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 3969 #define RTC_DR_YT RTC_DR_YT_Msk 3970 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 3971 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 3972 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 3973 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 3974 #define RTC_DR_YU_Pos (16U) 3975 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 3976 #define RTC_DR_YU RTC_DR_YU_Msk 3977 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 3978 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 3979 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 3980 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 3981 #define RTC_DR_WDU_Pos (13U) 3982 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 3983 #define RTC_DR_WDU RTC_DR_WDU_Msk 3984 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 3985 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 3986 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 3987 #define RTC_DR_MT_Pos (12U) 3988 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 3989 #define RTC_DR_MT RTC_DR_MT_Msk 3990 #define RTC_DR_MU_Pos (8U) 3991 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 3992 #define RTC_DR_MU RTC_DR_MU_Msk 3993 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 3994 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 3995 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 3996 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 3997 #define RTC_DR_DT_Pos (4U) 3998 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 3999 #define RTC_DR_DT RTC_DR_DT_Msk 4000 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4001 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4002 #define RTC_DR_DU_Pos (0U) 4003 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4004 #define RTC_DR_DU RTC_DR_DU_Msk 4005 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4006 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4007 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4008 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4009 4010 /******************** Bits definition for RTC_CR register ******************/ 4011 #define RTC_CR_COE_Pos (23U) 4012 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4013 #define RTC_CR_COE RTC_CR_COE_Msk 4014 #define RTC_CR_OSEL_Pos (21U) 4015 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4016 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 4017 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4018 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4019 #define RTC_CR_POL_Pos (20U) 4020 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4021 #define RTC_CR_POL RTC_CR_POL_Msk 4022 #define RTC_CR_COSEL_Pos (19U) 4023 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 4024 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 4025 #define RTC_CR_BKP_Pos (18U) 4026 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 4027 #define RTC_CR_BKP RTC_CR_BKP_Msk 4028 #define RTC_CR_SUB1H_Pos (17U) 4029 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4030 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 4031 #define RTC_CR_ADD1H_Pos (16U) 4032 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4033 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 4034 #define RTC_CR_TSIE_Pos (15U) 4035 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4036 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 4037 #define RTC_CR_ALRAIE_Pos (12U) 4038 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4039 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 4040 #define RTC_CR_TSE_Pos (11U) 4041 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4042 #define RTC_CR_TSE RTC_CR_TSE_Msk 4043 #define RTC_CR_ALRAE_Pos (8U) 4044 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4045 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 4046 #define RTC_CR_FMT_Pos (6U) 4047 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4048 #define RTC_CR_FMT RTC_CR_FMT_Msk 4049 #define RTC_CR_BYPSHAD_Pos (5U) 4050 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 4051 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 4052 #define RTC_CR_REFCKON_Pos (4U) 4053 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4054 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 4055 #define RTC_CR_TSEDGE_Pos (3U) 4056 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4057 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 4058 4059 /* Legacy defines */ 4060 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 4061 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 4062 #define RTC_CR_BCK RTC_CR_BKP 4063 4064 /******************** Bits definition for RTC_ISR register *****************/ 4065 #define RTC_ISR_RECALPF_Pos (16U) 4066 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 4067 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 4068 #define RTC_ISR_TAMP2F_Pos (14U) 4069 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 4070 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 4071 #define RTC_ISR_TAMP1F_Pos (13U) 4072 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 4073 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 4074 #define RTC_ISR_TSOVF_Pos (12U) 4075 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 4076 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 4077 #define RTC_ISR_TSF_Pos (11U) 4078 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 4079 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 4080 #define RTC_ISR_ALRAF_Pos (8U) 4081 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 4082 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 4083 #define RTC_ISR_INIT_Pos (7U) 4084 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 4085 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 4086 #define RTC_ISR_INITF_Pos (6U) 4087 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 4088 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 4089 #define RTC_ISR_RSF_Pos (5U) 4090 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 4091 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 4092 #define RTC_ISR_INITS_Pos (4U) 4093 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 4094 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 4095 #define RTC_ISR_SHPF_Pos (3U) 4096 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 4097 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 4098 #define RTC_ISR_ALRAWF_Pos (0U) 4099 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 4100 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 4101 4102 /******************** Bits definition for RTC_PRER register ****************/ 4103 #define RTC_PRER_PREDIV_A_Pos (16U) 4104 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4105 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 4106 #define RTC_PRER_PREDIV_S_Pos (0U) 4107 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 4108 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 4109 4110 /******************** Bits definition for RTC_ALRMAR register **************/ 4111 #define RTC_ALRMAR_MSK4_Pos (31U) 4112 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4113 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 4114 #define RTC_ALRMAR_WDSEL_Pos (30U) 4115 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4116 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 4117 #define RTC_ALRMAR_DT_Pos (28U) 4118 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4119 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 4120 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4121 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4122 #define RTC_ALRMAR_DU_Pos (24U) 4123 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4124 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 4125 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4126 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4127 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4128 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4129 #define RTC_ALRMAR_MSK3_Pos (23U) 4130 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4131 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 4132 #define RTC_ALRMAR_PM_Pos (22U) 4133 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4134 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 4135 #define RTC_ALRMAR_HT_Pos (20U) 4136 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4137 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 4138 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4139 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4140 #define RTC_ALRMAR_HU_Pos (16U) 4141 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4142 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 4143 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4144 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4145 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4146 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4147 #define RTC_ALRMAR_MSK2_Pos (15U) 4148 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4149 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 4150 #define RTC_ALRMAR_MNT_Pos (12U) 4151 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4152 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 4153 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4154 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4155 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4156 #define RTC_ALRMAR_MNU_Pos (8U) 4157 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 4158 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 4159 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 4160 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 4161 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 4162 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 4163 #define RTC_ALRMAR_MSK1_Pos (7U) 4164 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 4165 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 4166 #define RTC_ALRMAR_ST_Pos (4U) 4167 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 4168 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 4169 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 4170 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 4171 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 4172 #define RTC_ALRMAR_SU_Pos (0U) 4173 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 4174 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 4175 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 4176 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 4177 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 4178 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 4179 4180 /******************** Bits definition for RTC_WPR register *****************/ 4181 #define RTC_WPR_KEY_Pos (0U) 4182 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4183 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 4184 4185 /******************** Bits definition for RTC_SSR register *****************/ 4186 #define RTC_SSR_SS_Pos (0U) 4187 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 4188 #define RTC_SSR_SS RTC_SSR_SS_Msk 4189 4190 /******************** Bits definition for RTC_SHIFTR register **************/ 4191 #define RTC_SHIFTR_SUBFS_Pos (0U) 4192 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 4193 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 4194 #define RTC_SHIFTR_ADD1S_Pos (31U) 4195 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 4196 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 4197 4198 /******************** Bits definition for RTC_TSTR register ****************/ 4199 #define RTC_TSTR_PM_Pos (22U) 4200 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4201 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 4202 #define RTC_TSTR_HT_Pos (20U) 4203 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4204 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 4205 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4206 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4207 #define RTC_TSTR_HU_Pos (16U) 4208 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4209 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 4210 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4211 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4212 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4213 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4214 #define RTC_TSTR_MNT_Pos (12U) 4215 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4216 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 4217 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4218 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4219 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4220 #define RTC_TSTR_MNU_Pos (8U) 4221 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4222 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 4223 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4224 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4225 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4226 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4227 #define RTC_TSTR_ST_Pos (4U) 4228 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4229 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 4230 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4231 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4232 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4233 #define RTC_TSTR_SU_Pos (0U) 4234 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4235 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 4236 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4237 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4238 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4239 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4240 4241 /******************** Bits definition for RTC_TSDR register ****************/ 4242 #define RTC_TSDR_WDU_Pos (13U) 4243 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4244 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 4245 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4246 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4247 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4248 #define RTC_TSDR_MT_Pos (12U) 4249 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4250 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 4251 #define RTC_TSDR_MU_Pos (8U) 4252 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4253 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 4254 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4255 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4256 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4257 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4258 #define RTC_TSDR_DT_Pos (4U) 4259 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4260 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 4261 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4262 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4263 #define RTC_TSDR_DU_Pos (0U) 4264 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4265 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 4266 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4267 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4268 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4269 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4270 4271 /******************** Bits definition for RTC_TSSSR register ***************/ 4272 #define RTC_TSSSR_SS_Pos (0U) 4273 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4274 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 4275 4276 /******************** Bits definition for RTC_CALR register ****************/ 4277 #define RTC_CALR_CALP_Pos (15U) 4278 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4279 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 4280 #define RTC_CALR_CALW8_Pos (14U) 4281 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4282 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 4283 #define RTC_CALR_CALW16_Pos (13U) 4284 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4285 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 4286 #define RTC_CALR_CALM_Pos (0U) 4287 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4288 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 4289 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4290 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4291 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4292 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4293 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4294 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4295 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4296 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4297 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4298 4299 /******************** Bits definition for RTC_TAFCR register ***************/ 4300 #define RTC_TAFCR_PC15MODE_Pos (23U) 4301 #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ 4302 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk 4303 #define RTC_TAFCR_PC15VALUE_Pos (22U) 4304 #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ 4305 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk 4306 #define RTC_TAFCR_PC14MODE_Pos (21U) 4307 #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ 4308 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk 4309 #define RTC_TAFCR_PC14VALUE_Pos (20U) 4310 #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ 4311 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk 4312 #define RTC_TAFCR_PC13MODE_Pos (19U) 4313 #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ 4314 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk 4315 #define RTC_TAFCR_PC13VALUE_Pos (18U) 4316 #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ 4317 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk 4318 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 4319 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 4320 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 4321 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 4322 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 4323 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 4324 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 4325 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 4326 #define RTC_TAFCR_TAMPFLT_Pos (11U) 4327 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 4328 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 4329 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 4330 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 4331 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 4332 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 4333 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 4334 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 4335 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 4336 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 4337 #define RTC_TAFCR_TAMPTS_Pos (7U) 4338 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 4339 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 4340 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 4341 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 4342 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 4343 #define RTC_TAFCR_TAMP2E_Pos (3U) 4344 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 4345 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 4346 #define RTC_TAFCR_TAMPIE_Pos (2U) 4347 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 4348 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 4349 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 4350 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 4351 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 4352 #define RTC_TAFCR_TAMP1E_Pos (0U) 4353 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 4354 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 4355 4356 /* Reference defines */ 4357 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 4358 4359 /******************** Bits definition for RTC_ALRMASSR register ************/ 4360 #define RTC_ALRMASSR_MASKSS_Pos (24U) 4361 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 4362 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 4363 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 4364 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 4365 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 4366 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 4367 #define RTC_ALRMASSR_SS_Pos (0U) 4368 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 4369 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 4370 4371 /******************** Bits definition for RTC_BKP0R register ***************/ 4372 #define RTC_BKP0R_Pos (0U) 4373 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 4374 #define RTC_BKP0R RTC_BKP0R_Msk 4375 4376 /******************** Bits definition for RTC_BKP1R register ***************/ 4377 #define RTC_BKP1R_Pos (0U) 4378 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 4379 #define RTC_BKP1R RTC_BKP1R_Msk 4380 4381 /******************** Bits definition for RTC_BKP2R register ***************/ 4382 #define RTC_BKP2R_Pos (0U) 4383 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 4384 #define RTC_BKP2R RTC_BKP2R_Msk 4385 4386 /******************** Bits definition for RTC_BKP3R register ***************/ 4387 #define RTC_BKP3R_Pos (0U) 4388 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 4389 #define RTC_BKP3R RTC_BKP3R_Msk 4390 4391 /******************** Bits definition for RTC_BKP4R register ***************/ 4392 #define RTC_BKP4R_Pos (0U) 4393 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 4394 #define RTC_BKP4R RTC_BKP4R_Msk 4395 4396 /******************** Number of backup registers ******************************/ 4397 #define RTC_BKP_NUMBER 0x00000005U 4398 4399 /*****************************************************************************/ 4400 /* */ 4401 /* Serial Peripheral Interface (SPI) */ 4402 /* */ 4403 /*****************************************************************************/ 4404 4405 /* 4406 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 4407 */ 4408 #define SPI_I2S_SUPPORT /*!< I2S support */ 4409 4410 /******************* Bit definition for SPI_CR1 register *******************/ 4411 #define SPI_CR1_CPHA_Pos (0U) 4412 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4413 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4414 #define SPI_CR1_CPOL_Pos (1U) 4415 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4416 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4417 #define SPI_CR1_MSTR_Pos (2U) 4418 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4419 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4420 #define SPI_CR1_BR_Pos (3U) 4421 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4422 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4423 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4424 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4425 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4426 #define SPI_CR1_SPE_Pos (6U) 4427 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4428 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4429 #define SPI_CR1_LSBFIRST_Pos (7U) 4430 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4431 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4432 #define SPI_CR1_SSI_Pos (8U) 4433 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4434 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4435 #define SPI_CR1_SSM_Pos (9U) 4436 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4437 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4438 #define SPI_CR1_RXONLY_Pos (10U) 4439 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4440 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4441 #define SPI_CR1_CRCL_Pos (11U) 4442 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 4443 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 4444 #define SPI_CR1_CRCNEXT_Pos (12U) 4445 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4446 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4447 #define SPI_CR1_CRCEN_Pos (13U) 4448 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4449 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4450 #define SPI_CR1_BIDIOE_Pos (14U) 4451 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4452 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4453 #define SPI_CR1_BIDIMODE_Pos (15U) 4454 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4455 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4456 4457 /******************* Bit definition for SPI_CR2 register *******************/ 4458 #define SPI_CR2_RXDMAEN_Pos (0U) 4459 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4460 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4461 #define SPI_CR2_TXDMAEN_Pos (1U) 4462 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4463 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4464 #define SPI_CR2_SSOE_Pos (2U) 4465 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4466 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4467 #define SPI_CR2_NSSP_Pos (3U) 4468 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 4469 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 4470 #define SPI_CR2_FRF_Pos (4U) 4471 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 4472 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 4473 #define SPI_CR2_ERRIE_Pos (5U) 4474 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4475 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4476 #define SPI_CR2_RXNEIE_Pos (6U) 4477 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4478 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4479 #define SPI_CR2_TXEIE_Pos (7U) 4480 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4481 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4482 #define SPI_CR2_DS_Pos (8U) 4483 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 4484 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 4485 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 4486 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 4487 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 4488 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 4489 #define SPI_CR2_FRXTH_Pos (12U) 4490 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 4491 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 4492 #define SPI_CR2_LDMARX_Pos (13U) 4493 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 4494 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 4495 #define SPI_CR2_LDMATX_Pos (14U) 4496 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 4497 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 4498 4499 /******************** Bit definition for SPI_SR register *******************/ 4500 #define SPI_SR_RXNE_Pos (0U) 4501 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4502 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4503 #define SPI_SR_TXE_Pos (1U) 4504 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4505 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4506 #define SPI_SR_CHSIDE_Pos (2U) 4507 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 4508 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 4509 #define SPI_SR_UDR_Pos (3U) 4510 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 4511 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 4512 #define SPI_SR_CRCERR_Pos (4U) 4513 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 4514 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 4515 #define SPI_SR_MODF_Pos (5U) 4516 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 4517 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 4518 #define SPI_SR_OVR_Pos (6U) 4519 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 4520 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 4521 #define SPI_SR_BSY_Pos (7U) 4522 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 4523 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 4524 #define SPI_SR_FRE_Pos (8U) 4525 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 4526 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 4527 #define SPI_SR_FRLVL_Pos (9U) 4528 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 4529 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 4530 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 4531 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 4532 #define SPI_SR_FTLVL_Pos (11U) 4533 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 4534 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 4535 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 4536 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 4537 4538 /******************** Bit definition for SPI_DR register *******************/ 4539 #define SPI_DR_DR_Pos (0U) 4540 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ 4541 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 4542 4543 /******************* Bit definition for SPI_CRCPR register *****************/ 4544 #define SPI_CRCPR_CRCPOLY_Pos (0U) 4545 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */ 4546 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 4547 4548 /****************** Bit definition for SPI_RXCRCR register *****************/ 4549 #define SPI_RXCRCR_RXCRC_Pos (0U) 4550 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */ 4551 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 4552 4553 /****************** Bit definition for SPI_TXCRCR register *****************/ 4554 #define SPI_TXCRCR_TXCRC_Pos (0U) 4555 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */ 4556 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 4557 4558 /****************** Bit definition for SPI_I2SCFGR register ****************/ 4559 #define SPI_I2SCFGR_CHLEN_Pos (0U) 4560 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 4561 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 4562 #define SPI_I2SCFGR_DATLEN_Pos (1U) 4563 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 4564 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 4565 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 4566 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 4567 #define SPI_I2SCFGR_CKPOL_Pos (3U) 4568 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 4569 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 4570 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 4571 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 4572 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 4573 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 4574 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 4575 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 4576 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 4577 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 4578 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 4579 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 4580 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 4581 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 4582 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 4583 #define SPI_I2SCFGR_I2SE_Pos (10U) 4584 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 4585 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 4586 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 4587 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 4588 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 4589 4590 /****************** Bit definition for SPI_I2SPR register ******************/ 4591 #define SPI_I2SPR_I2SDIV_Pos (0U) 4592 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 4593 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 4594 #define SPI_I2SPR_ODD_Pos (8U) 4595 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 4596 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 4597 #define SPI_I2SPR_MCKOE_Pos (9U) 4598 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 4599 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 4600 4601 /*****************************************************************************/ 4602 /* */ 4603 /* System Configuration (SYSCFG) */ 4604 /* */ 4605 /*****************************************************************************/ 4606 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 4607 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 4608 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 4609 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 4610 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 4611 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 4612 4613 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U) 4614 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */ 4615 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ 4616 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U) 4617 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */ 4618 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */ 4619 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U) 4620 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */ 4621 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */ 4622 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U) 4623 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */ 4624 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */ 4625 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) 4626 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ 4627 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ 4628 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) 4629 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ 4630 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ 4631 4632 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U) 4633 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */ 4634 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */ 4635 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U) 4636 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */ 4637 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */ 4638 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U) 4639 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */ 4640 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */ 4641 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U) 4642 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */ 4643 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */ 4644 4645 /***************** Bit definition for SYSCFG_EXTICR1 register **************/ 4646 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 4647 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 4648 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 4649 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 4650 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 4651 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 4652 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 4653 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 4654 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 4655 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 4656 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 4657 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 4658 4659 /** 4660 * @brief EXTI0 configuration 4661 */ 4662 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 4663 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 4664 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 4665 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 4666 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ 4667 4668 /** 4669 * @brief EXTI1 configuration 4670 */ 4671 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 4672 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 4673 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 4674 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 4675 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ 4676 4677 /** 4678 * @brief EXTI2 configuration 4679 */ 4680 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 4681 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 4682 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 4683 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 4684 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ 4685 4686 /** 4687 * @brief EXTI3 configuration 4688 */ 4689 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 4690 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 4691 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 4692 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 4693 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */ 4694 4695 /***************** Bit definition for SYSCFG_EXTICR2 register **************/ 4696 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 4697 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 4698 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 4699 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 4700 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 4701 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 4702 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 4703 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 4704 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 4705 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 4706 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 4707 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 4708 4709 /** 4710 * @brief EXTI4 configuration 4711 */ 4712 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 4713 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 4714 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 4715 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 4716 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ 4717 4718 /** 4719 * @brief EXTI5 configuration 4720 */ 4721 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 4722 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 4723 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 4724 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 4725 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ 4726 4727 /** 4728 * @brief EXTI6 configuration 4729 */ 4730 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 4731 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 4732 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 4733 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 4734 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ 4735 4736 /** 4737 * @brief EXTI7 configuration 4738 */ 4739 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 4740 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 4741 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 4742 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 4743 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */ 4744 4745 /***************** Bit definition for SYSCFG_EXTICR3 register **************/ 4746 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 4747 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 4748 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 4749 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 4750 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 4751 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 4752 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 4753 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 4754 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 4755 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 4756 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 4757 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 4758 4759 /** 4760 * @brief EXTI8 configuration 4761 */ 4762 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 4763 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 4764 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 4765 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 4766 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */ 4767 4768 4769 /** 4770 * @brief EXTI9 configuration 4771 */ 4772 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 4773 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 4774 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 4775 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 4776 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ 4777 4778 /** 4779 * @brief EXTI10 configuration 4780 */ 4781 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 4782 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 4783 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 4784 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 4785 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ 4786 4787 /** 4788 * @brief EXTI11 configuration 4789 */ 4790 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 4791 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 4792 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 4793 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 4794 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */ 4795 4796 /***************** Bit definition for SYSCFG_EXTICR4 register **************/ 4797 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 4798 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 4799 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 4800 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 4801 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 4802 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 4803 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 4804 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 4805 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 4806 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 4807 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 4808 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 4809 4810 /** 4811 * @brief EXTI12 configuration 4812 */ 4813 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 4814 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 4815 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 4816 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 4817 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */ 4818 4819 /** 4820 * @brief EXTI13 configuration 4821 */ 4822 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 4823 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 4824 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 4825 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 4826 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */ 4827 4828 /** 4829 * @brief EXTI14 configuration 4830 */ 4831 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 4832 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 4833 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 4834 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 4835 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */ 4836 4837 /** 4838 * @brief EXTI15 configuration 4839 */ 4840 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 4841 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 4842 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 4843 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 4844 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */ 4845 4846 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 4847 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) 4848 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ 4849 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ 4850 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) 4851 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ 4852 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ 4853 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) 4854 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ 4855 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */ 4856 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U) 4857 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */ 4858 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */ 4859 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ 4860 4861 /*****************************************************************************/ 4862 /* */ 4863 /* Timers (TIM) */ 4864 /* */ 4865 /*****************************************************************************/ 4866 /******************* Bit definition for TIM_CR1 register *******************/ 4867 #define TIM_CR1_CEN_Pos (0U) 4868 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 4869 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 4870 #define TIM_CR1_UDIS_Pos (1U) 4871 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 4872 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 4873 #define TIM_CR1_URS_Pos (2U) 4874 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 4875 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 4876 #define TIM_CR1_OPM_Pos (3U) 4877 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 4878 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 4879 #define TIM_CR1_DIR_Pos (4U) 4880 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 4881 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 4882 4883 #define TIM_CR1_CMS_Pos (5U) 4884 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 4885 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4886 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 4887 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 4888 4889 #define TIM_CR1_ARPE_Pos (7U) 4890 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 4891 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 4892 4893 #define TIM_CR1_CKD_Pos (8U) 4894 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 4895 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 4896 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 4897 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 4898 4899 /******************* Bit definition for TIM_CR2 register *******************/ 4900 #define TIM_CR2_CCPC_Pos (0U) 4901 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 4902 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 4903 #define TIM_CR2_CCUS_Pos (2U) 4904 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 4905 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 4906 #define TIM_CR2_CCDS_Pos (3U) 4907 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 4908 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 4909 4910 #define TIM_CR2_MMS_Pos (4U) 4911 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 4912 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 4913 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 4914 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 4915 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 4916 4917 #define TIM_CR2_TI1S_Pos (7U) 4918 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 4919 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 4920 #define TIM_CR2_OIS1_Pos (8U) 4921 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 4922 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 4923 #define TIM_CR2_OIS1N_Pos (9U) 4924 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 4925 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 4926 #define TIM_CR2_OIS2_Pos (10U) 4927 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 4928 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 4929 #define TIM_CR2_OIS2N_Pos (11U) 4930 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 4931 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 4932 #define TIM_CR2_OIS3_Pos (12U) 4933 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 4934 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 4935 #define TIM_CR2_OIS3N_Pos (13U) 4936 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 4937 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 4938 #define TIM_CR2_OIS4_Pos (14U) 4939 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 4940 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 4941 4942 /******************* Bit definition for TIM_SMCR register ******************/ 4943 #define TIM_SMCR_SMS_Pos (0U) 4944 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 4945 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 4946 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 4947 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 4948 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 4949 4950 #define TIM_SMCR_OCCS_Pos (3U) 4951 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 4952 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 4953 4954 #define TIM_SMCR_TS_Pos (4U) 4955 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 4956 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 4957 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 4958 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 4959 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 4960 4961 #define TIM_SMCR_MSM_Pos (7U) 4962 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 4963 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 4964 4965 #define TIM_SMCR_ETF_Pos (8U) 4966 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 4967 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 4968 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 4969 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 4970 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 4971 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 4972 4973 #define TIM_SMCR_ETPS_Pos (12U) 4974 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 4975 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 4976 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 4977 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 4978 4979 #define TIM_SMCR_ECE_Pos (14U) 4980 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 4981 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 4982 #define TIM_SMCR_ETP_Pos (15U) 4983 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 4984 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 4985 4986 /******************* Bit definition for TIM_DIER register ******************/ 4987 #define TIM_DIER_UIE_Pos (0U) 4988 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 4989 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 4990 #define TIM_DIER_CC1IE_Pos (1U) 4991 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 4992 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 4993 #define TIM_DIER_CC2IE_Pos (2U) 4994 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 4995 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 4996 #define TIM_DIER_CC3IE_Pos (3U) 4997 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 4998 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 4999 #define TIM_DIER_CC4IE_Pos (4U) 5000 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5001 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5002 #define TIM_DIER_COMIE_Pos (5U) 5003 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 5004 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 5005 #define TIM_DIER_TIE_Pos (6U) 5006 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5007 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5008 #define TIM_DIER_BIE_Pos (7U) 5009 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 5010 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 5011 #define TIM_DIER_UDE_Pos (8U) 5012 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5013 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5014 #define TIM_DIER_CC1DE_Pos (9U) 5015 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5016 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5017 #define TIM_DIER_CC2DE_Pos (10U) 5018 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5019 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5020 #define TIM_DIER_CC3DE_Pos (11U) 5021 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5022 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5023 #define TIM_DIER_CC4DE_Pos (12U) 5024 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5025 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5026 #define TIM_DIER_COMDE_Pos (13U) 5027 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 5028 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 5029 #define TIM_DIER_TDE_Pos (14U) 5030 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5031 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5032 5033 /******************** Bit definition for TIM_SR register *******************/ 5034 #define TIM_SR_UIF_Pos (0U) 5035 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5036 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5037 #define TIM_SR_CC1IF_Pos (1U) 5038 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5039 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5040 #define TIM_SR_CC2IF_Pos (2U) 5041 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5042 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5043 #define TIM_SR_CC3IF_Pos (3U) 5044 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 5045 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 5046 #define TIM_SR_CC4IF_Pos (4U) 5047 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 5048 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 5049 #define TIM_SR_COMIF_Pos (5U) 5050 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 5051 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 5052 #define TIM_SR_TIF_Pos (6U) 5053 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 5054 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 5055 #define TIM_SR_BIF_Pos (7U) 5056 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 5057 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 5058 #define TIM_SR_CC1OF_Pos (9U) 5059 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 5060 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 5061 #define TIM_SR_CC2OF_Pos (10U) 5062 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 5063 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 5064 #define TIM_SR_CC3OF_Pos (11U) 5065 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 5066 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 5067 #define TIM_SR_CC4OF_Pos (12U) 5068 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 5069 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 5070 5071 /******************* Bit definition for TIM_EGR register *******************/ 5072 #define TIM_EGR_UG_Pos (0U) 5073 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 5074 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 5075 #define TIM_EGR_CC1G_Pos (1U) 5076 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 5077 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 5078 #define TIM_EGR_CC2G_Pos (2U) 5079 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 5080 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 5081 #define TIM_EGR_CC3G_Pos (3U) 5082 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 5083 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 5084 #define TIM_EGR_CC4G_Pos (4U) 5085 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 5086 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 5087 #define TIM_EGR_COMG_Pos (5U) 5088 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 5089 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 5090 #define TIM_EGR_TG_Pos (6U) 5091 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 5092 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 5093 #define TIM_EGR_BG_Pos (7U) 5094 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 5095 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 5096 5097 /****************** Bit definition for TIM_CCMR1 register ******************/ 5098 #define TIM_CCMR1_CC1S_Pos (0U) 5099 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 5100 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5101 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 5102 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 5103 5104 #define TIM_CCMR1_OC1FE_Pos (2U) 5105 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 5106 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 5107 #define TIM_CCMR1_OC1PE_Pos (3U) 5108 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 5109 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 5110 5111 #define TIM_CCMR1_OC1M_Pos (4U) 5112 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 5113 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5114 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 5115 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 5116 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 5117 5118 #define TIM_CCMR1_OC1CE_Pos (7U) 5119 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 5120 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 5121 5122 #define TIM_CCMR1_CC2S_Pos (8U) 5123 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 5124 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5125 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 5126 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 5127 5128 #define TIM_CCMR1_OC2FE_Pos (10U) 5129 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 5130 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 5131 #define TIM_CCMR1_OC2PE_Pos (11U) 5132 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 5133 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 5134 5135 #define TIM_CCMR1_OC2M_Pos (12U) 5136 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 5137 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5138 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 5139 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 5140 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 5141 5142 #define TIM_CCMR1_OC2CE_Pos (15U) 5143 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 5144 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 5145 5146 /*---------------------------------------------------------------------------*/ 5147 5148 #define TIM_CCMR1_IC1PSC_Pos (2U) 5149 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 5150 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5151 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 5152 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 5153 5154 #define TIM_CCMR1_IC1F_Pos (4U) 5155 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 5156 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5157 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 5158 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 5159 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 5160 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 5161 5162 #define TIM_CCMR1_IC2PSC_Pos (10U) 5163 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 5164 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5165 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 5166 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 5167 5168 #define TIM_CCMR1_IC2F_Pos (12U) 5169 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 5170 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5171 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 5172 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 5173 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 5174 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 5175 5176 /****************** Bit definition for TIM_CCMR2 register ******************/ 5177 #define TIM_CCMR2_CC3S_Pos (0U) 5178 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 5179 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5180 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 5181 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 5182 5183 #define TIM_CCMR2_OC3FE_Pos (2U) 5184 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 5185 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 5186 #define TIM_CCMR2_OC3PE_Pos (3U) 5187 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 5188 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 5189 5190 #define TIM_CCMR2_OC3M_Pos (4U) 5191 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 5192 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5193 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 5194 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 5195 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 5196 5197 #define TIM_CCMR2_OC3CE_Pos (7U) 5198 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 5199 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 5200 5201 #define TIM_CCMR2_CC4S_Pos (8U) 5202 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 5203 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5204 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 5205 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 5206 5207 #define TIM_CCMR2_OC4FE_Pos (10U) 5208 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 5209 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 5210 #define TIM_CCMR2_OC4PE_Pos (11U) 5211 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 5212 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 5213 5214 #define TIM_CCMR2_OC4M_Pos (12U) 5215 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 5216 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5217 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 5218 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 5219 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 5220 5221 #define TIM_CCMR2_OC4CE_Pos (15U) 5222 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 5223 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 5224 5225 /*---------------------------------------------------------------------------*/ 5226 5227 #define TIM_CCMR2_IC3PSC_Pos (2U) 5228 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 5229 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 5230 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 5231 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 5232 5233 #define TIM_CCMR2_IC3F_Pos (4U) 5234 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 5235 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 5236 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 5237 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 5238 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 5239 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 5240 5241 #define TIM_CCMR2_IC4PSC_Pos (10U) 5242 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 5243 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 5244 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 5245 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 5246 5247 #define TIM_CCMR2_IC4F_Pos (12U) 5248 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 5249 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 5250 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 5251 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 5252 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 5253 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 5254 5255 /******************* Bit definition for TIM_CCER register ******************/ 5256 #define TIM_CCER_CC1E_Pos (0U) 5257 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 5258 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 5259 #define TIM_CCER_CC1P_Pos (1U) 5260 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 5261 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 5262 #define TIM_CCER_CC1NE_Pos (2U) 5263 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 5264 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 5265 #define TIM_CCER_CC1NP_Pos (3U) 5266 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 5267 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 5268 #define TIM_CCER_CC2E_Pos (4U) 5269 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 5270 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 5271 #define TIM_CCER_CC2P_Pos (5U) 5272 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 5273 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 5274 #define TIM_CCER_CC2NE_Pos (6U) 5275 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 5276 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 5277 #define TIM_CCER_CC2NP_Pos (7U) 5278 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 5279 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 5280 #define TIM_CCER_CC3E_Pos (8U) 5281 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 5282 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 5283 #define TIM_CCER_CC3P_Pos (9U) 5284 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 5285 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 5286 #define TIM_CCER_CC3NE_Pos (10U) 5287 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 5288 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 5289 #define TIM_CCER_CC3NP_Pos (11U) 5290 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 5291 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 5292 #define TIM_CCER_CC4E_Pos (12U) 5293 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 5294 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 5295 #define TIM_CCER_CC4P_Pos (13U) 5296 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 5297 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 5298 #define TIM_CCER_CC4NP_Pos (15U) 5299 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 5300 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 5301 5302 /******************* Bit definition for TIM_CNT register *******************/ 5303 #define TIM_CNT_CNT_Pos (0U) 5304 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 5305 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 5306 5307 /******************* Bit definition for TIM_PSC register *******************/ 5308 #define TIM_PSC_PSC_Pos (0U) 5309 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 5310 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 5311 5312 /******************* Bit definition for TIM_ARR register *******************/ 5313 #define TIM_ARR_ARR_Pos (0U) 5314 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 5315 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 5316 5317 /******************* Bit definition for TIM_RCR register *******************/ 5318 #define TIM_RCR_REP_Pos (0U) 5319 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 5320 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 5321 5322 /******************* Bit definition for TIM_CCR1 register ******************/ 5323 #define TIM_CCR1_CCR1_Pos (0U) 5324 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 5325 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 5326 5327 /******************* Bit definition for TIM_CCR2 register ******************/ 5328 #define TIM_CCR2_CCR2_Pos (0U) 5329 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 5330 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 5331 5332 /******************* Bit definition for TIM_CCR3 register ******************/ 5333 #define TIM_CCR3_CCR3_Pos (0U) 5334 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 5335 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 5336 5337 /******************* Bit definition for TIM_CCR4 register ******************/ 5338 #define TIM_CCR4_CCR4_Pos (0U) 5339 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 5340 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 5341 5342 /******************* Bit definition for TIM_BDTR register ******************/ 5343 #define TIM_BDTR_DTG_Pos (0U) 5344 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 5345 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 5346 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 5347 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 5348 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 5349 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 5350 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 5351 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 5352 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 5353 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 5354 5355 #define TIM_BDTR_LOCK_Pos (8U) 5356 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 5357 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 5358 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 5359 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 5360 5361 #define TIM_BDTR_OSSI_Pos (10U) 5362 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 5363 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 5364 #define TIM_BDTR_OSSR_Pos (11U) 5365 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 5366 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 5367 #define TIM_BDTR_BKE_Pos (12U) 5368 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 5369 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 5370 #define TIM_BDTR_BKP_Pos (13U) 5371 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 5372 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 5373 #define TIM_BDTR_AOE_Pos (14U) 5374 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 5375 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 5376 #define TIM_BDTR_MOE_Pos (15U) 5377 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 5378 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 5379 5380 /******************* Bit definition for TIM_DCR register *******************/ 5381 #define TIM_DCR_DBA_Pos (0U) 5382 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 5383 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 5384 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 5385 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 5386 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 5387 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 5388 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 5389 5390 #define TIM_DCR_DBL_Pos (8U) 5391 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 5392 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 5393 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 5394 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 5395 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 5396 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 5397 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 5398 5399 /******************* Bit definition for TIM_DMAR register ******************/ 5400 #define TIM_DMAR_DMAB_Pos (0U) 5401 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 5402 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 5403 5404 /******************* Bit definition for TIM14_OR register ********************/ 5405 #define TIM14_OR_TI1_RMP_Pos (0U) 5406 #define TIM14_OR_TI1_RMP_Msk (0x3UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 5407 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */ 5408 #define TIM14_OR_TI1_RMP_0 (0x1UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 5409 #define TIM14_OR_TI1_RMP_1 (0x2UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 5410 5411 /******************************************************************************/ 5412 /* */ 5413 /* Touch Sensing Controller (TSC) */ 5414 /* */ 5415 /******************************************************************************/ 5416 /******************* Bit definition for TSC_CR register *********************/ 5417 #define TSC_CR_TSCE_Pos (0U) 5418 #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ 5419 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ 5420 #define TSC_CR_START_Pos (1U) 5421 #define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */ 5422 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ 5423 #define TSC_CR_AM_Pos (2U) 5424 #define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */ 5425 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ 5426 #define TSC_CR_SYNCPOL_Pos (3U) 5427 #define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ 5428 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ 5429 #define TSC_CR_IODEF_Pos (4U) 5430 #define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ 5431 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ 5432 5433 #define TSC_CR_MCV_Pos (5U) 5434 #define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ 5435 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ 5436 #define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */ 5437 #define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */ 5438 #define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */ 5439 5440 #define TSC_CR_PGPSC_Pos (12U) 5441 #define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ 5442 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ 5443 #define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ 5444 #define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ 5445 #define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ 5446 5447 #define TSC_CR_SSPSC_Pos (15U) 5448 #define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ 5449 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ 5450 #define TSC_CR_SSE_Pos (16U) 5451 #define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */ 5452 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ 5453 5454 #define TSC_CR_SSD_Pos (17U) 5455 #define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ 5456 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ 5457 #define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */ 5458 #define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */ 5459 #define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */ 5460 #define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */ 5461 #define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */ 5462 #define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */ 5463 #define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */ 5464 5465 #define TSC_CR_CTPL_Pos (24U) 5466 #define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ 5467 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ 5468 #define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ 5469 #define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ 5470 #define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ 5471 #define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ 5472 5473 #define TSC_CR_CTPH_Pos (28U) 5474 #define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ 5475 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ 5476 #define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ 5477 #define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ 5478 #define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ 5479 #define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ 5480 5481 /******************* Bit definition for TSC_IER register ********************/ 5482 #define TSC_IER_EOAIE_Pos (0U) 5483 #define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ 5484 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ 5485 #define TSC_IER_MCEIE_Pos (1U) 5486 #define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ 5487 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ 5488 5489 /******************* Bit definition for TSC_ICR register ********************/ 5490 #define TSC_ICR_EOAIC_Pos (0U) 5491 #define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ 5492 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ 5493 #define TSC_ICR_MCEIC_Pos (1U) 5494 #define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ 5495 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ 5496 5497 /******************* Bit definition for TSC_ISR register ********************/ 5498 #define TSC_ISR_EOAF_Pos (0U) 5499 #define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ 5500 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ 5501 #define TSC_ISR_MCEF_Pos (1U) 5502 #define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ 5503 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ 5504 5505 /******************* Bit definition for TSC_IOHCR register ******************/ 5506 #define TSC_IOHCR_G1_IO1_Pos (0U) 5507 #define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ 5508 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ 5509 #define TSC_IOHCR_G1_IO2_Pos (1U) 5510 #define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ 5511 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ 5512 #define TSC_IOHCR_G1_IO3_Pos (2U) 5513 #define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ 5514 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ 5515 #define TSC_IOHCR_G1_IO4_Pos (3U) 5516 #define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ 5517 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ 5518 #define TSC_IOHCR_G2_IO1_Pos (4U) 5519 #define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ 5520 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ 5521 #define TSC_IOHCR_G2_IO2_Pos (5U) 5522 #define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ 5523 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ 5524 #define TSC_IOHCR_G2_IO3_Pos (6U) 5525 #define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ 5526 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ 5527 #define TSC_IOHCR_G2_IO4_Pos (7U) 5528 #define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ 5529 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ 5530 #define TSC_IOHCR_G3_IO1_Pos (8U) 5531 #define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ 5532 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ 5533 #define TSC_IOHCR_G3_IO2_Pos (9U) 5534 #define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ 5535 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ 5536 #define TSC_IOHCR_G3_IO3_Pos (10U) 5537 #define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ 5538 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ 5539 #define TSC_IOHCR_G3_IO4_Pos (11U) 5540 #define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ 5541 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ 5542 #define TSC_IOHCR_G4_IO1_Pos (12U) 5543 #define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ 5544 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ 5545 #define TSC_IOHCR_G4_IO2_Pos (13U) 5546 #define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ 5547 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ 5548 #define TSC_IOHCR_G4_IO3_Pos (14U) 5549 #define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ 5550 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ 5551 #define TSC_IOHCR_G4_IO4_Pos (15U) 5552 #define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ 5553 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ 5554 #define TSC_IOHCR_G5_IO1_Pos (16U) 5555 #define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ 5556 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ 5557 #define TSC_IOHCR_G5_IO2_Pos (17U) 5558 #define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ 5559 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ 5560 #define TSC_IOHCR_G5_IO3_Pos (18U) 5561 #define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ 5562 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ 5563 #define TSC_IOHCR_G5_IO4_Pos (19U) 5564 #define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ 5565 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ 5566 #define TSC_IOHCR_G6_IO1_Pos (20U) 5567 #define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ 5568 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ 5569 #define TSC_IOHCR_G6_IO2_Pos (21U) 5570 #define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ 5571 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ 5572 #define TSC_IOHCR_G6_IO3_Pos (22U) 5573 #define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ 5574 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ 5575 #define TSC_IOHCR_G6_IO4_Pos (23U) 5576 #define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ 5577 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ 5578 #define TSC_IOHCR_G7_IO1_Pos (24U) 5579 #define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ 5580 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ 5581 #define TSC_IOHCR_G7_IO2_Pos (25U) 5582 #define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ 5583 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ 5584 #define TSC_IOHCR_G7_IO3_Pos (26U) 5585 #define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ 5586 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ 5587 #define TSC_IOHCR_G7_IO4_Pos (27U) 5588 #define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ 5589 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ 5590 #define TSC_IOHCR_G8_IO1_Pos (28U) 5591 #define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */ 5592 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ 5593 #define TSC_IOHCR_G8_IO2_Pos (29U) 5594 #define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */ 5595 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ 5596 #define TSC_IOHCR_G8_IO3_Pos (30U) 5597 #define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */ 5598 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ 5599 #define TSC_IOHCR_G8_IO4_Pos (31U) 5600 #define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */ 5601 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ 5602 5603 /******************* Bit definition for TSC_IOASCR register *****************/ 5604 #define TSC_IOASCR_G1_IO1_Pos (0U) 5605 #define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ 5606 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ 5607 #define TSC_IOASCR_G1_IO2_Pos (1U) 5608 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ 5609 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ 5610 #define TSC_IOASCR_G1_IO3_Pos (2U) 5611 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ 5612 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ 5613 #define TSC_IOASCR_G1_IO4_Pos (3U) 5614 #define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ 5615 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ 5616 #define TSC_IOASCR_G2_IO1_Pos (4U) 5617 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ 5618 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ 5619 #define TSC_IOASCR_G2_IO2_Pos (5U) 5620 #define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ 5621 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ 5622 #define TSC_IOASCR_G2_IO3_Pos (6U) 5623 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ 5624 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ 5625 #define TSC_IOASCR_G2_IO4_Pos (7U) 5626 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ 5627 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ 5628 #define TSC_IOASCR_G3_IO1_Pos (8U) 5629 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ 5630 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ 5631 #define TSC_IOASCR_G3_IO2_Pos (9U) 5632 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ 5633 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ 5634 #define TSC_IOASCR_G3_IO3_Pos (10U) 5635 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ 5636 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ 5637 #define TSC_IOASCR_G3_IO4_Pos (11U) 5638 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ 5639 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ 5640 #define TSC_IOASCR_G4_IO1_Pos (12U) 5641 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ 5642 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ 5643 #define TSC_IOASCR_G4_IO2_Pos (13U) 5644 #define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ 5645 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ 5646 #define TSC_IOASCR_G4_IO3_Pos (14U) 5647 #define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ 5648 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ 5649 #define TSC_IOASCR_G4_IO4_Pos (15U) 5650 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ 5651 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ 5652 #define TSC_IOASCR_G5_IO1_Pos (16U) 5653 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ 5654 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ 5655 #define TSC_IOASCR_G5_IO2_Pos (17U) 5656 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ 5657 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ 5658 #define TSC_IOASCR_G5_IO3_Pos (18U) 5659 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ 5660 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ 5661 #define TSC_IOASCR_G5_IO4_Pos (19U) 5662 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ 5663 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ 5664 #define TSC_IOASCR_G6_IO1_Pos (20U) 5665 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ 5666 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ 5667 #define TSC_IOASCR_G6_IO2_Pos (21U) 5668 #define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ 5669 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ 5670 #define TSC_IOASCR_G6_IO3_Pos (22U) 5671 #define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ 5672 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ 5673 #define TSC_IOASCR_G6_IO4_Pos (23U) 5674 #define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ 5675 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ 5676 #define TSC_IOASCR_G7_IO1_Pos (24U) 5677 #define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ 5678 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ 5679 #define TSC_IOASCR_G7_IO2_Pos (25U) 5680 #define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ 5681 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ 5682 #define TSC_IOASCR_G7_IO3_Pos (26U) 5683 #define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ 5684 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ 5685 #define TSC_IOASCR_G7_IO4_Pos (27U) 5686 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ 5687 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ 5688 #define TSC_IOASCR_G8_IO1_Pos (28U) 5689 #define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */ 5690 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */ 5691 #define TSC_IOASCR_G8_IO2_Pos (29U) 5692 #define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */ 5693 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */ 5694 #define TSC_IOASCR_G8_IO3_Pos (30U) 5695 #define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */ 5696 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */ 5697 #define TSC_IOASCR_G8_IO4_Pos (31U) 5698 #define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */ 5699 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */ 5700 5701 /******************* Bit definition for TSC_IOSCR register ******************/ 5702 #define TSC_IOSCR_G1_IO1_Pos (0U) 5703 #define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ 5704 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ 5705 #define TSC_IOSCR_G1_IO2_Pos (1U) 5706 #define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ 5707 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ 5708 #define TSC_IOSCR_G1_IO3_Pos (2U) 5709 #define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ 5710 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ 5711 #define TSC_IOSCR_G1_IO4_Pos (3U) 5712 #define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ 5713 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ 5714 #define TSC_IOSCR_G2_IO1_Pos (4U) 5715 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ 5716 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ 5717 #define TSC_IOSCR_G2_IO2_Pos (5U) 5718 #define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ 5719 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ 5720 #define TSC_IOSCR_G2_IO3_Pos (6U) 5721 #define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ 5722 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ 5723 #define TSC_IOSCR_G2_IO4_Pos (7U) 5724 #define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ 5725 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ 5726 #define TSC_IOSCR_G3_IO1_Pos (8U) 5727 #define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ 5728 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ 5729 #define TSC_IOSCR_G3_IO2_Pos (9U) 5730 #define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ 5731 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ 5732 #define TSC_IOSCR_G3_IO3_Pos (10U) 5733 #define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ 5734 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ 5735 #define TSC_IOSCR_G3_IO4_Pos (11U) 5736 #define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ 5737 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ 5738 #define TSC_IOSCR_G4_IO1_Pos (12U) 5739 #define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ 5740 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ 5741 #define TSC_IOSCR_G4_IO2_Pos (13U) 5742 #define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ 5743 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ 5744 #define TSC_IOSCR_G4_IO3_Pos (14U) 5745 #define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ 5746 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ 5747 #define TSC_IOSCR_G4_IO4_Pos (15U) 5748 #define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ 5749 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ 5750 #define TSC_IOSCR_G5_IO1_Pos (16U) 5751 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ 5752 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ 5753 #define TSC_IOSCR_G5_IO2_Pos (17U) 5754 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ 5755 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ 5756 #define TSC_IOSCR_G5_IO3_Pos (18U) 5757 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ 5758 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ 5759 #define TSC_IOSCR_G5_IO4_Pos (19U) 5760 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ 5761 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ 5762 #define TSC_IOSCR_G6_IO1_Pos (20U) 5763 #define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ 5764 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ 5765 #define TSC_IOSCR_G6_IO2_Pos (21U) 5766 #define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ 5767 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ 5768 #define TSC_IOSCR_G6_IO3_Pos (22U) 5769 #define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ 5770 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ 5771 #define TSC_IOSCR_G6_IO4_Pos (23U) 5772 #define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ 5773 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ 5774 #define TSC_IOSCR_G7_IO1_Pos (24U) 5775 #define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ 5776 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ 5777 #define TSC_IOSCR_G7_IO2_Pos (25U) 5778 #define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ 5779 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ 5780 #define TSC_IOSCR_G7_IO3_Pos (26U) 5781 #define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ 5782 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ 5783 #define TSC_IOSCR_G7_IO4_Pos (27U) 5784 #define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ 5785 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ 5786 #define TSC_IOSCR_G8_IO1_Pos (28U) 5787 #define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */ 5788 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */ 5789 #define TSC_IOSCR_G8_IO2_Pos (29U) 5790 #define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */ 5791 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */ 5792 #define TSC_IOSCR_G8_IO3_Pos (30U) 5793 #define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */ 5794 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */ 5795 #define TSC_IOSCR_G8_IO4_Pos (31U) 5796 #define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */ 5797 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */ 5798 5799 /******************* Bit definition for TSC_IOCCR register ******************/ 5800 #define TSC_IOCCR_G1_IO1_Pos (0U) 5801 #define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ 5802 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ 5803 #define TSC_IOCCR_G1_IO2_Pos (1U) 5804 #define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ 5805 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ 5806 #define TSC_IOCCR_G1_IO3_Pos (2U) 5807 #define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ 5808 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ 5809 #define TSC_IOCCR_G1_IO4_Pos (3U) 5810 #define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ 5811 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ 5812 #define TSC_IOCCR_G2_IO1_Pos (4U) 5813 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ 5814 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ 5815 #define TSC_IOCCR_G2_IO2_Pos (5U) 5816 #define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ 5817 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ 5818 #define TSC_IOCCR_G2_IO3_Pos (6U) 5819 #define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ 5820 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ 5821 #define TSC_IOCCR_G2_IO4_Pos (7U) 5822 #define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ 5823 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ 5824 #define TSC_IOCCR_G3_IO1_Pos (8U) 5825 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ 5826 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ 5827 #define TSC_IOCCR_G3_IO2_Pos (9U) 5828 #define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ 5829 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ 5830 #define TSC_IOCCR_G3_IO3_Pos (10U) 5831 #define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ 5832 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ 5833 #define TSC_IOCCR_G3_IO4_Pos (11U) 5834 #define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ 5835 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ 5836 #define TSC_IOCCR_G4_IO1_Pos (12U) 5837 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ 5838 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ 5839 #define TSC_IOCCR_G4_IO2_Pos (13U) 5840 #define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ 5841 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ 5842 #define TSC_IOCCR_G4_IO3_Pos (14U) 5843 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ 5844 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ 5845 #define TSC_IOCCR_G4_IO4_Pos (15U) 5846 #define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ 5847 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ 5848 #define TSC_IOCCR_G5_IO1_Pos (16U) 5849 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ 5850 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ 5851 #define TSC_IOCCR_G5_IO2_Pos (17U) 5852 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ 5853 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ 5854 #define TSC_IOCCR_G5_IO3_Pos (18U) 5855 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ 5856 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ 5857 #define TSC_IOCCR_G5_IO4_Pos (19U) 5858 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ 5859 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ 5860 #define TSC_IOCCR_G6_IO1_Pos (20U) 5861 #define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ 5862 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ 5863 #define TSC_IOCCR_G6_IO2_Pos (21U) 5864 #define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ 5865 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ 5866 #define TSC_IOCCR_G6_IO3_Pos (22U) 5867 #define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ 5868 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ 5869 #define TSC_IOCCR_G6_IO4_Pos (23U) 5870 #define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ 5871 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ 5872 #define TSC_IOCCR_G7_IO1_Pos (24U) 5873 #define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ 5874 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ 5875 #define TSC_IOCCR_G7_IO2_Pos (25U) 5876 #define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ 5877 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ 5878 #define TSC_IOCCR_G7_IO3_Pos (26U) 5879 #define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ 5880 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ 5881 #define TSC_IOCCR_G7_IO4_Pos (27U) 5882 #define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ 5883 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ 5884 #define TSC_IOCCR_G8_IO1_Pos (28U) 5885 #define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */ 5886 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */ 5887 #define TSC_IOCCR_G8_IO2_Pos (29U) 5888 #define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */ 5889 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */ 5890 #define TSC_IOCCR_G8_IO3_Pos (30U) 5891 #define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */ 5892 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */ 5893 #define TSC_IOCCR_G8_IO4_Pos (31U) 5894 #define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */ 5895 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */ 5896 5897 /******************* Bit definition for TSC_IOGCSR register *****************/ 5898 #define TSC_IOGCSR_G1E_Pos (0U) 5899 #define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ 5900 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ 5901 #define TSC_IOGCSR_G2E_Pos (1U) 5902 #define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ 5903 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ 5904 #define TSC_IOGCSR_G3E_Pos (2U) 5905 #define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ 5906 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ 5907 #define TSC_IOGCSR_G4E_Pos (3U) 5908 #define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ 5909 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ 5910 #define TSC_IOGCSR_G5E_Pos (4U) 5911 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ 5912 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ 5913 #define TSC_IOGCSR_G6E_Pos (5U) 5914 #define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ 5915 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ 5916 #define TSC_IOGCSR_G7E_Pos (6U) 5917 #define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ 5918 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ 5919 #define TSC_IOGCSR_G8E_Pos (7U) 5920 #define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */ 5921 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */ 5922 #define TSC_IOGCSR_G1S_Pos (16U) 5923 #define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ 5924 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ 5925 #define TSC_IOGCSR_G2S_Pos (17U) 5926 #define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ 5927 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ 5928 #define TSC_IOGCSR_G3S_Pos (18U) 5929 #define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ 5930 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ 5931 #define TSC_IOGCSR_G4S_Pos (19U) 5932 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ 5933 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ 5934 #define TSC_IOGCSR_G5S_Pos (20U) 5935 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ 5936 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ 5937 #define TSC_IOGCSR_G6S_Pos (21U) 5938 #define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ 5939 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ 5940 #define TSC_IOGCSR_G7S_Pos (22U) 5941 #define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ 5942 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ 5943 #define TSC_IOGCSR_G8S_Pos (23U) 5944 #define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */ 5945 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */ 5946 5947 /******************* Bit definition for TSC_IOGXCR register *****************/ 5948 #define TSC_IOGXCR_CNT_Pos (0U) 5949 #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ 5950 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ 5951 5952 /******************************************************************************/ 5953 /* */ 5954 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 5955 /* */ 5956 /******************************************************************************/ 5957 5958 /* 5959 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 5960 */ 5961 5962 /* Support of LIN feature */ 5963 #define USART_LIN_SUPPORT 5964 5965 /* Support of Smartcard feature */ 5966 #define USART_SMARTCARD_SUPPORT 5967 5968 /* Support of Irda feature */ 5969 #define USART_IRDA_SUPPORT 5970 5971 /* Support of Wake Up from Stop Mode feature */ 5972 #define USART_WUSM_SUPPORT 5973 5974 /****************** Bit definition for USART_CR1 register *******************/ 5975 #define USART_CR1_UE_Pos (0U) 5976 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 5977 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5978 #define USART_CR1_UESM_Pos (1U) 5979 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 5980 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 5981 #define USART_CR1_RE_Pos (2U) 5982 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5983 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5984 #define USART_CR1_TE_Pos (3U) 5985 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5986 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5987 #define USART_CR1_IDLEIE_Pos (4U) 5988 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5989 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5990 #define USART_CR1_RXNEIE_Pos (5U) 5991 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5992 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5993 #define USART_CR1_TCIE_Pos (6U) 5994 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5995 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5996 #define USART_CR1_TXEIE_Pos (7U) 5997 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5998 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 5999 #define USART_CR1_PEIE_Pos (8U) 6000 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 6001 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 6002 #define USART_CR1_PS_Pos (9U) 6003 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 6004 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 6005 #define USART_CR1_PCE_Pos (10U) 6006 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 6007 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 6008 #define USART_CR1_WAKE_Pos (11U) 6009 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 6010 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 6011 #define USART_CR1_M_Pos (12U) 6012 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 6013 #define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */ 6014 #define USART_CR1_MME_Pos (13U) 6015 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 6016 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 6017 #define USART_CR1_CMIE_Pos (14U) 6018 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 6019 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 6020 #define USART_CR1_OVER8_Pos (15U) 6021 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 6022 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 6023 #define USART_CR1_DEDT_Pos (16U) 6024 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 6025 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 6026 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 6027 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 6028 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 6029 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 6030 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 6031 #define USART_CR1_DEAT_Pos (21U) 6032 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 6033 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 6034 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 6035 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 6036 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 6037 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 6038 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 6039 #define USART_CR1_RTOIE_Pos (26U) 6040 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 6041 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 6042 #define USART_CR1_EOBIE_Pos (27U) 6043 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 6044 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 6045 6046 /****************** Bit definition for USART_CR2 register *******************/ 6047 #define USART_CR2_ADDM7_Pos (4U) 6048 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 6049 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 6050 #define USART_CR2_LBDL_Pos (5U) 6051 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 6052 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 6053 #define USART_CR2_LBDIE_Pos (6U) 6054 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 6055 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 6056 #define USART_CR2_LBCL_Pos (8U) 6057 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 6058 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 6059 #define USART_CR2_CPHA_Pos (9U) 6060 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 6061 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 6062 #define USART_CR2_CPOL_Pos (10U) 6063 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 6064 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 6065 #define USART_CR2_CLKEN_Pos (11U) 6066 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 6067 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 6068 #define USART_CR2_STOP_Pos (12U) 6069 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 6070 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 6071 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 6072 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 6073 #define USART_CR2_LINEN_Pos (14U) 6074 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 6075 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 6076 #define USART_CR2_SWAP_Pos (15U) 6077 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 6078 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 6079 #define USART_CR2_RXINV_Pos (16U) 6080 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 6081 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 6082 #define USART_CR2_TXINV_Pos (17U) 6083 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 6084 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 6085 #define USART_CR2_DATAINV_Pos (18U) 6086 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 6087 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 6088 #define USART_CR2_MSBFIRST_Pos (19U) 6089 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 6090 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 6091 #define USART_CR2_ABREN_Pos (20U) 6092 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 6093 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 6094 #define USART_CR2_ABRMODE_Pos (21U) 6095 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 6096 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 6097 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 6098 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 6099 #define USART_CR2_RTOEN_Pos (23U) 6100 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 6101 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 6102 #define USART_CR2_ADD_Pos (24U) 6103 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 6104 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 6105 6106 /****************** Bit definition for USART_CR3 register *******************/ 6107 #define USART_CR3_EIE_Pos (0U) 6108 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 6109 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 6110 #define USART_CR3_IREN_Pos (1U) 6111 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 6112 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 6113 #define USART_CR3_IRLP_Pos (2U) 6114 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 6115 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 6116 #define USART_CR3_HDSEL_Pos (3U) 6117 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 6118 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 6119 #define USART_CR3_NACK_Pos (4U) 6120 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 6121 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 6122 #define USART_CR3_SCEN_Pos (5U) 6123 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 6124 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 6125 #define USART_CR3_DMAR_Pos (6U) 6126 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 6127 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 6128 #define USART_CR3_DMAT_Pos (7U) 6129 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 6130 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 6131 #define USART_CR3_RTSE_Pos (8U) 6132 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 6133 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 6134 #define USART_CR3_CTSE_Pos (9U) 6135 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 6136 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 6137 #define USART_CR3_CTSIE_Pos (10U) 6138 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 6139 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 6140 #define USART_CR3_ONEBIT_Pos (11U) 6141 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 6142 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 6143 #define USART_CR3_OVRDIS_Pos (12U) 6144 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 6145 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 6146 #define USART_CR3_DDRE_Pos (13U) 6147 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 6148 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 6149 #define USART_CR3_DEM_Pos (14U) 6150 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 6151 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 6152 #define USART_CR3_DEP_Pos (15U) 6153 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 6154 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 6155 #define USART_CR3_SCARCNT_Pos (17U) 6156 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 6157 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 6158 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 6159 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 6160 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 6161 #define USART_CR3_WUS_Pos (20U) 6162 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 6163 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 6164 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 6165 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 6166 #define USART_CR3_WUFIE_Pos (22U) 6167 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 6168 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 6169 6170 /****************** Bit definition for USART_BRR register *******************/ 6171 #define USART_BRR_DIV_FRACTION_Pos (0U) 6172 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 6173 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 6174 #define USART_BRR_DIV_MANTISSA_Pos (4U) 6175 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 6176 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 6177 6178 /****************** Bit definition for USART_GTPR register ******************/ 6179 #define USART_GTPR_PSC_Pos (0U) 6180 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 6181 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 6182 #define USART_GTPR_GT_Pos (8U) 6183 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 6184 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 6185 6186 6187 /******************* Bit definition for USART_RTOR register *****************/ 6188 #define USART_RTOR_RTO_Pos (0U) 6189 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 6190 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 6191 #define USART_RTOR_BLEN_Pos (24U) 6192 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 6193 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 6194 6195 /******************* Bit definition for USART_RQR register ******************/ 6196 #define USART_RQR_ABRRQ_Pos (0U) 6197 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 6198 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 6199 #define USART_RQR_SBKRQ_Pos (1U) 6200 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 6201 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 6202 #define USART_RQR_MMRQ_Pos (2U) 6203 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 6204 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 6205 #define USART_RQR_RXFRQ_Pos (3U) 6206 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 6207 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 6208 #define USART_RQR_TXFRQ_Pos (4U) 6209 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 6210 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 6211 6212 /******************* Bit definition for USART_ISR register ******************/ 6213 #define USART_ISR_PE_Pos (0U) 6214 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 6215 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 6216 #define USART_ISR_FE_Pos (1U) 6217 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 6218 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 6219 #define USART_ISR_NE_Pos (2U) 6220 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 6221 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 6222 #define USART_ISR_ORE_Pos (3U) 6223 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 6224 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 6225 #define USART_ISR_IDLE_Pos (4U) 6226 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 6227 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 6228 #define USART_ISR_RXNE_Pos (5U) 6229 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 6230 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 6231 #define USART_ISR_TC_Pos (6U) 6232 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 6233 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 6234 #define USART_ISR_TXE_Pos (7U) 6235 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 6236 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 6237 #define USART_ISR_LBDF_Pos (8U) 6238 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 6239 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 6240 #define USART_ISR_CTSIF_Pos (9U) 6241 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 6242 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 6243 #define USART_ISR_CTS_Pos (10U) 6244 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 6245 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 6246 #define USART_ISR_RTOF_Pos (11U) 6247 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 6248 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 6249 #define USART_ISR_EOBF_Pos (12U) 6250 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 6251 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 6252 #define USART_ISR_ABRE_Pos (14U) 6253 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 6254 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 6255 #define USART_ISR_ABRF_Pos (15U) 6256 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 6257 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 6258 #define USART_ISR_BUSY_Pos (16U) 6259 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 6260 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 6261 #define USART_ISR_CMF_Pos (17U) 6262 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 6263 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 6264 #define USART_ISR_SBKF_Pos (18U) 6265 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 6266 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 6267 #define USART_ISR_RWU_Pos (19U) 6268 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 6269 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 6270 #define USART_ISR_WUF_Pos (20U) 6271 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 6272 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 6273 #define USART_ISR_TEACK_Pos (21U) 6274 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 6275 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 6276 #define USART_ISR_REACK_Pos (22U) 6277 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 6278 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 6279 6280 /******************* Bit definition for USART_ICR register ******************/ 6281 #define USART_ICR_PECF_Pos (0U) 6282 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 6283 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 6284 #define USART_ICR_FECF_Pos (1U) 6285 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 6286 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 6287 #define USART_ICR_NCF_Pos (2U) 6288 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 6289 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 6290 #define USART_ICR_ORECF_Pos (3U) 6291 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 6292 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 6293 #define USART_ICR_IDLECF_Pos (4U) 6294 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 6295 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 6296 #define USART_ICR_TCCF_Pos (6U) 6297 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 6298 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 6299 #define USART_ICR_LBDCF_Pos (8U) 6300 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 6301 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 6302 #define USART_ICR_CTSCF_Pos (9U) 6303 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 6304 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 6305 #define USART_ICR_RTOCF_Pos (11U) 6306 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 6307 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 6308 #define USART_ICR_EOBCF_Pos (12U) 6309 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 6310 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 6311 #define USART_ICR_CMCF_Pos (17U) 6312 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 6313 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 6314 #define USART_ICR_WUCF_Pos (20U) 6315 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 6316 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 6317 6318 /******************* Bit definition for USART_RDR register ******************/ 6319 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */ 6320 6321 /******************* Bit definition for USART_TDR register ******************/ 6322 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */ 6323 6324 /******************************************************************************/ 6325 /* */ 6326 /* Window WATCHDOG (WWDG) */ 6327 /* */ 6328 /******************************************************************************/ 6329 6330 /******************* Bit definition for WWDG_CR register ********************/ 6331 #define WWDG_CR_T_Pos (0U) 6332 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 6333 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 6334 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 6335 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 6336 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 6337 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 6338 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 6339 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 6340 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 6341 6342 /* Legacy defines */ 6343 #define WWDG_CR_T0 WWDG_CR_T_0 6344 #define WWDG_CR_T1 WWDG_CR_T_1 6345 #define WWDG_CR_T2 WWDG_CR_T_2 6346 #define WWDG_CR_T3 WWDG_CR_T_3 6347 #define WWDG_CR_T4 WWDG_CR_T_4 6348 #define WWDG_CR_T5 WWDG_CR_T_5 6349 #define WWDG_CR_T6 WWDG_CR_T_6 6350 6351 #define WWDG_CR_WDGA_Pos (7U) 6352 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 6353 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 6354 6355 /******************* Bit definition for WWDG_CFR register *******************/ 6356 #define WWDG_CFR_W_Pos (0U) 6357 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 6358 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 6359 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 6360 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 6361 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 6362 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 6363 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 6364 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 6365 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 6366 6367 /* Legacy defines */ 6368 #define WWDG_CFR_W0 WWDG_CFR_W_0 6369 #define WWDG_CFR_W1 WWDG_CFR_W_1 6370 #define WWDG_CFR_W2 WWDG_CFR_W_2 6371 #define WWDG_CFR_W3 WWDG_CFR_W_3 6372 #define WWDG_CFR_W4 WWDG_CFR_W_4 6373 #define WWDG_CFR_W5 WWDG_CFR_W_5 6374 #define WWDG_CFR_W6 WWDG_CFR_W_6 6375 6376 #define WWDG_CFR_WDGTB_Pos (7U) 6377 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 6378 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 6379 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 6380 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 6381 6382 /* Legacy defines */ 6383 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 6384 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 6385 6386 #define WWDG_CFR_EWI_Pos (9U) 6387 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 6388 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 6389 6390 /******************* Bit definition for WWDG_SR register ********************/ 6391 #define WWDG_SR_EWIF_Pos (0U) 6392 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 6393 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 6394 6395 /** 6396 * @} 6397 */ 6398 6399 /** 6400 * @} 6401 */ 6402 6403 6404 /** @addtogroup Exported_macro 6405 * @{ 6406 */ 6407 6408 /****************************** ADC Instances *********************************/ 6409 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 6410 6411 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC) 6412 6413 /****************************** COMP Instances *********************************/ 6414 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 6415 ((INSTANCE) == COMP2)) 6416 6417 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 6418 6419 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1) 6420 6421 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) 6422 6423 /****************************** CEC Instances *********************************/ 6424 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC) 6425 6426 /****************************** CRC Instances *********************************/ 6427 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 6428 6429 /******************************* DAC Instances ********************************/ 6430 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) 6431 6432 /******************************* DMA Instances ********************************/ 6433 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 6434 ((INSTANCE) == DMA1_Channel2) || \ 6435 ((INSTANCE) == DMA1_Channel3) || \ 6436 ((INSTANCE) == DMA1_Channel4) || \ 6437 ((INSTANCE) == DMA1_Channel5)) 6438 6439 /****************************** GPIO Instances ********************************/ 6440 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6441 ((INSTANCE) == GPIOB) || \ 6442 ((INSTANCE) == GPIOC) || \ 6443 ((INSTANCE) == GPIOD) || \ 6444 ((INSTANCE) == GPIOF)) 6445 6446 /**************************** GPIO Alternate Function Instances ***************/ 6447 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6448 ((INSTANCE) == GPIOB)) 6449 6450 /****************************** GPIO Lock Instances ***************************/ 6451 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6452 ((INSTANCE) == GPIOB)) 6453 6454 /****************************** I2C Instances *********************************/ 6455 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6456 ((INSTANCE) == I2C2)) 6457 6458 /****************** I2C Instances : wakeup capability from stop modes *********/ 6459 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 6460 6461 /****************************** I2S Instances *********************************/ 6462 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 6463 ((INSTANCE) == SPI2)) 6464 6465 /****************************** IWDG Instances ********************************/ 6466 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 6467 6468 /****************************** RTC Instances *********************************/ 6469 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 6470 6471 /****************************** SMBUS Instances *********************************/ 6472 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 6473 6474 /****************************** SPI Instances *********************************/ 6475 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 6476 ((INSTANCE) == SPI2)) 6477 6478 /****************************** TIM Instances *********************************/ 6479 #define IS_TIM_INSTANCE(INSTANCE)\ 6480 (((INSTANCE) == TIM1) || \ 6481 ((INSTANCE) == TIM2) || \ 6482 ((INSTANCE) == TIM3) || \ 6483 ((INSTANCE) == TIM6) || \ 6484 ((INSTANCE) == TIM14) || \ 6485 ((INSTANCE) == TIM15) || \ 6486 ((INSTANCE) == TIM16) || \ 6487 ((INSTANCE) == TIM17)) 6488 6489 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 6490 (((INSTANCE) == TIM1) || \ 6491 ((INSTANCE) == TIM2) || \ 6492 ((INSTANCE) == TIM3) || \ 6493 ((INSTANCE) == TIM14) || \ 6494 ((INSTANCE) == TIM15) || \ 6495 ((INSTANCE) == TIM16) || \ 6496 ((INSTANCE) == TIM17)) 6497 6498 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 6499 (((INSTANCE) == TIM1) || \ 6500 ((INSTANCE) == TIM2) || \ 6501 ((INSTANCE) == TIM3) || \ 6502 ((INSTANCE) == TIM15)) 6503 6504 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 6505 (((INSTANCE) == TIM1) || \ 6506 ((INSTANCE) == TIM2) || \ 6507 ((INSTANCE) == TIM3)) 6508 6509 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 6510 (((INSTANCE) == TIM1) || \ 6511 ((INSTANCE) == TIM2) || \ 6512 ((INSTANCE) == TIM3)) 6513 6514 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 6515 (((INSTANCE) == TIM1) || \ 6516 ((INSTANCE) == TIM2) || \ 6517 ((INSTANCE) == TIM3)) 6518 6519 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 6520 (((INSTANCE) == TIM1) || \ 6521 ((INSTANCE) == TIM2) || \ 6522 ((INSTANCE) == TIM3)) 6523 6524 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 6525 (((INSTANCE) == TIM1) || \ 6526 ((INSTANCE) == TIM2) || \ 6527 ((INSTANCE) == TIM3) || \ 6528 ((INSTANCE) == TIM15)) 6529 6530 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 6531 (((INSTANCE) == TIM1) || \ 6532 ((INSTANCE) == TIM2) || \ 6533 ((INSTANCE) == TIM3) || \ 6534 ((INSTANCE) == TIM15)) 6535 6536 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 6537 (((INSTANCE) == TIM1) || \ 6538 ((INSTANCE) == TIM2) || \ 6539 ((INSTANCE) == TIM3)) 6540 6541 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 6542 (((INSTANCE) == TIM1) || \ 6543 ((INSTANCE) == TIM2) || \ 6544 ((INSTANCE) == TIM3)) 6545 6546 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ 6547 (((INSTANCE) == TIM1)) 6548 6549 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ 6550 (((INSTANCE) == TIM1)) 6551 6552 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 6553 (((INSTANCE) == TIM1) || \ 6554 ((INSTANCE) == TIM2) || \ 6555 ((INSTANCE) == TIM3)) 6556 6557 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 6558 (((INSTANCE) == TIM1) || \ 6559 ((INSTANCE) == TIM2) || \ 6560 ((INSTANCE) == TIM3) || \ 6561 ((INSTANCE) == TIM6) || \ 6562 ((INSTANCE) == TIM15)) 6563 6564 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 6565 (((INSTANCE) == TIM1) || \ 6566 ((INSTANCE) == TIM2) || \ 6567 ((INSTANCE) == TIM3) || \ 6568 ((INSTANCE) == TIM15)) 6569 6570 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ 6571 ((INSTANCE) == TIM2) 6572 6573 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 6574 (((INSTANCE) == TIM1) || \ 6575 ((INSTANCE) == TIM2) || \ 6576 ((INSTANCE) == TIM3) || \ 6577 ((INSTANCE) == TIM15) || \ 6578 ((INSTANCE) == TIM16) || \ 6579 ((INSTANCE) == TIM17)) 6580 6581 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 6582 (((INSTANCE) == TIM1) || \ 6583 ((INSTANCE) == TIM15) || \ 6584 ((INSTANCE) == TIM16) || \ 6585 ((INSTANCE) == TIM17)) 6586 6587 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 6588 ((((INSTANCE) == TIM1) && \ 6589 (((CHANNEL) == TIM_CHANNEL_1) || \ 6590 ((CHANNEL) == TIM_CHANNEL_2) || \ 6591 ((CHANNEL) == TIM_CHANNEL_3) || \ 6592 ((CHANNEL) == TIM_CHANNEL_4))) \ 6593 || \ 6594 (((INSTANCE) == TIM2) && \ 6595 (((CHANNEL) == TIM_CHANNEL_1) || \ 6596 ((CHANNEL) == TIM_CHANNEL_2) || \ 6597 ((CHANNEL) == TIM_CHANNEL_3) || \ 6598 ((CHANNEL) == TIM_CHANNEL_4))) \ 6599 || \ 6600 (((INSTANCE) == TIM3) && \ 6601 (((CHANNEL) == TIM_CHANNEL_1) || \ 6602 ((CHANNEL) == TIM_CHANNEL_2) || \ 6603 ((CHANNEL) == TIM_CHANNEL_3) || \ 6604 ((CHANNEL) == TIM_CHANNEL_4))) \ 6605 || \ 6606 (((INSTANCE) == TIM14) && \ 6607 (((CHANNEL) == TIM_CHANNEL_1))) \ 6608 || \ 6609 (((INSTANCE) == TIM15) && \ 6610 (((CHANNEL) == TIM_CHANNEL_1) || \ 6611 ((CHANNEL) == TIM_CHANNEL_2))) \ 6612 || \ 6613 (((INSTANCE) == TIM16) && \ 6614 (((CHANNEL) == TIM_CHANNEL_1))) \ 6615 || \ 6616 (((INSTANCE) == TIM17) && \ 6617 (((CHANNEL) == TIM_CHANNEL_1)))) 6618 6619 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 6620 ((((INSTANCE) == TIM1) && \ 6621 (((CHANNEL) == TIM_CHANNEL_1) || \ 6622 ((CHANNEL) == TIM_CHANNEL_2) || \ 6623 ((CHANNEL) == TIM_CHANNEL_3))) \ 6624 || \ 6625 (((INSTANCE) == TIM15) && \ 6626 ((CHANNEL) == TIM_CHANNEL_1)) \ 6627 || \ 6628 (((INSTANCE) == TIM16) && \ 6629 ((CHANNEL) == TIM_CHANNEL_1)) \ 6630 || \ 6631 (((INSTANCE) == TIM17) && \ 6632 ((CHANNEL) == TIM_CHANNEL_1))) 6633 6634 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 6635 (((INSTANCE) == TIM1) || \ 6636 ((INSTANCE) == TIM2) || \ 6637 ((INSTANCE) == TIM3)) 6638 6639 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 6640 (((INSTANCE) == TIM1) || \ 6641 ((INSTANCE) == TIM15) || \ 6642 ((INSTANCE) == TIM16) || \ 6643 ((INSTANCE) == TIM17)) 6644 6645 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 6646 (((INSTANCE) == TIM1) || \ 6647 ((INSTANCE) == TIM2) || \ 6648 ((INSTANCE) == TIM3) || \ 6649 ((INSTANCE) == TIM14) || \ 6650 ((INSTANCE) == TIM15) || \ 6651 ((INSTANCE) == TIM16) || \ 6652 ((INSTANCE) == TIM17)) 6653 6654 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 6655 (((INSTANCE) == TIM1) || \ 6656 ((INSTANCE) == TIM2) || \ 6657 ((INSTANCE) == TIM3) || \ 6658 ((INSTANCE) == TIM6) || \ 6659 ((INSTANCE) == TIM15) || \ 6660 ((INSTANCE) == TIM16) || \ 6661 ((INSTANCE) == TIM17)) 6662 6663 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 6664 (((INSTANCE) == TIM1) || \ 6665 ((INSTANCE) == TIM2) || \ 6666 ((INSTANCE) == TIM3) || \ 6667 ((INSTANCE) == TIM15) || \ 6668 ((INSTANCE) == TIM16) || \ 6669 ((INSTANCE) == TIM17)) 6670 6671 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 6672 (((INSTANCE) == TIM1) || \ 6673 ((INSTANCE) == TIM15) || \ 6674 ((INSTANCE) == TIM16) || \ 6675 ((INSTANCE) == TIM17)) 6676 6677 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ 6678 ((INSTANCE) == TIM14) 6679 6680 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ 6681 ((INSTANCE) == TIM1) 6682 6683 /****************************** TSC Instances *********************************/ 6684 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) 6685 6686 /*********************** UART Instances : IRDA mode ***************************/ 6687 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6688 6689 /********************* UART Instances : Smard card mode ***********************/ 6690 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6691 6692 /******************** USART Instances : Synchronous mode **********************/ 6693 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6694 ((INSTANCE) == USART2)) 6695 6696 /******************** USART Instances : auto Baud rate detection **************/ 6697 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6698 6699 /******************** UART Instances : Asynchronous mode **********************/ 6700 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6701 ((INSTANCE) == USART2)) 6702 6703 /******************** UART Instances : Half-Duplex mode **********************/ 6704 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6705 ((INSTANCE) == USART2)) 6706 6707 /****************** UART Instances : Hardware Flow control ********************/ 6708 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6709 ((INSTANCE) == USART2)) 6710 6711 /****************** UART Instances : LIN mode ********************/ 6712 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6713 6714 /****************** UART Instances : wakeup from stop mode ********************/ 6715 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6716 /* Old macro definition maintained for legacy purpose */ 6717 #define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE 6718 6719 /****************** UART Instances : Driver enable detection ********************/ 6720 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6721 ((INSTANCE) == USART2)) 6722 6723 /****************************** WWDG Instances ********************************/ 6724 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 6725 6726 /** 6727 * @} 6728 */ 6729 6730 6731 /******************************************************************************/ 6732 /* For a painless codes migration between the STM32F0xx device product */ 6733 /* lines, the aliases defined below are put in place to overcome the */ 6734 /* differences in the interrupt handlers and IRQn definitions. */ 6735 /* No need to update developed interrupt code when moving across */ 6736 /* product lines within the same STM32F0 Family */ 6737 /******************************************************************************/ 6738 6739 /* Aliases for __IRQn */ 6740 #define ADC1_IRQn ADC1_COMP_IRQn 6741 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 6742 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 6743 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 6744 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 6745 #define PVD_VDDIO2_IRQn PVD_IRQn 6746 #define VDDIO2_IRQn PVD_IRQn 6747 #define RCC_CRS_IRQn RCC_IRQn 6748 #define TIM6_IRQn TIM6_DAC_IRQn 6749 6750 #define SVC_IRQn SVCall_IRQn 6751 6752 /* Aliases for __IRQHandler */ 6753 #define ADC1_IRQHandler ADC1_COMP_IRQHandler 6754 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 6755 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 6756 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 6757 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 6758 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler 6759 #define VDDIO2_IRQHandler PVD_IRQHandler 6760 #define RCC_CRS_IRQHandler RCC_IRQHandler 6761 #define TIM6_IRQHandler TIM6_DAC_IRQHandler 6762 6763 #ifdef __cplusplus 6764 } 6765 #endif /* __cplusplus */ 6766 6767 #endif /* __STM32F051x8_H */ 6768 6769 /** 6770 * @} 6771 */ 6772 6773 /** 6774 * @} 6775 */ 6776 6777
