1 /** 2 ****************************************************************************** 3 * @file stm32f301x8.h 4 * @author MCD Application Team 5 * @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File. 6 * 7 * This file contains: 8 * - Data structures and the address mapping for all peripherals 9 * - Peripheral's registers declarations and bits definition 10 * - Macros to access peripheral's registers hardware 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2016 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 */ 24 25 /** @addtogroup CMSIS_Device 26 * @{ 27 */ 28 29 /** @addtogroup stm32f301x8 30 * @{ 31 */ 32 33 #ifndef __STM32F301x8_H 34 #define __STM32F301x8_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 /** @addtogroup Configuration_section_for_CMSIS 41 * @{ 42 */ 43 44 /** 45 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 46 */ 47 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ 48 #define __MPU_PRESENT 0U /*!< STM32F301x8 devices do not provide an MPU */ 49 #define __NVIC_PRIO_BITS 4U /*!< STM32F301x8 devices use 4 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 51 #define __FPU_PRESENT 1U /*!< STM32F301x8 devices provide an FPU */ 52 53 /** 54 * @} 55 */ 56 57 /** @addtogroup Peripheral_interrupt_number_definition 58 * @{ 59 */ 60 61 /** 62 * @brief STM32F301x8 devices Interrupt Number Definition, according to the selected device 63 * in @ref Library_configuration_section 64 */ 65 typedef enum 66 { 67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 68 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 69 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 70 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 71 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 72 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 73 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 74 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 75 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 76 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 77 /****** STM32 specific Interrupt Numbers **********************************************************************/ 78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 79 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 80 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ 81 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ 82 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 83 RCC_IRQn = 5, /*!< RCC global Interrupt */ 84 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 85 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 86 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ 87 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 88 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 89 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 90 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 91 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 92 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 93 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 94 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 95 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 96 ADC1_IRQn = 18, /*!< ADC1 Interrupts */ 97 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 98 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 99 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 100 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 101 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 102 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 103 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 104 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 105 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ 106 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 107 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 108 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 109 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ 110 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ 111 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 112 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ 113 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 114 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ 115 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ 116 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ 117 I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */ 118 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ 119 FPU_IRQn = 81, /*!< Floating point Interrupt */ 120 } IRQn_Type; 121 122 /** 123 * @} 124 */ 125 126 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 127 #include "system_stm32f3xx.h" /* STM32F3xx System Header */ 128 #include <stdint.h> 129 130 /** @addtogroup Peripheral_registers_structures 131 * @{ 132 */ 133 134 /** 135 * @brief Analog to Digital Converter 136 */ 137 138 typedef struct 139 { 140 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ 141 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ 142 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 143 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ 144 uint32_t RESERVED0; /*!< Reserved, 0x010 */ 145 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ 146 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ 147 uint32_t RESERVED1; /*!< Reserved, 0x01C */ 148 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ 149 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ 150 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ 151 uint32_t RESERVED2; /*!< Reserved, 0x02C */ 152 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 153 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 154 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 155 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 156 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ 157 uint32_t RESERVED3; /*!< Reserved, 0x044 */ 158 uint32_t RESERVED4; /*!< Reserved, 0x048 */ 159 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ 160 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ 161 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ 162 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ 163 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ 164 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ 165 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ 166 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ 167 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ 168 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ 169 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ 170 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ 171 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ 172 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ 173 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ 174 uint32_t RESERVED9; /*!< Reserved, 0x0AC */ 175 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ 176 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ 177 178 } ADC_TypeDef; 179 180 typedef struct 181 { 182 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ 183 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ 184 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ 185 __IO uint32_t CDR; /*!< ADC common regular data register for dual 186 AND triple modes, Address offset: ADC1/3 base address + 0x30C */ 187 } ADC_Common_TypeDef; 188 189 /** 190 * @brief Analog Comparators 191 */ 192 typedef struct 193 { 194 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 195 } COMP_TypeDef; 196 197 typedef struct 198 { 199 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 200 } COMP_Common_TypeDef; 201 202 /** 203 * @brief CRC calculation unit 204 */ 205 206 typedef struct 207 { 208 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 209 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 210 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 211 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 212 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 213 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 214 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 215 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 216 } CRC_TypeDef; 217 218 /** 219 * @brief Digital to Analog Converter 220 */ 221 222 typedef struct 223 { 224 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 225 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 226 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 227 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 228 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 229 __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */ 230 __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */ 231 __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */ 232 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 233 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 234 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 235 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 236 __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */ 237 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 238 } DAC_TypeDef; 239 240 /** 241 * @brief Debug MCU 242 */ 243 244 typedef struct 245 { 246 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 247 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 248 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 249 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 250 }DBGMCU_TypeDef; 251 252 /** 253 * @brief DMA Controller 254 */ 255 256 typedef struct 257 { 258 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 259 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 260 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 261 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 262 } DMA_Channel_TypeDef; 263 264 typedef struct 265 { 266 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 267 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 268 } DMA_TypeDef; 269 270 /** 271 * @brief External Interrupt/Event Controller 272 */ 273 274 typedef struct 275 { 276 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 277 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 278 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 279 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 280 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 281 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 282 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 283 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 284 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ 285 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ 286 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ 287 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ 288 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ 289 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ 290 }EXTI_TypeDef; 291 292 /** 293 * @brief FLASH Registers 294 */ 295 296 typedef struct 297 { 298 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ 299 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ 300 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ 301 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ 302 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ 303 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ 304 uint32_t RESERVED; /*!< Reserved, 0x18 */ 305 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ 306 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ 307 308 } FLASH_TypeDef; 309 310 /** 311 * @brief Option Bytes Registers 312 */ 313 typedef struct 314 { 315 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ 316 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ 317 __IO uint16_t Data0; /*!<FLASH option byte Data0 options, Address offset: 0x04 */ 318 __IO uint16_t Data1; /*!<FLASH option byte Data1 options, Address offset: 0x06 */ 319 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ 320 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ 321 } OB_TypeDef; 322 323 /** 324 * @brief General Purpose I/O 325 */ 326 327 typedef struct 328 { 329 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 330 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 331 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 332 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 333 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 334 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 335 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ 336 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 337 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 338 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 339 }GPIO_TypeDef; 340 341 /** 342 * @brief Operational Amplifier (OPAMP) 343 */ 344 345 typedef struct 346 { 347 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ 348 } OPAMP_TypeDef; 349 350 /** 351 * @brief System configuration controller 352 */ 353 354 typedef struct 355 { 356 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 357 uint32_t RESERVED; /*!< Reserved, 0x04 */ 358 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ 359 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 360 } SYSCFG_TypeDef; 361 362 /** 363 * @brief Inter-integrated Circuit Interface 364 */ 365 366 typedef struct 367 { 368 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 369 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 370 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 371 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 372 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 373 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 374 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 375 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 376 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 377 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 378 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 379 }I2C_TypeDef; 380 381 /** 382 * @brief Independent WATCHDOG 383 */ 384 385 typedef struct 386 { 387 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 388 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 389 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 390 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 391 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 392 } IWDG_TypeDef; 393 394 /** 395 * @brief Power Control 396 */ 397 398 typedef struct 399 { 400 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 401 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 402 } PWR_TypeDef; 403 404 /** 405 * @brief Reset and Clock Control 406 */ 407 typedef struct 408 { 409 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 410 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 411 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 412 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 413 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 414 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 415 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 416 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 417 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 418 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 419 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 420 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 421 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 422 } RCC_TypeDef; 423 424 /** 425 * @brief Real-Time Clock 426 */ 427 428 typedef struct 429 { 430 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 431 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 432 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 433 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 434 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 435 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 436 uint32_t RESERVED0; /*!< Reserved, 0x18 */ 437 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 438 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 439 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 440 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 441 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 442 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 443 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 444 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 445 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 446 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 447 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 448 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 449 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 450 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 451 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 452 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 453 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 454 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 455 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 456 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 457 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 458 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 459 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 460 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 461 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 462 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 463 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 464 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 465 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 466 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 467 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 468 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 469 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 470 } RTC_TypeDef; 471 472 473 /** 474 * @brief Serial Peripheral Interface 475 */ 476 477 typedef struct 478 { 479 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ 480 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 481 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 482 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 483 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ 484 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ 485 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ 486 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 487 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 488 } SPI_TypeDef; 489 490 /** 491 * @brief TIM 492 */ 493 typedef struct 494 { 495 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 496 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 497 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 498 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 499 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 500 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 501 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 502 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 503 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 504 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 505 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 506 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 507 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 508 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 509 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 510 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 511 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 512 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 513 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 514 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 515 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 516 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 517 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 518 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ 519 } TIM_TypeDef; 520 521 /** 522 * @brief Touch Sensing Controller (TSC) 523 */ 524 typedef struct 525 { 526 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 527 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 528 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 529 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 530 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 531 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 532 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 533 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 534 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 535 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 536 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 537 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 538 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 539 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ 540 } TSC_TypeDef; 541 542 /** 543 * @brief Universal Synchronous Asynchronous Receiver Transmitter 544 */ 545 546 typedef struct 547 { 548 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 549 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 550 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 551 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 552 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 553 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 554 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 555 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 556 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 557 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 558 uint16_t RESERVED1; /*!< Reserved, 0x26 */ 559 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 560 uint16_t RESERVED2; /*!< Reserved, 0x2A */ 561 } USART_TypeDef; 562 563 /** 564 * @brief Window WATCHDOG 565 */ 566 typedef struct 567 { 568 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 569 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 570 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 571 } WWDG_TypeDef; 572 573 /** 574 * @} 575 */ 576 577 /** @addtogroup Peripheral_memory_map 578 * @{ 579 */ 580 581 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 582 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 583 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 584 #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ 585 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ 586 587 588 /*!< Peripheral memory map */ 589 #define APB1PERIPH_BASE PERIPH_BASE 590 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 591 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 592 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 593 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) 594 595 /*!< APB1 peripherals */ 596 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 597 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 598 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 599 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 600 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 601 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400UL) 602 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 603 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) 604 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000UL) 605 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 606 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 607 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 608 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 609 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 610 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL) 611 #define DAC_BASE DAC1_BASE 612 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800UL) 613 614 /*!< APB2 peripherals */ 615 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 616 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL) 617 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL) 618 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL) 619 #define COMP_BASE COMP2_BASE 620 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL) 621 #define OPAMP_BASE OPAMP2_BASE 622 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 623 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 624 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 625 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) 626 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 627 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 628 629 /*!< AHB1 peripherals */ 630 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) 631 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL) 632 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL) 633 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL) 634 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL) 635 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL) 636 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL) 637 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL) 638 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL) 639 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ 640 #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ 641 #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ 642 #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ 643 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) 644 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) 645 646 /*!< AHB2 peripherals */ 647 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) 648 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) 649 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) 650 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) 651 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) 652 653 /*!< AHB3 peripherals */ 654 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL) 655 #define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL) 656 657 #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ 658 /** 659 * @} 660 */ 661 662 /** @addtogroup Peripheral_declaration 663 * @{ 664 */ 665 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 666 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 667 #define RTC ((RTC_TypeDef *) RTC_BASE) 668 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 669 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 670 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) 671 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 672 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 673 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) 674 #define USART2 ((USART_TypeDef *) USART2_BASE) 675 #define USART3 ((USART_TypeDef *) USART3_BASE) 676 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 677 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 678 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 679 #define PWR ((PWR_TypeDef *) PWR_BASE) 680 #define DAC ((DAC_TypeDef *) DAC_BASE) 681 #define DAC1 ((DAC_TypeDef *) DAC1_BASE) 682 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 683 #define COMP4 ((COMP_TypeDef *) COMP4_BASE) 684 #define COMP6 ((COMP_TypeDef *) COMP6_BASE) 685 /* Legacy define */ 686 #define COMP ((COMP_TypeDef *) COMP_BASE) 687 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 688 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) 689 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 690 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 691 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 692 #define USART1 ((USART_TypeDef *) USART1_BASE) 693 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 694 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 695 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 696 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 697 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 698 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 699 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 700 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 701 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 702 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 703 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 704 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 705 #define RCC ((RCC_TypeDef *) RCC_BASE) 706 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 707 #define OB ((OB_TypeDef *) OB_BASE) 708 #define CRC ((CRC_TypeDef *) CRC_BASE) 709 #define TSC ((TSC_TypeDef *) TSC_BASE) 710 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 711 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 712 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 713 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 714 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 715 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 716 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) 717 718 /** 719 * @} 720 */ 721 722 /** @addtogroup Exported_constants 723 * @{ 724 */ 725 726 /** @addtogroup Hardware_Constant_Definition 727 * @{ 728 */ 729 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 730 731 /** 732 * @} 733 */ 734 735 /** @addtogroup Peripheral_Registers_Bits_Definition 736 * @{ 737 */ 738 739 /******************************************************************************/ 740 /* Peripheral Registers_Bits_Definition */ 741 /******************************************************************************/ 742 743 /******************************************************************************/ 744 /* */ 745 /* Analog to Digital Converter SAR (ADC) */ 746 /* */ 747 /******************************************************************************/ 748 749 #define ADC5_V1_1 /*!< ADC IP version */ 750 751 /* 752 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 753 */ 754 /* Note: No specific macro feature on this device */ 755 756 /******************** Bit definition for ADC_ISR register ********************/ 757 #define ADC_ISR_ADRDY_Pos (0U) 758 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 759 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 760 #define ADC_ISR_EOSMP_Pos (1U) 761 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 762 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 763 #define ADC_ISR_EOC_Pos (2U) 764 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 765 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 766 #define ADC_ISR_EOS_Pos (3U) 767 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 768 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 769 #define ADC_ISR_OVR_Pos (4U) 770 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 771 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 772 #define ADC_ISR_JEOC_Pos (5U) 773 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ 774 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ 775 #define ADC_ISR_JEOS_Pos (6U) 776 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ 777 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 778 #define ADC_ISR_AWD1_Pos (7U) 779 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 780 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 781 #define ADC_ISR_AWD2_Pos (8U) 782 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 783 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 784 #define ADC_ISR_AWD3_Pos (9U) 785 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 786 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 787 #define ADC_ISR_JQOVF_Pos (10U) 788 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ 789 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ 790 791 /* Legacy defines */ 792 #define ADC_ISR_ADRD (ADC_ISR_ADRDY) 793 794 /******************** Bit definition for ADC_IER register ********************/ 795 #define ADC_IER_ADRDYIE_Pos (0U) 796 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 797 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 798 #define ADC_IER_EOSMPIE_Pos (1U) 799 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 800 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 801 #define ADC_IER_EOCIE_Pos (2U) 802 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 803 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 804 #define ADC_IER_EOSIE_Pos (3U) 805 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 806 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 807 #define ADC_IER_OVRIE_Pos (4U) 808 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 809 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 810 #define ADC_IER_JEOCIE_Pos (5U) 811 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ 812 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ 813 #define ADC_IER_JEOSIE_Pos (6U) 814 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ 815 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 816 #define ADC_IER_AWD1IE_Pos (7U) 817 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 818 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 819 #define ADC_IER_AWD2IE_Pos (8U) 820 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 821 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 822 #define ADC_IER_AWD3IE_Pos (9U) 823 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 824 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 825 #define ADC_IER_JQOVFIE_Pos (10U) 826 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ 827 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ 828 829 /* Legacy defines */ 830 #define ADC_IER_RDY (ADC_IER_ADRDYIE) 831 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) 832 #define ADC_IER_EOC (ADC_IER_EOCIE) 833 #define ADC_IER_EOS (ADC_IER_EOSIE) 834 #define ADC_IER_OVR (ADC_IER_OVRIE) 835 #define ADC_IER_JEOC (ADC_IER_JEOCIE) 836 #define ADC_IER_JEOS (ADC_IER_JEOSIE) 837 #define ADC_IER_AWD1 (ADC_IER_AWD1IE) 838 #define ADC_IER_AWD2 (ADC_IER_AWD2IE) 839 #define ADC_IER_AWD3 (ADC_IER_AWD3IE) 840 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) 841 842 /******************** Bit definition for ADC_CR register ********************/ 843 #define ADC_CR_ADEN_Pos (0U) 844 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 845 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 846 #define ADC_CR_ADDIS_Pos (1U) 847 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 848 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 849 #define ADC_CR_ADSTART_Pos (2U) 850 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 851 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 852 #define ADC_CR_JADSTART_Pos (3U) 853 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ 854 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ 855 #define ADC_CR_ADSTP_Pos (4U) 856 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 857 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 858 #define ADC_CR_JADSTP_Pos (5U) 859 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ 860 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ 861 #define ADC_CR_ADVREGEN_Pos (28U) 862 #define ADC_CR_ADVREGEN_Msk (0x3UL << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */ 863 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 864 #define ADC_CR_ADVREGEN_0 (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 865 #define ADC_CR_ADVREGEN_1 (0x2UL << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */ 866 #define ADC_CR_ADCALDIF_Pos (30U) 867 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ 868 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ 869 #define ADC_CR_ADCAL_Pos (31U) 870 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 871 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 872 873 /******************** Bit definition for ADC_CFGR register ******************/ 874 #define ADC_CFGR_DMAEN_Pos (0U) 875 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ 876 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ 877 #define ADC_CFGR_DMACFG_Pos (1U) 878 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ 879 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ 880 881 #define ADC_CFGR_RES_Pos (3U) 882 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ 883 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ 884 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ 885 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ 886 887 #define ADC_CFGR_ALIGN_Pos (5U) 888 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ 889 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ 890 891 #define ADC_CFGR_EXTSEL_Pos (6U) 892 #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ 893 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ 894 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ 895 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ 896 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ 897 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ 898 899 #define ADC_CFGR_EXTEN_Pos (10U) 900 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ 901 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 902 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ 903 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ 904 905 #define ADC_CFGR_OVRMOD_Pos (12U) 906 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ 907 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 908 #define ADC_CFGR_CONT_Pos (13U) 909 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ 910 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ 911 #define ADC_CFGR_AUTDLY_Pos (14U) 912 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ 913 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ 914 915 #define ADC_CFGR_DISCEN_Pos (16U) 916 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ 917 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 918 919 #define ADC_CFGR_DISCNUM_Pos (17U) 920 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ 921 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ 922 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ 923 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ 924 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ 925 926 #define ADC_CFGR_JDISCEN_Pos (20U) 927 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ 928 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ 929 #define ADC_CFGR_JQM_Pos (21U) 930 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ 931 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ 932 #define ADC_CFGR_AWD1SGL_Pos (22U) 933 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ 934 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 935 #define ADC_CFGR_AWD1EN_Pos (23U) 936 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ 937 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 938 #define ADC_CFGR_JAWD1EN_Pos (24U) 939 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ 940 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 941 #define ADC_CFGR_JAUTO_Pos (25U) 942 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ 943 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 944 945 #define ADC_CFGR_AWD1CH_Pos (26U) 946 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ 947 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 948 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ 949 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ 950 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ 951 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ 952 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ 953 954 /* Legacy defines */ 955 #define ADC_CFGR_AUTOFF_Pos (15U) 956 #define ADC_CFGR_AUTOFF_Msk (0x1UL << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */ 957 #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */ 958 959 /******************** Bit definition for ADC_SMPR1 register *****************/ 960 #define ADC_SMPR1_SMP0_Pos (0U) 961 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ 962 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 963 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ 964 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ 965 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ 966 967 #define ADC_SMPR1_SMP1_Pos (3U) 968 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ 969 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 970 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ 971 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ 972 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ 973 974 #define ADC_SMPR1_SMP2_Pos (6U) 975 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ 976 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 977 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ 978 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ 979 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ 980 981 #define ADC_SMPR1_SMP3_Pos (9U) 982 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ 983 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 984 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ 985 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ 986 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ 987 988 #define ADC_SMPR1_SMP4_Pos (12U) 989 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ 990 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 991 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ 992 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ 993 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ 994 995 #define ADC_SMPR1_SMP5_Pos (15U) 996 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ 997 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 998 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ 999 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ 1000 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ 1001 1002 #define ADC_SMPR1_SMP6_Pos (18U) 1003 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ 1004 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1005 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ 1006 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ 1007 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ 1008 1009 #define ADC_SMPR1_SMP7_Pos (21U) 1010 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ 1011 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1012 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ 1013 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ 1014 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ 1015 1016 #define ADC_SMPR1_SMP8_Pos (24U) 1017 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ 1018 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1019 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ 1020 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ 1021 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ 1022 1023 #define ADC_SMPR1_SMP9_Pos (27U) 1024 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ 1025 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1026 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ 1027 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ 1028 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ 1029 1030 /******************** Bit definition for ADC_SMPR2 register *****************/ 1031 #define ADC_SMPR2_SMP10_Pos (0U) 1032 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1033 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1034 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1035 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1036 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1037 1038 #define ADC_SMPR2_SMP11_Pos (3U) 1039 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1040 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1041 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1042 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1043 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1044 1045 #define ADC_SMPR2_SMP12_Pos (6U) 1046 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1047 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1048 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1049 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1050 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1051 1052 #define ADC_SMPR2_SMP13_Pos (9U) 1053 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1054 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1055 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1056 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1057 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1058 1059 #define ADC_SMPR2_SMP14_Pos (12U) 1060 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1061 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1062 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1063 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1064 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1065 1066 #define ADC_SMPR2_SMP15_Pos (15U) 1067 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1068 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 1069 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1070 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1071 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1072 1073 #define ADC_SMPR2_SMP16_Pos (18U) 1074 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1075 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1076 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1077 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1078 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1079 1080 #define ADC_SMPR2_SMP17_Pos (21U) 1081 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1082 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1083 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1084 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1085 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1086 1087 #define ADC_SMPR2_SMP18_Pos (24U) 1088 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1089 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1090 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1091 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1092 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1093 1094 /******************** Bit definition for ADC_TR1 register *******************/ 1095 #define ADC_TR1_LT1_Pos (0U) 1096 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 1097 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 1098 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 1099 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 1100 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 1101 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 1102 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 1103 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 1104 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 1105 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 1106 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 1107 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 1108 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 1109 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 1110 1111 #define ADC_TR1_HT1_Pos (16U) 1112 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 1113 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 1114 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 1115 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 1116 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 1117 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 1118 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 1119 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 1120 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 1121 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 1122 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 1123 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 1124 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 1125 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 1126 1127 /******************** Bit definition for ADC_TR2 register *******************/ 1128 #define ADC_TR2_LT2_Pos (0U) 1129 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ 1130 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1131 #define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ 1132 #define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ 1133 #define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ 1134 #define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ 1135 #define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ 1136 #define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ 1137 #define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ 1138 #define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ 1139 1140 #define ADC_TR2_HT2_Pos (16U) 1141 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ 1142 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1143 #define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ 1144 #define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ 1145 #define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ 1146 #define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ 1147 #define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ 1148 #define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ 1149 #define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ 1150 #define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ 1151 1152 /******************** Bit definition for ADC_TR3 register *******************/ 1153 #define ADC_TR3_LT3_Pos (0U) 1154 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ 1155 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1156 #define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ 1157 #define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ 1158 #define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ 1159 #define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ 1160 #define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ 1161 #define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ 1162 #define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ 1163 #define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ 1164 1165 #define ADC_TR3_HT3_Pos (16U) 1166 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ 1167 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1168 #define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ 1169 #define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ 1170 #define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ 1171 #define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ 1172 #define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ 1173 #define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ 1174 #define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ 1175 #define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ 1176 1177 /******************** Bit definition for ADC_SQR1 register ******************/ 1178 #define ADC_SQR1_L_Pos (0U) 1179 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ 1180 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1181 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ 1182 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ 1183 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ 1184 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ 1185 1186 #define ADC_SQR1_SQ1_Pos (6U) 1187 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ 1188 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1189 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ 1190 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ 1191 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ 1192 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ 1193 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ 1194 1195 #define ADC_SQR1_SQ2_Pos (12U) 1196 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ 1197 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1198 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ 1199 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ 1200 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ 1201 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ 1202 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ 1203 1204 #define ADC_SQR1_SQ3_Pos (18U) 1205 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ 1206 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1207 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ 1208 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ 1209 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ 1210 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ 1211 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ 1212 1213 #define ADC_SQR1_SQ4_Pos (24U) 1214 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ 1215 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1216 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ 1217 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ 1218 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ 1219 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ 1220 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ 1221 1222 /******************** Bit definition for ADC_SQR2 register ******************/ 1223 #define ADC_SQR2_SQ5_Pos (0U) 1224 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ 1225 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1226 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ 1227 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ 1228 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ 1229 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ 1230 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ 1231 1232 #define ADC_SQR2_SQ6_Pos (6U) 1233 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ 1234 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1235 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ 1236 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ 1237 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ 1238 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ 1239 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ 1240 1241 #define ADC_SQR2_SQ7_Pos (12U) 1242 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ 1243 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1244 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ 1245 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ 1246 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ 1247 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ 1248 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ 1249 1250 #define ADC_SQR2_SQ8_Pos (18U) 1251 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ 1252 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1253 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ 1254 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ 1255 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ 1256 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ 1257 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ 1258 1259 #define ADC_SQR2_SQ9_Pos (24U) 1260 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ 1261 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1262 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ 1263 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ 1264 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ 1265 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ 1266 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ 1267 1268 /******************** Bit definition for ADC_SQR3 register ******************/ 1269 #define ADC_SQR3_SQ10_Pos (0U) 1270 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ 1271 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1272 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ 1273 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ 1274 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ 1275 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ 1276 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ 1277 1278 #define ADC_SQR3_SQ11_Pos (6U) 1279 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ 1280 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1281 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ 1282 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ 1283 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ 1284 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ 1285 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ 1286 1287 #define ADC_SQR3_SQ12_Pos (12U) 1288 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ 1289 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1290 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ 1291 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ 1292 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ 1293 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ 1294 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ 1295 1296 #define ADC_SQR3_SQ13_Pos (18U) 1297 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ 1298 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1299 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ 1300 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ 1301 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ 1302 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ 1303 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ 1304 1305 #define ADC_SQR3_SQ14_Pos (24U) 1306 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ 1307 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1308 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ 1309 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ 1310 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ 1311 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ 1312 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ 1313 1314 /******************** Bit definition for ADC_SQR4 register ******************/ 1315 #define ADC_SQR4_SQ15_Pos (0U) 1316 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ 1317 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1318 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ 1319 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ 1320 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ 1321 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ 1322 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ 1323 1324 #define ADC_SQR4_SQ16_Pos (6U) 1325 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ 1326 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1327 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ 1328 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ 1329 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ 1330 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ 1331 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ 1332 1333 /******************** Bit definition for ADC_DR register ********************/ 1334 #define ADC_DR_RDATA_Pos (0U) 1335 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ 1336 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ 1337 #define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ 1338 #define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ 1339 #define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ 1340 #define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ 1341 #define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ 1342 #define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ 1343 #define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ 1344 #define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ 1345 #define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ 1346 #define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ 1347 #define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ 1348 #define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ 1349 #define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ 1350 #define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ 1351 #define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ 1352 #define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ 1353 1354 /******************** Bit definition for ADC_JSQR register ******************/ 1355 #define ADC_JSQR_JL_Pos (0U) 1356 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ 1357 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1358 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ 1359 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ 1360 1361 #define ADC_JSQR_JEXTSEL_Pos (2U) 1362 #define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ 1363 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1364 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ 1365 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ 1366 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ 1367 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ 1368 1369 #define ADC_JSQR_JEXTEN_Pos (6U) 1370 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ 1371 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1372 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ 1373 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ 1374 1375 #define ADC_JSQR_JSQ1_Pos (8U) 1376 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ 1377 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1378 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ 1379 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ 1380 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ 1381 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ 1382 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ 1383 1384 #define ADC_JSQR_JSQ2_Pos (14U) 1385 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ 1386 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1387 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ 1388 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ 1389 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ 1390 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ 1391 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ 1392 1393 #define ADC_JSQR_JSQ3_Pos (20U) 1394 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ 1395 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1396 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ 1397 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ 1398 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ 1399 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ 1400 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ 1401 1402 #define ADC_JSQR_JSQ4_Pos (26U) 1403 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ 1404 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1405 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ 1406 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ 1407 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ 1408 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ 1409 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ 1410 1411 1412 /******************** Bit definition for ADC_OFR1 register ******************/ 1413 #define ADC_OFR1_OFFSET1_Pos (0U) 1414 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ 1415 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ 1416 #define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ 1417 #define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ 1418 #define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ 1419 #define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ 1420 #define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ 1421 #define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ 1422 #define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ 1423 #define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ 1424 #define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ 1425 #define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ 1426 #define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ 1427 #define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ 1428 1429 #define ADC_OFR1_OFFSET1_CH_Pos (26U) 1430 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ 1431 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ 1432 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ 1433 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ 1434 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ 1435 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ 1436 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ 1437 1438 #define ADC_OFR1_OFFSET1_EN_Pos (31U) 1439 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ 1440 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ 1441 1442 /******************** Bit definition for ADC_OFR2 register ******************/ 1443 #define ADC_OFR2_OFFSET2_Pos (0U) 1444 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ 1445 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ 1446 #define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ 1447 #define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ 1448 #define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ 1449 #define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ 1450 #define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ 1451 #define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ 1452 #define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ 1453 #define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ 1454 #define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ 1455 #define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ 1456 #define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ 1457 #define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ 1458 1459 #define ADC_OFR2_OFFSET2_CH_Pos (26U) 1460 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ 1461 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ 1462 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ 1463 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ 1464 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ 1465 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ 1466 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ 1467 1468 #define ADC_OFR2_OFFSET2_EN_Pos (31U) 1469 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ 1470 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ 1471 1472 /******************** Bit definition for ADC_OFR3 register ******************/ 1473 #define ADC_OFR3_OFFSET3_Pos (0U) 1474 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ 1475 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ 1476 #define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ 1477 #define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ 1478 #define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ 1479 #define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ 1480 #define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ 1481 #define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ 1482 #define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ 1483 #define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ 1484 #define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ 1485 #define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ 1486 #define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ 1487 #define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ 1488 1489 #define ADC_OFR3_OFFSET3_CH_Pos (26U) 1490 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ 1491 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ 1492 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ 1493 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ 1494 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ 1495 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ 1496 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ 1497 1498 #define ADC_OFR3_OFFSET3_EN_Pos (31U) 1499 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ 1500 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ 1501 1502 /******************** Bit definition for ADC_OFR4 register ******************/ 1503 #define ADC_OFR4_OFFSET4_Pos (0U) 1504 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ 1505 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ 1506 #define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ 1507 #define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ 1508 #define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ 1509 #define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ 1510 #define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ 1511 #define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ 1512 #define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ 1513 #define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ 1514 #define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ 1515 #define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ 1516 #define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ 1517 #define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ 1518 1519 #define ADC_OFR4_OFFSET4_CH_Pos (26U) 1520 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ 1521 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ 1522 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ 1523 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ 1524 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ 1525 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ 1526 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ 1527 1528 #define ADC_OFR4_OFFSET4_EN_Pos (31U) 1529 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ 1530 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ 1531 1532 /******************** Bit definition for ADC_JDR1 register ******************/ 1533 #define ADC_JDR1_JDATA_Pos (0U) 1534 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1535 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1536 #define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ 1537 #define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ 1538 #define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ 1539 #define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ 1540 #define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ 1541 #define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ 1542 #define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ 1543 #define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ 1544 #define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ 1545 #define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ 1546 #define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ 1547 #define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ 1548 #define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ 1549 #define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ 1550 #define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ 1551 #define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ 1552 1553 /******************** Bit definition for ADC_JDR2 register ******************/ 1554 #define ADC_JDR2_JDATA_Pos (0U) 1555 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1556 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1557 #define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ 1558 #define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ 1559 #define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ 1560 #define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ 1561 #define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ 1562 #define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ 1563 #define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ 1564 #define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ 1565 #define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ 1566 #define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ 1567 #define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ 1568 #define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ 1569 #define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ 1570 #define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ 1571 #define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ 1572 #define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ 1573 1574 /******************** Bit definition for ADC_JDR3 register ******************/ 1575 #define ADC_JDR3_JDATA_Pos (0U) 1576 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1577 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1578 #define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ 1579 #define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ 1580 #define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ 1581 #define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ 1582 #define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ 1583 #define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ 1584 #define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ 1585 #define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ 1586 #define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ 1587 #define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ 1588 #define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ 1589 #define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ 1590 #define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ 1591 #define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ 1592 #define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ 1593 #define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ 1594 1595 /******************** Bit definition for ADC_JDR4 register ******************/ 1596 #define ADC_JDR4_JDATA_Pos (0U) 1597 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1598 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1599 #define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ 1600 #define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ 1601 #define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ 1602 #define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ 1603 #define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ 1604 #define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ 1605 #define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ 1606 #define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ 1607 #define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ 1608 #define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ 1609 #define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ 1610 #define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ 1611 #define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ 1612 #define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ 1613 #define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ 1614 #define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ 1615 1616 /******************** Bit definition for ADC_AWD2CR register ****************/ 1617 #define ADC_AWD2CR_AWD2CH_Pos (1U) 1618 #define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ 1619 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1620 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1621 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1622 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1623 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1624 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 1625 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 1626 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 1627 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 1628 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 1629 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 1630 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 1631 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 1632 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 1633 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 1634 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 1635 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 1636 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 1637 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 1638 1639 /******************** Bit definition for ADC_AWD3CR register ****************/ 1640 #define ADC_AWD3CR_AWD3CH_Pos (1U) 1641 #define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ 1642 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 1643 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 1644 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 1645 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 1646 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 1647 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 1648 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 1649 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 1650 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 1651 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 1652 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 1653 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 1654 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 1655 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 1656 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 1657 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 1658 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 1659 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 1660 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 1661 1662 /******************** Bit definition for ADC_DIFSEL register ****************/ 1663 #define ADC_DIFSEL_DIFSEL_Pos (1U) 1664 #define ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0003FFFF */ 1665 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ 1666 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ 1667 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ 1668 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ 1669 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ 1670 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ 1671 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ 1672 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ 1673 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ 1674 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ 1675 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ 1676 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ 1677 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ 1678 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ 1679 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ 1680 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ 1681 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ 1682 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ 1683 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ 1684 1685 /******************** Bit definition for ADC_CALFACT register ***************/ 1686 #define ADC_CALFACT_CALFACT_S_Pos (0U) 1687 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ 1688 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ 1689 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ 1690 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ 1691 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ 1692 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ 1693 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ 1694 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ 1695 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ 1696 1697 #define ADC_CALFACT_CALFACT_D_Pos (16U) 1698 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ 1699 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ 1700 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ 1701 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ 1702 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ 1703 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ 1704 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ 1705 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ 1706 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ 1707 1708 /************************* ADC Common registers *****************************/ 1709 /*************** Bit definition for ADC1_COMMON_CSR register ***************/ 1710 #define ADC1_CSR_ADRDY_MST_Pos (0U) 1711 #define ADC1_CSR_ADRDY_MST_Msk (0x1UL << ADC1_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ 1712 #define ADC1_CSR_ADRDY_MST ADC1_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ 1713 #define ADC1_CSR_ADRDY_EOSMP_MST_Pos (1U) 1714 #define ADC1_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC1_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */ 1715 #define ADC1_CSR_ADRDY_EOSMP_MST ADC1_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ 1716 #define ADC1_CSR_ADRDY_EOC_MST_Pos (2U) 1717 #define ADC1_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC1_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */ 1718 #define ADC1_CSR_ADRDY_EOC_MST ADC1_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ 1719 #define ADC1_CSR_ADRDY_EOS_MST_Pos (3U) 1720 #define ADC1_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC1_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */ 1721 #define ADC1_CSR_ADRDY_EOS_MST ADC1_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ 1722 #define ADC1_CSR_ADRDY_OVR_MST_Pos (4U) 1723 #define ADC1_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC1_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */ 1724 #define ADC1_CSR_ADRDY_OVR_MST ADC1_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */ 1725 #define ADC1_CSR_ADRDY_JEOC_MST_Pos (5U) 1726 #define ADC1_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC1_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */ 1727 #define ADC1_CSR_ADRDY_JEOC_MST ADC1_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ 1728 #define ADC1_CSR_ADRDY_JEOS_MST_Pos (6U) 1729 #define ADC1_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC1_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */ 1730 #define ADC1_CSR_ADRDY_JEOS_MST ADC1_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ 1731 #define ADC1_CSR_AWD1_MST_Pos (7U) 1732 #define ADC1_CSR_AWD1_MST_Msk (0x1UL << ADC1_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ 1733 #define ADC1_CSR_AWD1_MST ADC1_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ 1734 #define ADC1_CSR_AWD2_MST_Pos (8U) 1735 #define ADC1_CSR_AWD2_MST_Msk (0x1UL << ADC1_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ 1736 #define ADC1_CSR_AWD2_MST ADC1_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ 1737 #define ADC1_CSR_AWD3_MST_Pos (9U) 1738 #define ADC1_CSR_AWD3_MST_Msk (0x1UL << ADC1_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ 1739 #define ADC1_CSR_AWD3_MST ADC1_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ 1740 #define ADC1_CSR_JQOVF_MST_Pos (10U) 1741 #define ADC1_CSR_JQOVF_MST_Msk (0x1UL << ADC1_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ 1742 #define ADC1_CSR_JQOVF_MST ADC1_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ 1743 #define ADC1_CSR_ADRDY_SLV_Pos (16U) 1744 #define ADC1_CSR_ADRDY_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ 1745 #define ADC1_CSR_ADRDY_SLV ADC1_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ 1746 #define ADC1_CSR_ADRDY_EOSMP_SLV_Pos (17U) 1747 #define ADC1_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */ 1748 #define ADC1_CSR_ADRDY_EOSMP_SLV ADC1_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ 1749 #define ADC1_CSR_ADRDY_EOC_SLV_Pos (18U) 1750 #define ADC1_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */ 1751 #define ADC1_CSR_ADRDY_EOC_SLV ADC1_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ 1752 #define ADC1_CSR_ADRDY_EOS_SLV_Pos (19U) 1753 #define ADC1_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */ 1754 #define ADC1_CSR_ADRDY_EOS_SLV ADC1_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ 1755 #define ADC1_CSR_ADRDY_OVR_SLV_Pos (20U) 1756 #define ADC1_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */ 1757 #define ADC1_CSR_ADRDY_OVR_SLV ADC1_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ 1758 #define ADC1_CSR_ADRDY_JEOC_SLV_Pos (21U) 1759 #define ADC1_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */ 1760 #define ADC1_CSR_ADRDY_JEOC_SLV ADC1_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ 1761 #define ADC1_CSR_ADRDY_JEOS_SLV_Pos (22U) 1762 #define ADC1_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC1_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */ 1763 #define ADC1_CSR_ADRDY_JEOS_SLV ADC1_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ 1764 #define ADC1_CSR_AWD1_SLV_Pos (23U) 1765 #define ADC1_CSR_AWD1_SLV_Msk (0x1UL << ADC1_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ 1766 #define ADC1_CSR_AWD1_SLV ADC1_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ 1767 #define ADC1_CSR_AWD2_SLV_Pos (24U) 1768 #define ADC1_CSR_AWD2_SLV_Msk (0x1UL << ADC1_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ 1769 #define ADC1_CSR_AWD2_SLV ADC1_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ 1770 #define ADC1_CSR_AWD3_SLV_Pos (25U) 1771 #define ADC1_CSR_AWD3_SLV_Msk (0x1UL << ADC1_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ 1772 #define ADC1_CSR_AWD3_SLV ADC1_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ 1773 #define ADC1_CSR_JQOVF_SLV_Pos (26U) 1774 #define ADC1_CSR_JQOVF_SLV_Msk (0x1UL << ADC1_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ 1775 #define ADC1_CSR_JQOVF_SLV ADC1_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ 1776 1777 /*************** Bit definition for ADC1_COMMON_CCR register ***************/ 1778 #define ADC1_CCR_MULTI_Pos (0U) 1779 #define ADC1_CCR_MULTI_Msk (0x1FUL << ADC1_CCR_MULTI_Pos) /*!< 0x0000001F */ 1780 #define ADC1_CCR_MULTI ADC1_CCR_MULTI_Msk /*!< Multi ADC mode selection */ 1781 #define ADC1_CCR_MULTI_0 (0x01UL << ADC1_CCR_MULTI_Pos) /*!< 0x00000001 */ 1782 #define ADC1_CCR_MULTI_1 (0x02UL << ADC1_CCR_MULTI_Pos) /*!< 0x00000002 */ 1783 #define ADC1_CCR_MULTI_2 (0x04UL << ADC1_CCR_MULTI_Pos) /*!< 0x00000004 */ 1784 #define ADC1_CCR_MULTI_3 (0x08UL << ADC1_CCR_MULTI_Pos) /*!< 0x00000008 */ 1785 #define ADC1_CCR_MULTI_4 (0x10UL << ADC1_CCR_MULTI_Pos) /*!< 0x00000010 */ 1786 #define ADC1_CCR_DELAY_Pos (8U) 1787 #define ADC1_CCR_DELAY_Msk (0xFUL << ADC1_CCR_DELAY_Pos) /*!< 0x00000F00 */ 1788 #define ADC1_CCR_DELAY ADC1_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ 1789 #define ADC1_CCR_DELAY_0 (0x1UL << ADC1_CCR_DELAY_Pos) /*!< 0x00000100 */ 1790 #define ADC1_CCR_DELAY_1 (0x2UL << ADC1_CCR_DELAY_Pos) /*!< 0x00000200 */ 1791 #define ADC1_CCR_DELAY_2 (0x4UL << ADC1_CCR_DELAY_Pos) /*!< 0x00000400 */ 1792 #define ADC1_CCR_DELAY_3 (0x8UL << ADC1_CCR_DELAY_Pos) /*!< 0x00000800 */ 1793 #define ADC1_CCR_DMACFG_Pos (13U) 1794 #define ADC1_CCR_DMACFG_Msk (0x1UL << ADC1_CCR_DMACFG_Pos) /*!< 0x00002000 */ 1795 #define ADC1_CCR_DMACFG ADC1_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */ 1796 #define ADC1_CCR_MDMA_Pos (14U) 1797 #define ADC1_CCR_MDMA_Msk (0x3UL << ADC1_CCR_MDMA_Pos) /*!< 0x0000C000 */ 1798 #define ADC1_CCR_MDMA ADC1_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */ 1799 #define ADC1_CCR_MDMA_0 (0x1UL << ADC1_CCR_MDMA_Pos) /*!< 0x00004000 */ 1800 #define ADC1_CCR_MDMA_1 (0x2UL << ADC1_CCR_MDMA_Pos) /*!< 0x00008000 */ 1801 #define ADC1_CCR_CKMODE_Pos (16U) 1802 #define ADC1_CCR_CKMODE_Msk (0x3UL << ADC1_CCR_CKMODE_Pos) /*!< 0x00030000 */ 1803 #define ADC1_CCR_CKMODE ADC1_CCR_CKMODE_Msk /*!< ADC clock mode */ 1804 #define ADC1_CCR_CKMODE_0 (0x1UL << ADC1_CCR_CKMODE_Pos) /*!< 0x00010000 */ 1805 #define ADC1_CCR_CKMODE_1 (0x2UL << ADC1_CCR_CKMODE_Pos) /*!< 0x00020000 */ 1806 #define ADC1_CCR_VREFEN_Pos (22U) 1807 #define ADC1_CCR_VREFEN_Msk (0x1UL << ADC1_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1808 #define ADC1_CCR_VREFEN ADC1_CCR_VREFEN_Msk /*!< VREFINT enable */ 1809 #define ADC1_CCR_TSEN_Pos (23U) 1810 #define ADC1_CCR_TSEN_Msk (0x1UL << ADC1_CCR_TSEN_Pos) /*!< 0x00800000 */ 1811 #define ADC1_CCR_TSEN ADC1_CCR_TSEN_Msk /*!< Temperature sensor enable */ 1812 #define ADC1_CCR_VBATEN_Pos (24U) 1813 #define ADC1_CCR_VBATEN_Msk (0x1UL << ADC1_CCR_VBATEN_Pos) /*!< 0x01000000 */ 1814 #define ADC1_CCR_VBATEN ADC1_CCR_VBATEN_Msk /*!< VBAT enable */ 1815 1816 /*************** Bit definition for ADC1_COMMON_CDR register ***************/ 1817 #define ADC1_CDR_RDATA_MST_Pos (0U) 1818 #define ADC1_CDR_RDATA_MST_Msk (0xFFFFUL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ 1819 #define ADC1_CDR_RDATA_MST ADC1_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */ 1820 #define ADC1_CDR_RDATA_MST_0 (0x0001UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ 1821 #define ADC1_CDR_RDATA_MST_1 (0x0002UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ 1822 #define ADC1_CDR_RDATA_MST_2 (0x0004UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ 1823 #define ADC1_CDR_RDATA_MST_3 (0x0008UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ 1824 #define ADC1_CDR_RDATA_MST_4 (0x0010UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ 1825 #define ADC1_CDR_RDATA_MST_5 (0x0020UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ 1826 #define ADC1_CDR_RDATA_MST_6 (0x0040UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ 1827 #define ADC1_CDR_RDATA_MST_7 (0x0080UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ 1828 #define ADC1_CDR_RDATA_MST_8 (0x0100UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ 1829 #define ADC1_CDR_RDATA_MST_9 (0x0200UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ 1830 #define ADC1_CDR_RDATA_MST_10 (0x0400UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ 1831 #define ADC1_CDR_RDATA_MST_11 (0x0800UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ 1832 #define ADC1_CDR_RDATA_MST_12 (0x1000UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ 1833 #define ADC1_CDR_RDATA_MST_13 (0x2000UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ 1834 #define ADC1_CDR_RDATA_MST_14 (0x4000UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ 1835 #define ADC1_CDR_RDATA_MST_15 (0x8000UL << ADC1_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ 1836 1837 #define ADC1_CDR_RDATA_SLV_Pos (16U) 1838 #define ADC1_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ 1839 #define ADC1_CDR_RDATA_SLV ADC1_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */ 1840 #define ADC1_CDR_RDATA_SLV_0 (0x0001UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ 1841 #define ADC1_CDR_RDATA_SLV_1 (0x0002UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ 1842 #define ADC1_CDR_RDATA_SLV_2 (0x0004UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ 1843 #define ADC1_CDR_RDATA_SLV_3 (0x0008UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ 1844 #define ADC1_CDR_RDATA_SLV_4 (0x0010UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ 1845 #define ADC1_CDR_RDATA_SLV_5 (0x0020UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ 1846 #define ADC1_CDR_RDATA_SLV_6 (0x0040UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ 1847 #define ADC1_CDR_RDATA_SLV_7 (0x0080UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ 1848 #define ADC1_CDR_RDATA_SLV_8 (0x0100UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ 1849 #define ADC1_CDR_RDATA_SLV_9 (0x0200UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ 1850 #define ADC1_CDR_RDATA_SLV_10 (0x0400UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ 1851 #define ADC1_CDR_RDATA_SLV_11 (0x0800UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ 1852 #define ADC1_CDR_RDATA_SLV_12 (0x1000UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ 1853 #define ADC1_CDR_RDATA_SLV_13 (0x2000UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ 1854 #define ADC1_CDR_RDATA_SLV_14 (0x4000UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ 1855 #define ADC1_CDR_RDATA_SLV_15 (0x8000UL << ADC1_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ 1856 1857 /******************** Bit definition for ADC_CSR register *******************/ 1858 #define ADC_CSR_ADRDY_MST_Pos (0U) 1859 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ 1860 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ 1861 #define ADC_CSR_EOSMP_MST_Pos (1U) 1862 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ 1863 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ 1864 #define ADC_CSR_EOC_MST_Pos (2U) 1865 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ 1866 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ 1867 #define ADC_CSR_EOS_MST_Pos (3U) 1868 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ 1869 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ 1870 #define ADC_CSR_OVR_MST_Pos (4U) 1871 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ 1872 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ 1873 #define ADC_CSR_JEOC_MST_Pos (5U) 1874 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ 1875 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ 1876 #define ADC_CSR_JEOS_MST_Pos (6U) 1877 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ 1878 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 1879 #define ADC_CSR_AWD1_MST_Pos (7U) 1880 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ 1881 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ 1882 #define ADC_CSR_AWD2_MST_Pos (8U) 1883 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ 1884 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ 1885 #define ADC_CSR_AWD3_MST_Pos (9U) 1886 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ 1887 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ 1888 #define ADC_CSR_JQOVF_MST_Pos (10U) 1889 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ 1890 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ 1891 1892 #define ADC_CSR_ADRDY_SLV_Pos (16U) 1893 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ 1894 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ 1895 #define ADC_CSR_EOSMP_SLV_Pos (17U) 1896 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ 1897 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ 1898 #define ADC_CSR_EOC_SLV_Pos (18U) 1899 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ 1900 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ 1901 #define ADC_CSR_EOS_SLV_Pos (19U) 1902 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ 1903 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ 1904 #define ADC_CSR_OVR_SLV_Pos (20U) 1905 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ 1906 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ 1907 #define ADC_CSR_JEOC_SLV_Pos (21U) 1908 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ 1909 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ 1910 #define ADC_CSR_JEOS_SLV_Pos (22U) 1911 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ 1912 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ 1913 #define ADC_CSR_AWD1_SLV_Pos (23U) 1914 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ 1915 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ 1916 #define ADC_CSR_AWD2_SLV_Pos (24U) 1917 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ 1918 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ 1919 #define ADC_CSR_AWD3_SLV_Pos (25U) 1920 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ 1921 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ 1922 #define ADC_CSR_JQOVF_SLV_Pos (26U) 1923 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ 1924 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ 1925 1926 /* Legacy defines */ 1927 #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST 1928 #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST 1929 #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST 1930 #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST 1931 #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST 1932 #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST 1933 1934 #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV 1935 #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV 1936 #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV 1937 #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV 1938 #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV 1939 #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV 1940 1941 /******************** Bit definition for ADC_CCR register *******************/ 1942 #define ADC_CCR_DUAL_Pos (0U) 1943 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ 1944 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ 1945 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ 1946 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ 1947 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ 1948 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ 1949 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ 1950 1951 #define ADC_CCR_DELAY_Pos (8U) 1952 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ 1953 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ 1954 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ 1955 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ 1956 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ 1957 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ 1958 1959 #define ADC_CCR_DMACFG_Pos (13U) 1960 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ 1961 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ 1962 1963 #define ADC_CCR_MDMA_Pos (14U) 1964 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ 1965 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ 1966 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ 1967 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ 1968 1969 #define ADC_CCR_CKMODE_Pos (16U) 1970 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ 1971 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ 1972 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ 1973 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ 1974 1975 #define ADC_CCR_VREFEN_Pos (22U) 1976 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1977 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 1978 #define ADC_CCR_TSEN_Pos (23U) 1979 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 1980 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 1981 #define ADC_CCR_VBATEN_Pos (24U) 1982 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 1983 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 1984 1985 /* Legacy defines */ 1986 #define ADC_CCR_MULTI (ADC_CCR_DUAL) 1987 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) 1988 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) 1989 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) 1990 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) 1991 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) 1992 1993 /******************** Bit definition for ADC_CDR register *******************/ 1994 #define ADC_CDR_RDATA_MST_Pos (0U) 1995 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ 1996 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ 1997 #define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ 1998 #define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ 1999 #define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ 2000 #define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ 2001 #define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ 2002 #define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ 2003 #define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ 2004 #define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ 2005 #define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ 2006 #define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ 2007 #define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ 2008 #define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ 2009 #define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ 2010 #define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ 2011 #define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ 2012 #define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ 2013 2014 #define ADC_CDR_RDATA_SLV_Pos (16U) 2015 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ 2016 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ 2017 #define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ 2018 #define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ 2019 #define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ 2020 #define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ 2021 #define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ 2022 #define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ 2023 #define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ 2024 #define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ 2025 #define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ 2026 #define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ 2027 #define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ 2028 #define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ 2029 #define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ 2030 #define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ 2031 #define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ 2032 #define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ 2033 2034 /******************************************************************************/ 2035 /* */ 2036 /* Analog Comparators (COMP) */ 2037 /* */ 2038 /******************************************************************************/ 2039 2040 #define COMP_V1_3_0_0 /*!< Comparator IP version */ 2041 2042 /********************** Bit definition for COMP2_CSR register ***************/ 2043 #define COMP2_CSR_COMP2EN_Pos (0U) 2044 #define COMP2_CSR_COMP2EN_Msk (0x1UL << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */ 2045 #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */ 2046 #define COMP2_CSR_COMP2SW1_Pos (1U) 2047 #define COMP2_CSR_COMP2SW1_Msk (0x1UL << COMP2_CSR_COMP2SW1_Pos) /*!< 0x00000002 */ 2048 #define COMP2_CSR_COMP2SW1 COMP2_CSR_COMP2SW1_Msk /*!< COMP2 SW1 switch control */ 2049 /* Legacy defines */ 2050 #define COMP_CSR_COMP2SW1 COMP2_CSR_COMP2SW1 2051 #define COMP2_CSR_COMP2INPDAC_Pos (1U) 2052 #define COMP2_CSR_COMP2INPDAC_Msk (0x1UL << COMP2_CSR_COMP2INPDAC_Pos) /*!< 0x00000002 */ 2053 #define COMP2_CSR_COMP2INPDAC COMP2_CSR_COMP2INPDAC_Msk /*!< COMP2 non inverting input to DAC output */ 2054 #define COMP2_CSR_COMP2INSEL_Pos (4U) 2055 #define COMP2_CSR_COMP2INSEL_Msk (0x7UL << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */ 2056 #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */ 2057 #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */ 2058 #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */ 2059 #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */ 2060 #define COMP2_CSR_COMP2OUTSEL_Pos (10U) 2061 #define COMP2_CSR_COMP2OUTSEL_Msk (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */ 2062 #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */ 2063 #define COMP2_CSR_COMP2OUTSEL_0 (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */ 2064 #define COMP2_CSR_COMP2OUTSEL_1 (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */ 2065 #define COMP2_CSR_COMP2OUTSEL_2 (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */ 2066 #define COMP2_CSR_COMP2OUTSEL_3 (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */ 2067 #define COMP2_CSR_COMP2POL_Pos (15U) 2068 #define COMP2_CSR_COMP2POL_Msk (0x1UL << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */ 2069 #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */ 2070 #define COMP2_CSR_COMP2BLANKING_Pos (18U) 2071 #define COMP2_CSR_COMP2BLANKING_Msk (0x3UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */ 2072 #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */ 2073 #define COMP2_CSR_COMP2BLANKING_0 (0x1UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */ 2074 #define COMP2_CSR_COMP2BLANKING_1 (0x2UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */ 2075 #define COMP2_CSR_COMP2BLANKING_2 (0x4UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */ 2076 #define COMP2_CSR_COMP2OUT_Pos (30U) 2077 #define COMP2_CSR_COMP2OUT_Msk (0x1UL << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */ 2078 #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */ 2079 #define COMP2_CSR_COMP2LOCK_Pos (31U) 2080 #define COMP2_CSR_COMP2LOCK_Msk (0x1UL << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ 2081 #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ 2082 2083 /********************** Bit definition for COMP4_CSR register ***************/ 2084 #define COMP4_CSR_COMP4EN_Pos (0U) 2085 #define COMP4_CSR_COMP4EN_Msk (0x1UL << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */ 2086 #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */ 2087 #define COMP4_CSR_COMP4INSEL_Pos (4U) 2088 #define COMP4_CSR_COMP4INSEL_Msk (0x7UL << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */ 2089 #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */ 2090 #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */ 2091 #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */ 2092 #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */ 2093 #define COMP4_CSR_COMP4OUTSEL_Pos (10U) 2094 #define COMP4_CSR_COMP4OUTSEL_Msk (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */ 2095 #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */ 2096 #define COMP4_CSR_COMP4OUTSEL_0 (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */ 2097 #define COMP4_CSR_COMP4OUTSEL_1 (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */ 2098 #define COMP4_CSR_COMP4OUTSEL_2 (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */ 2099 #define COMP4_CSR_COMP4OUTSEL_3 (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */ 2100 #define COMP4_CSR_COMP4POL_Pos (15U) 2101 #define COMP4_CSR_COMP4POL_Msk (0x1UL << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */ 2102 #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */ 2103 #define COMP4_CSR_COMP4BLANKING_Pos (18U) 2104 #define COMP4_CSR_COMP4BLANKING_Msk (0x3UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */ 2105 #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */ 2106 #define COMP4_CSR_COMP4BLANKING_0 (0x1UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */ 2107 #define COMP4_CSR_COMP4BLANKING_1 (0x2UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */ 2108 #define COMP4_CSR_COMP4BLANKING_2 (0x4UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */ 2109 #define COMP4_CSR_COMP4OUT_Pos (30U) 2110 #define COMP4_CSR_COMP4OUT_Msk (0x1UL << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */ 2111 #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */ 2112 #define COMP4_CSR_COMP4LOCK_Pos (31U) 2113 #define COMP4_CSR_COMP4LOCK_Msk (0x1UL << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */ 2114 #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */ 2115 2116 /********************** Bit definition for COMP6_CSR register ***************/ 2117 #define COMP6_CSR_COMP6EN_Pos (0U) 2118 #define COMP6_CSR_COMP6EN_Msk (0x1UL << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */ 2119 #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */ 2120 #define COMP6_CSR_COMP6INSEL_Pos (4U) 2121 #define COMP6_CSR_COMP6INSEL_Msk (0x7UL << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */ 2122 #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */ 2123 #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */ 2124 #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */ 2125 #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */ 2126 #define COMP6_CSR_COMP6OUTSEL_Pos (10U) 2127 #define COMP6_CSR_COMP6OUTSEL_Msk (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */ 2128 #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */ 2129 #define COMP6_CSR_COMP6OUTSEL_0 (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */ 2130 #define COMP6_CSR_COMP6OUTSEL_1 (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */ 2131 #define COMP6_CSR_COMP6OUTSEL_2 (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */ 2132 #define COMP6_CSR_COMP6OUTSEL_3 (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */ 2133 #define COMP6_CSR_COMP6POL_Pos (15U) 2134 #define COMP6_CSR_COMP6POL_Msk (0x1UL << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */ 2135 #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */ 2136 #define COMP6_CSR_COMP6BLANKING_Pos (18U) 2137 #define COMP6_CSR_COMP6BLANKING_Msk (0x3UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */ 2138 #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */ 2139 #define COMP6_CSR_COMP6BLANKING_0 (0x1UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */ 2140 #define COMP6_CSR_COMP6BLANKING_1 (0x2UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */ 2141 #define COMP6_CSR_COMP6BLANKING_2 (0x4UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */ 2142 #define COMP6_CSR_COMP6OUT_Pos (30U) 2143 #define COMP6_CSR_COMP6OUT_Msk (0x1UL << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */ 2144 #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */ 2145 #define COMP6_CSR_COMP6LOCK_Pos (31U) 2146 #define COMP6_CSR_COMP6LOCK_Msk (0x1UL << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */ 2147 #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */ 2148 2149 /********************** Bit definition for COMP_CSR register ****************/ 2150 #define COMP_CSR_COMPxEN_Pos (0U) 2151 #define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ 2152 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ 2153 #define COMP_CSR_COMPxSW1_Pos (1U) 2154 #define COMP_CSR_COMPxSW1_Msk (0x1UL << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */ 2155 #define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */ 2156 #define COMP_CSR_COMPxINSEL_Pos (4U) 2157 #define COMP_CSR_COMPxINSEL_Msk (0x7UL << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */ 2158 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */ 2159 #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */ 2160 #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */ 2161 #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */ 2162 #define COMP_CSR_COMPxOUTSEL_Pos (10U) 2163 #define COMP_CSR_COMPxOUTSEL_Msk (0xFUL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */ 2164 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */ 2165 #define COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */ 2166 #define COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */ 2167 #define COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */ 2168 #define COMP_CSR_COMPxOUTSEL_3 (0x8UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */ 2169 #define COMP_CSR_COMPxPOL_Pos (15U) 2170 #define COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */ 2171 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */ 2172 #define COMP_CSR_COMPxBLANKING_Pos (18U) 2173 #define COMP_CSR_COMPxBLANKING_Msk (0x3UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */ 2174 #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */ 2175 #define COMP_CSR_COMPxBLANKING_0 (0x1UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */ 2176 #define COMP_CSR_COMPxBLANKING_1 (0x2UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */ 2177 #define COMP_CSR_COMPxBLANKING_2 (0x4UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */ 2178 #define COMP_CSR_COMPxOUT_Pos (30U) 2179 #define COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */ 2180 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */ 2181 #define COMP_CSR_COMPxLOCK_Pos (31U) 2182 #define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ 2183 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ 2184 2185 /******************************************************************************/ 2186 /* */ 2187 /* Operational Amplifier (OPAMP) */ 2188 /* */ 2189 /******************************************************************************/ 2190 /********************* Bit definition for OPAMP2_CSR register ***************/ 2191 #define OPAMP2_CSR_OPAMP2EN_Pos (0U) 2192 #define OPAMP2_CSR_OPAMP2EN_Msk (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */ 2193 #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */ 2194 #define OPAMP2_CSR_FORCEVP_Pos (1U) 2195 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */ 2196 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ 2197 #define OPAMP2_CSR_VPSEL_Pos (2U) 2198 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */ 2199 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */ 2200 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */ 2201 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */ 2202 #define OPAMP2_CSR_VMSEL_Pos (5U) 2203 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */ 2204 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */ 2205 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */ 2206 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */ 2207 #define OPAMP2_CSR_TCMEN_Pos (7U) 2208 #define OPAMP2_CSR_TCMEN_Msk (0x1UL << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */ 2209 #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ 2210 #define OPAMP2_CSR_VMSSEL_Pos (8U) 2211 #define OPAMP2_CSR_VMSSEL_Msk (0x1UL << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */ 2212 #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ 2213 #define OPAMP2_CSR_VPSSEL_Pos (9U) 2214 #define OPAMP2_CSR_VPSSEL_Msk (0x3UL << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */ 2215 #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ 2216 #define OPAMP2_CSR_VPSSEL_0 (0x1UL << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */ 2217 #define OPAMP2_CSR_VPSSEL_1 (0x2UL << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */ 2218 #define OPAMP2_CSR_CALON_Pos (11U) 2219 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */ 2220 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */ 2221 #define OPAMP2_CSR_CALSEL_Pos (12U) 2222 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */ 2223 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */ 2224 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */ 2225 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */ 2226 #define OPAMP2_CSR_PGGAIN_Pos (14U) 2227 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ 2228 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ 2229 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */ 2230 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */ 2231 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */ 2232 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */ 2233 #define OPAMP2_CSR_USERTRIM_Pos (18U) 2234 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */ 2235 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */ 2236 #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U) 2237 #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ 2238 #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ 2239 #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U) 2240 #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ 2241 #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ 2242 #define OPAMP2_CSR_TSTREF_Pos (29U) 2243 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */ 2244 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ 2245 #define OPAMP2_CSR_OUTCAL_Pos (30U) 2246 #define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */ 2247 #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ 2248 #define OPAMP2_CSR_LOCK_Pos (31U) 2249 #define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */ 2250 #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */ 2251 2252 /********************* Bit definition for OPAMPx_CSR register ***************/ 2253 #define OPAMP_CSR_OPAMPxEN_Pos (0U) 2254 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ 2255 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ 2256 #define OPAMP_CSR_FORCEVP_Pos (1U) 2257 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */ 2258 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ 2259 #define OPAMP_CSR_VPSEL_Pos (2U) 2260 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */ 2261 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */ 2262 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */ 2263 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */ 2264 #define OPAMP_CSR_VMSEL_Pos (5U) 2265 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */ 2266 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ 2267 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */ 2268 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */ 2269 #define OPAMP_CSR_TCMEN_Pos (7U) 2270 #define OPAMP_CSR_TCMEN_Msk (0x1UL << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */ 2271 #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ 2272 #define OPAMP_CSR_VMSSEL_Pos (8U) 2273 #define OPAMP_CSR_VMSSEL_Msk (0x1UL << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */ 2274 #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ 2275 #define OPAMP_CSR_VPSSEL_Pos (9U) 2276 #define OPAMP_CSR_VPSSEL_Msk (0x3UL << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */ 2277 #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ 2278 #define OPAMP_CSR_VPSSEL_0 (0x1UL << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */ 2279 #define OPAMP_CSR_VPSSEL_1 (0x2UL << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */ 2280 #define OPAMP_CSR_CALON_Pos (11U) 2281 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ 2282 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ 2283 #define OPAMP_CSR_CALSEL_Pos (12U) 2284 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ 2285 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ 2286 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ 2287 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ 2288 #define OPAMP_CSR_PGGAIN_Pos (14U) 2289 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ 2290 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ 2291 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */ 2292 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */ 2293 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */ 2294 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */ 2295 #define OPAMP_CSR_USERTRIM_Pos (18U) 2296 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */ 2297 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ 2298 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U) 2299 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ 2300 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ 2301 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U) 2302 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ 2303 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ 2304 #define OPAMP_CSR_TSTREF_Pos (29U) 2305 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */ 2306 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ 2307 #define OPAMP_CSR_OUTCAL_Pos (30U) 2308 #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ 2309 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ 2310 #define OPAMP_CSR_LOCK_Pos (31U) 2311 #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ 2312 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */ 2313 2314 /******************************************************************************/ 2315 /* */ 2316 /* CRC calculation unit (CRC) */ 2317 /* */ 2318 /******************************************************************************/ 2319 /******************* Bit definition for CRC_DR register *********************/ 2320 #define CRC_DR_DR_Pos (0U) 2321 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 2322 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 2323 2324 /******************* Bit definition for CRC_IDR register ********************/ 2325 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 2326 2327 /******************** Bit definition for CRC_CR register ********************/ 2328 #define CRC_CR_RESET_Pos (0U) 2329 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 2330 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 2331 #define CRC_CR_POLYSIZE_Pos (3U) 2332 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 2333 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 2334 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 2335 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 2336 #define CRC_CR_REV_IN_Pos (5U) 2337 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 2338 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 2339 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 2340 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 2341 #define CRC_CR_REV_OUT_Pos (7U) 2342 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 2343 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 2344 2345 /******************* Bit definition for CRC_INIT register *******************/ 2346 #define CRC_INIT_INIT_Pos (0U) 2347 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 2348 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 2349 2350 /******************* Bit definition for CRC_POL register ********************/ 2351 #define CRC_POL_POL_Pos (0U) 2352 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 2353 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 2354 2355 /******************************************************************************/ 2356 /* */ 2357 /* Digital to Analog Converter (DAC) */ 2358 /* */ 2359 /******************************************************************************/ 2360 2361 /* 2362 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 2363 */ 2364 /* Note: No specific macro feature on this device */ 2365 2366 2367 /******************** Bit definition for DAC_CR register ********************/ 2368 #define DAC_CR_EN1_Pos (0U) 2369 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 2370 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ 2371 #define DAC_CR_BOFF1_Pos (1U) 2372 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 2373 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ 2374 #define DAC_CR_TEN1_Pos (2U) 2375 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 2376 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ 2377 2378 #define DAC_CR_TSEL1_Pos (3U) 2379 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 2380 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 2381 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 2382 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 2383 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 2384 2385 #define DAC_CR_WAVE1_Pos (6U) 2386 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 2387 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 2388 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 2389 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 2390 2391 #define DAC_CR_MAMP1_Pos (8U) 2392 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 2393 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 2394 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 2395 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 2396 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 2397 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 2398 2399 #define DAC_CR_DMAEN1_Pos (12U) 2400 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 2401 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ 2402 #define DAC_CR_DMAUDRIE1_Pos (13U) 2403 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 2404 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */ 2405 /***************** Bit definition for DAC_SWTRIGR register ******************/ 2406 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 2407 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 2408 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ 2409 2410 /***************** Bit definition for DAC_DHR12R1 register ******************/ 2411 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 2412 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 2413 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 2414 2415 /***************** Bit definition for DAC_DHR12L1 register ******************/ 2416 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 2417 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2418 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 2419 2420 /****************** Bit definition for DAC_DHR8R1 register ******************/ 2421 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 2422 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 2423 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 2424 2425 /***************** Bit definition for DAC_DHR12RD register ******************/ 2426 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 2427 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 2428 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 2429 2430 /***************** Bit definition for DAC_DHR12LD register ******************/ 2431 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 2432 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2433 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 2434 2435 /****************** Bit definition for DAC_DHR8RD register ******************/ 2436 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 2437 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 2438 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 2439 2440 /******************* Bit definition for DAC_DOR1 register *******************/ 2441 #define DAC_DOR1_DACC1DOR_Pos (0U) 2442 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 2443 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ 2444 2445 /******************** Bit definition for DAC_SR register ********************/ 2446 #define DAC_SR_DMAUDR1_Pos (13U) 2447 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 2448 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ 2449 2450 /******************************************************************************/ 2451 /* */ 2452 /* Debug MCU (DBGMCU) */ 2453 /* */ 2454 /******************************************************************************/ 2455 /******************** Bit definition for DBGMCU_IDCODE register *************/ 2456 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 2457 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 2458 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 2459 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 2460 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 2461 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 2462 2463 /******************** Bit definition for DBGMCU_CR register *****************/ 2464 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 2465 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 2466 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 2467 #define DBGMCU_CR_DBG_STOP_Pos (1U) 2468 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 2469 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 2470 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 2471 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 2472 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 2473 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 2474 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 2475 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 2476 2477 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 2478 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 2479 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk 2480 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 2481 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 2482 2483 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 2484 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 2485 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 2486 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 2487 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 2488 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 2489 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 2490 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 2491 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 2492 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 2493 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 2494 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 2495 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 2496 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 2497 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 2498 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 2499 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 2500 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 2501 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 2502 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 2503 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ 2504 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 2505 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (30U) 2506 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x40000000 */ 2507 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 2508 2509 /******************** Bit definition for DBGMCU_APB2_FZ register ************/ 2510 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) 2511 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ 2512 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 2513 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U) 2514 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */ 2515 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk 2516 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U) 2517 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */ 2518 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk 2519 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U) 2520 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */ 2521 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk 2522 2523 /******************************************************************************/ 2524 /* */ 2525 /* DMA Controller (DMA) */ 2526 /* */ 2527 /******************************************************************************/ 2528 /******************* Bit definition for DMA_ISR register ********************/ 2529 #define DMA_ISR_GIF1_Pos (0U) 2530 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2531 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2532 #define DMA_ISR_TCIF1_Pos (1U) 2533 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2534 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2535 #define DMA_ISR_HTIF1_Pos (2U) 2536 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2537 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2538 #define DMA_ISR_TEIF1_Pos (3U) 2539 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2540 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2541 #define DMA_ISR_GIF2_Pos (4U) 2542 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2543 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2544 #define DMA_ISR_TCIF2_Pos (5U) 2545 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2546 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2547 #define DMA_ISR_HTIF2_Pos (6U) 2548 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2549 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2550 #define DMA_ISR_TEIF2_Pos (7U) 2551 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2552 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2553 #define DMA_ISR_GIF3_Pos (8U) 2554 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2555 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2556 #define DMA_ISR_TCIF3_Pos (9U) 2557 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2558 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2559 #define DMA_ISR_HTIF3_Pos (10U) 2560 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2561 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2562 #define DMA_ISR_TEIF3_Pos (11U) 2563 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2564 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2565 #define DMA_ISR_GIF4_Pos (12U) 2566 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2567 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2568 #define DMA_ISR_TCIF4_Pos (13U) 2569 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2570 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2571 #define DMA_ISR_HTIF4_Pos (14U) 2572 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2573 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2574 #define DMA_ISR_TEIF4_Pos (15U) 2575 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2576 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2577 #define DMA_ISR_GIF5_Pos (16U) 2578 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2579 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2580 #define DMA_ISR_TCIF5_Pos (17U) 2581 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2582 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2583 #define DMA_ISR_HTIF5_Pos (18U) 2584 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2585 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2586 #define DMA_ISR_TEIF5_Pos (19U) 2587 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2588 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2589 #define DMA_ISR_GIF6_Pos (20U) 2590 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2591 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2592 #define DMA_ISR_TCIF6_Pos (21U) 2593 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2594 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2595 #define DMA_ISR_HTIF6_Pos (22U) 2596 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2597 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2598 #define DMA_ISR_TEIF6_Pos (23U) 2599 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2600 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2601 #define DMA_ISR_GIF7_Pos (24U) 2602 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2603 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2604 #define DMA_ISR_TCIF7_Pos (25U) 2605 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2606 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2607 #define DMA_ISR_HTIF7_Pos (26U) 2608 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2609 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2610 #define DMA_ISR_TEIF7_Pos (27U) 2611 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2612 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2613 2614 /******************* Bit definition for DMA_IFCR register *******************/ 2615 #define DMA_IFCR_CGIF1_Pos (0U) 2616 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2617 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2618 #define DMA_IFCR_CTCIF1_Pos (1U) 2619 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2620 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2621 #define DMA_IFCR_CHTIF1_Pos (2U) 2622 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2623 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2624 #define DMA_IFCR_CTEIF1_Pos (3U) 2625 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2626 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2627 #define DMA_IFCR_CGIF2_Pos (4U) 2628 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2629 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2630 #define DMA_IFCR_CTCIF2_Pos (5U) 2631 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2632 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2633 #define DMA_IFCR_CHTIF2_Pos (6U) 2634 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2635 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2636 #define DMA_IFCR_CTEIF2_Pos (7U) 2637 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2638 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2639 #define DMA_IFCR_CGIF3_Pos (8U) 2640 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2641 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2642 #define DMA_IFCR_CTCIF3_Pos (9U) 2643 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2644 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2645 #define DMA_IFCR_CHTIF3_Pos (10U) 2646 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2647 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2648 #define DMA_IFCR_CTEIF3_Pos (11U) 2649 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2650 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2651 #define DMA_IFCR_CGIF4_Pos (12U) 2652 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2653 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2654 #define DMA_IFCR_CTCIF4_Pos (13U) 2655 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2656 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2657 #define DMA_IFCR_CHTIF4_Pos (14U) 2658 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2659 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2660 #define DMA_IFCR_CTEIF4_Pos (15U) 2661 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2662 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2663 #define DMA_IFCR_CGIF5_Pos (16U) 2664 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2665 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2666 #define DMA_IFCR_CTCIF5_Pos (17U) 2667 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2668 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2669 #define DMA_IFCR_CHTIF5_Pos (18U) 2670 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2671 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2672 #define DMA_IFCR_CTEIF5_Pos (19U) 2673 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2674 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2675 #define DMA_IFCR_CGIF6_Pos (20U) 2676 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2677 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2678 #define DMA_IFCR_CTCIF6_Pos (21U) 2679 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2680 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2681 #define DMA_IFCR_CHTIF6_Pos (22U) 2682 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2683 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2684 #define DMA_IFCR_CTEIF6_Pos (23U) 2685 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2686 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2687 #define DMA_IFCR_CGIF7_Pos (24U) 2688 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2689 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2690 #define DMA_IFCR_CTCIF7_Pos (25U) 2691 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2692 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2693 #define DMA_IFCR_CHTIF7_Pos (26U) 2694 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2695 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2696 #define DMA_IFCR_CTEIF7_Pos (27U) 2697 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2698 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2699 2700 /******************* Bit definition for DMA_CCR register ********************/ 2701 #define DMA_CCR_EN_Pos (0U) 2702 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2703 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 2704 #define DMA_CCR_TCIE_Pos (1U) 2705 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2706 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2707 #define DMA_CCR_HTIE_Pos (2U) 2708 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2709 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2710 #define DMA_CCR_TEIE_Pos (3U) 2711 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2712 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2713 #define DMA_CCR_DIR_Pos (4U) 2714 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2715 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2716 #define DMA_CCR_CIRC_Pos (5U) 2717 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2718 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2719 #define DMA_CCR_PINC_Pos (6U) 2720 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2721 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2722 #define DMA_CCR_MINC_Pos (7U) 2723 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2724 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2725 2726 #define DMA_CCR_PSIZE_Pos (8U) 2727 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2728 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2729 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2730 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2731 2732 #define DMA_CCR_MSIZE_Pos (10U) 2733 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2734 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2735 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2736 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2737 2738 #define DMA_CCR_PL_Pos (12U) 2739 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2740 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 2741 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2742 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2743 2744 #define DMA_CCR_MEM2MEM_Pos (14U) 2745 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2746 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2747 2748 /****************** Bit definition for DMA_CNDTR register *******************/ 2749 #define DMA_CNDTR_NDT_Pos (0U) 2750 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 2751 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2752 2753 /****************** Bit definition for DMA_CPAR register ********************/ 2754 #define DMA_CPAR_PA_Pos (0U) 2755 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2756 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2757 2758 /****************** Bit definition for DMA_CMAR register ********************/ 2759 #define DMA_CMAR_MA_Pos (0U) 2760 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2761 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2762 2763 /******************************************************************************/ 2764 /* */ 2765 /* External Interrupt/Event Controller (EXTI) */ 2766 /* */ 2767 /******************************************************************************/ 2768 /******************* Bit definition for EXTI_IMR register *******************/ 2769 #define EXTI_IMR_MR0_Pos (0U) 2770 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2771 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2772 #define EXTI_IMR_MR1_Pos (1U) 2773 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2774 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2775 #define EXTI_IMR_MR2_Pos (2U) 2776 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2777 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2778 #define EXTI_IMR_MR3_Pos (3U) 2779 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2780 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2781 #define EXTI_IMR_MR4_Pos (4U) 2782 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2783 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2784 #define EXTI_IMR_MR5_Pos (5U) 2785 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2786 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2787 #define EXTI_IMR_MR6_Pos (6U) 2788 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2789 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2790 #define EXTI_IMR_MR7_Pos (7U) 2791 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2792 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2793 #define EXTI_IMR_MR8_Pos (8U) 2794 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2795 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2796 #define EXTI_IMR_MR9_Pos (9U) 2797 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2798 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2799 #define EXTI_IMR_MR10_Pos (10U) 2800 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2801 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2802 #define EXTI_IMR_MR11_Pos (11U) 2803 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2804 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2805 #define EXTI_IMR_MR12_Pos (12U) 2806 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2807 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2808 #define EXTI_IMR_MR13_Pos (13U) 2809 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2810 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2811 #define EXTI_IMR_MR14_Pos (14U) 2812 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2813 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2814 #define EXTI_IMR_MR15_Pos (15U) 2815 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2816 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2817 #define EXTI_IMR_MR16_Pos (16U) 2818 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2819 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2820 #define EXTI_IMR_MR17_Pos (17U) 2821 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2822 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2823 #define EXTI_IMR_MR19_Pos (19U) 2824 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 2825 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 2826 #define EXTI_IMR_MR20_Pos (20U) 2827 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 2828 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 2829 #define EXTI_IMR_MR22_Pos (22U) 2830 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 2831 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 2832 #define EXTI_IMR_MR23_Pos (23U) 2833 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 2834 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 2835 #define EXTI_IMR_MR24_Pos (24U) 2836 #define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */ 2837 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */ 2838 #define EXTI_IMR_MR25_Pos (25U) 2839 #define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ 2840 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ 2841 #define EXTI_IMR_MR27_Pos (27U) 2842 #define EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ 2843 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ 2844 #define EXTI_IMR_MR30_Pos (30U) 2845 #define EXTI_IMR_MR30_Msk (0x1UL << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */ 2846 #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */ 2847 2848 /* References Defines */ 2849 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2850 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2851 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2852 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2853 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2854 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2855 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2856 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2857 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2858 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2859 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2860 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2861 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2862 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2863 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2864 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2865 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2866 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2867 #if defined(EXTI_IMR_MR18) 2868 #define EXTI_IMR_IM18 EXTI_IMR_MR18 2869 #endif 2870 #define EXTI_IMR_IM19 EXTI_IMR_MR19 2871 #define EXTI_IMR_IM20 EXTI_IMR_MR20 2872 #if defined(EXTI_IMR_MR21) 2873 #define EXTI_IMR_IM21 EXTI_IMR_MR21 2874 #endif 2875 #define EXTI_IMR_IM22 EXTI_IMR_MR22 2876 #define EXTI_IMR_IM23 EXTI_IMR_MR23 2877 #if defined(EXTI_IMR_MR24) 2878 #define EXTI_IMR_IM24 EXTI_IMR_MR24 2879 #endif 2880 #define EXTI_IMR_IM25 EXTI_IMR_MR25 2881 #if defined(EXTI_IMR_MR26) 2882 #define EXTI_IMR_IM26 EXTI_IMR_MR26 2883 #endif 2884 #if defined(EXTI_IMR_MR27) 2885 #define EXTI_IMR_IM27 EXTI_IMR_MR27 2886 #endif 2887 #if defined(EXTI_IMR_MR28) 2888 #define EXTI_IMR_IM28 EXTI_IMR_MR28 2889 #endif 2890 #if defined(EXTI_IMR_MR29) 2891 #define EXTI_IMR_IM29 EXTI_IMR_MR29 2892 #endif 2893 #if defined(EXTI_IMR_MR30) 2894 #define EXTI_IMR_IM30 EXTI_IMR_MR30 2895 #endif 2896 #if defined(EXTI_IMR_MR31) 2897 #define EXTI_IMR_IM31 EXTI_IMR_MR31 2898 #endif 2899 2900 #define EXTI_IMR_IM_Pos (0U) 2901 #define EXTI_IMR_IM_Msk (0xFFFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */ 2902 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 2903 2904 /******************* Bit definition for EXTI_EMR register *******************/ 2905 #define EXTI_EMR_MR0_Pos (0U) 2906 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2907 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2908 #define EXTI_EMR_MR1_Pos (1U) 2909 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2910 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2911 #define EXTI_EMR_MR2_Pos (2U) 2912 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2913 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2914 #define EXTI_EMR_MR3_Pos (3U) 2915 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2916 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2917 #define EXTI_EMR_MR4_Pos (4U) 2918 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2919 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2920 #define EXTI_EMR_MR5_Pos (5U) 2921 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2922 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2923 #define EXTI_EMR_MR6_Pos (6U) 2924 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2925 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2926 #define EXTI_EMR_MR7_Pos (7U) 2927 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2928 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2929 #define EXTI_EMR_MR8_Pos (8U) 2930 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2931 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2932 #define EXTI_EMR_MR9_Pos (9U) 2933 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2934 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2935 #define EXTI_EMR_MR10_Pos (10U) 2936 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2937 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2938 #define EXTI_EMR_MR11_Pos (11U) 2939 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2940 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2941 #define EXTI_EMR_MR12_Pos (12U) 2942 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2943 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2944 #define EXTI_EMR_MR13_Pos (13U) 2945 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2946 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2947 #define EXTI_EMR_MR14_Pos (14U) 2948 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2949 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2950 #define EXTI_EMR_MR15_Pos (15U) 2951 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2952 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2953 #define EXTI_EMR_MR16_Pos (16U) 2954 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2955 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2956 #define EXTI_EMR_MR17_Pos (17U) 2957 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2958 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2959 #define EXTI_EMR_MR19_Pos (19U) 2960 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 2961 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 2962 #define EXTI_EMR_MR20_Pos (20U) 2963 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 2964 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 2965 #define EXTI_EMR_MR22_Pos (22U) 2966 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 2967 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 2968 #define EXTI_EMR_MR23_Pos (23U) 2969 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 2970 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 2971 #define EXTI_EMR_MR24_Pos (24U) 2972 #define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */ 2973 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */ 2974 #define EXTI_EMR_MR25_Pos (25U) 2975 #define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ 2976 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ 2977 #define EXTI_EMR_MR27_Pos (27U) 2978 #define EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ 2979 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ 2980 #define EXTI_EMR_MR30_Pos (30U) 2981 #define EXTI_EMR_MR30_Msk (0x1UL << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */ 2982 #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */ 2983 2984 /* References Defines */ 2985 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2986 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2987 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2988 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2989 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2990 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2991 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2992 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2993 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2994 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2995 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2996 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2997 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2998 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2999 #define EXTI_EMR_EM14 EXTI_EMR_MR14 3000 #define EXTI_EMR_EM15 EXTI_EMR_MR15 3001 #define EXTI_EMR_EM16 EXTI_EMR_MR16 3002 #define EXTI_EMR_EM17 EXTI_EMR_MR17 3003 #if defined(EXTI_EMR_MR18) 3004 #define EXTI_EMR_EM18 EXTI_EMR_MR18 3005 #endif 3006 #define EXTI_EMR_EM19 EXTI_EMR_MR19 3007 #define EXTI_EMR_EM20 EXTI_EMR_MR20 3008 #if defined(EXTI_EMR_MR21) 3009 #define EXTI_EMR_EM21 EXTI_EMR_MR21 3010 #endif 3011 #define EXTI_EMR_EM22 EXTI_EMR_MR22 3012 #define EXTI_EMR_EM23 EXTI_EMR_MR23 3013 #if defined(EXTI_EMR_MR24) 3014 #define EXTI_EMR_EM24 EXTI_EMR_MR24 3015 #endif 3016 #define EXTI_EMR_EM25 EXTI_EMR_MR25 3017 #if defined(EXTI_EMR_MR26) 3018 #define EXTI_EMR_EM26 EXTI_EMR_MR26 3019 #endif 3020 #if defined(EXTI_EMR_MR27) 3021 #define EXTI_EMR_EM27 EXTI_EMR_MR27 3022 #endif 3023 #if defined(EXTI_EMR_MR28) 3024 #define EXTI_EMR_EM28 EXTI_EMR_MR28 3025 #endif 3026 #if defined(EXTI_EMR_MR29) 3027 #define EXTI_EMR_EM29 EXTI_EMR_MR29 3028 #endif 3029 #if defined(EXTI_EMR_MR30) 3030 #define EXTI_EMR_EM30 EXTI_EMR_MR30 3031 #endif 3032 #if defined(EXTI_EMR_MR31) 3033 #define EXTI_EMR_EM31 EXTI_EMR_MR31 3034 #endif 3035 3036 /****************** Bit definition for EXTI_RTSR register *******************/ 3037 #define EXTI_RTSR_TR0_Pos (0U) 3038 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 3039 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 3040 #define EXTI_RTSR_TR1_Pos (1U) 3041 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 3042 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 3043 #define EXTI_RTSR_TR2_Pos (2U) 3044 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 3045 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 3046 #define EXTI_RTSR_TR3_Pos (3U) 3047 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 3048 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 3049 #define EXTI_RTSR_TR4_Pos (4U) 3050 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 3051 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 3052 #define EXTI_RTSR_TR5_Pos (5U) 3053 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 3054 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 3055 #define EXTI_RTSR_TR6_Pos (6U) 3056 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 3057 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 3058 #define EXTI_RTSR_TR7_Pos (7U) 3059 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 3060 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 3061 #define EXTI_RTSR_TR8_Pos (8U) 3062 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 3063 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 3064 #define EXTI_RTSR_TR9_Pos (9U) 3065 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 3066 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 3067 #define EXTI_RTSR_TR10_Pos (10U) 3068 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 3069 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 3070 #define EXTI_RTSR_TR11_Pos (11U) 3071 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 3072 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 3073 #define EXTI_RTSR_TR12_Pos (12U) 3074 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 3075 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 3076 #define EXTI_RTSR_TR13_Pos (13U) 3077 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 3078 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 3079 #define EXTI_RTSR_TR14_Pos (14U) 3080 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 3081 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 3082 #define EXTI_RTSR_TR15_Pos (15U) 3083 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 3084 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 3085 #define EXTI_RTSR_TR16_Pos (16U) 3086 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 3087 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 3088 #define EXTI_RTSR_TR17_Pos (17U) 3089 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 3090 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 3091 #define EXTI_RTSR_TR19_Pos (19U) 3092 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 3093 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 3094 #define EXTI_RTSR_TR20_Pos (20U) 3095 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 3096 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 3097 #define EXTI_RTSR_TR22_Pos (22U) 3098 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 3099 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 3100 #define EXTI_RTSR_TR30_Pos (30U) 3101 #define EXTI_RTSR_TR30_Msk (0x1UL << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */ 3102 #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */ 3103 3104 /* References Defines */ 3105 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 3106 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 3107 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 3108 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 3109 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 3110 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 3111 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 3112 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 3113 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 3114 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 3115 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 3116 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 3117 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 3118 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 3119 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 3120 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 3121 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 3122 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 3123 #if defined(EXTI_RTSR_TR18) 3124 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 3125 #endif 3126 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 3127 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 3128 #if defined(EXTI_RTSR_TR21) 3129 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 3130 #endif 3131 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 3132 #if defined(EXTI_RTSR_TR23) 3133 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 3134 #endif 3135 #if defined(EXTI_RTSR_TR24) 3136 #define EXTI_RTSR_RT24 EXTI_RTSR_TR24 3137 #endif 3138 #if defined(EXTI_RTSR_TR25) 3139 #define EXTI_RTSR_RT25 EXTI_RTSR_TR25 3140 #endif 3141 #if defined(EXTI_RTSR_TR26) 3142 #define EXTI_RTSR_RT26 EXTI_RTSR_TR26 3143 #endif 3144 #if defined(EXTI_RTSR_TR27) 3145 #define EXTI_RTSR_RT27 EXTI_RTSR_TR27 3146 #endif 3147 #if defined(EXTI_RTSR_TR28) 3148 #define EXTI_RTSR_RT28 EXTI_RTSR_TR28 3149 #endif 3150 #if defined(EXTI_RTSR_TR29) 3151 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29 3152 #endif 3153 #if defined(EXTI_RTSR_TR30) 3154 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30 3155 #endif 3156 #if defined(EXTI_RTSR_TR31) 3157 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31 3158 #endif 3159 3160 /****************** Bit definition for EXTI_FTSR register *******************/ 3161 #define EXTI_FTSR_TR0_Pos (0U) 3162 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 3163 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 3164 #define EXTI_FTSR_TR1_Pos (1U) 3165 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 3166 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 3167 #define EXTI_FTSR_TR2_Pos (2U) 3168 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 3169 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 3170 #define EXTI_FTSR_TR3_Pos (3U) 3171 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 3172 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 3173 #define EXTI_FTSR_TR4_Pos (4U) 3174 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 3175 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 3176 #define EXTI_FTSR_TR5_Pos (5U) 3177 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 3178 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 3179 #define EXTI_FTSR_TR6_Pos (6U) 3180 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 3181 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 3182 #define EXTI_FTSR_TR7_Pos (7U) 3183 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 3184 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 3185 #define EXTI_FTSR_TR8_Pos (8U) 3186 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 3187 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 3188 #define EXTI_FTSR_TR9_Pos (9U) 3189 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 3190 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 3191 #define EXTI_FTSR_TR10_Pos (10U) 3192 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 3193 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 3194 #define EXTI_FTSR_TR11_Pos (11U) 3195 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 3196 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 3197 #define EXTI_FTSR_TR12_Pos (12U) 3198 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 3199 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 3200 #define EXTI_FTSR_TR13_Pos (13U) 3201 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 3202 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 3203 #define EXTI_FTSR_TR14_Pos (14U) 3204 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 3205 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 3206 #define EXTI_FTSR_TR15_Pos (15U) 3207 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 3208 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 3209 #define EXTI_FTSR_TR16_Pos (16U) 3210 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 3211 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 3212 #define EXTI_FTSR_TR17_Pos (17U) 3213 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 3214 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 3215 #define EXTI_FTSR_TR19_Pos (19U) 3216 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 3217 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 3218 #define EXTI_FTSR_TR20_Pos (20U) 3219 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 3220 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 3221 #define EXTI_FTSR_TR22_Pos (22U) 3222 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 3223 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 3224 #define EXTI_FTSR_TR30_Pos (30U) 3225 #define EXTI_FTSR_TR30_Msk (0x1UL << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */ 3226 #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */ 3227 3228 /* References Defines */ 3229 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 3230 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 3231 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 3232 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 3233 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 3234 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 3235 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 3236 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 3237 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 3238 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 3239 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 3240 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 3241 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 3242 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 3243 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 3244 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 3245 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 3246 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 3247 #if defined(EXTI_FTSR_TR18) 3248 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 3249 #endif 3250 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 3251 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 3252 #if defined(EXTI_FTSR_TR21) 3253 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 3254 #endif 3255 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 3256 #if defined(EXTI_FTSR_TR23) 3257 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 3258 #endif 3259 #if defined(EXTI_FTSR_TR24) 3260 #define EXTI_FTSR_FT24 EXTI_FTSR_TR24 3261 #endif 3262 #if defined(EXTI_FTSR_TR25) 3263 #define EXTI_FTSR_FT25 EXTI_FTSR_TR25 3264 #endif 3265 #if defined(EXTI_FTSR_TR26) 3266 #define EXTI_FTSR_FT26 EXTI_FTSR_TR26 3267 #endif 3268 #if defined(EXTI_FTSR_TR27) 3269 #define EXTI_FTSR_FT27 EXTI_FTSR_TR27 3270 #endif 3271 #if defined(EXTI_FTSR_TR28) 3272 #define EXTI_FTSR_FT28 EXTI_FTSR_TR28 3273 #endif 3274 #if defined(EXTI_FTSR_TR29) 3275 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29 3276 #endif 3277 #if defined(EXTI_FTSR_TR30) 3278 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30 3279 #endif 3280 #if defined(EXTI_FTSR_TR31) 3281 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31 3282 #endif 3283 3284 /****************** Bit definition for EXTI_SWIER register ******************/ 3285 #define EXTI_SWIER_SWIER0_Pos (0U) 3286 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 3287 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 3288 #define EXTI_SWIER_SWIER1_Pos (1U) 3289 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 3290 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 3291 #define EXTI_SWIER_SWIER2_Pos (2U) 3292 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 3293 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 3294 #define EXTI_SWIER_SWIER3_Pos (3U) 3295 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 3296 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 3297 #define EXTI_SWIER_SWIER4_Pos (4U) 3298 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 3299 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 3300 #define EXTI_SWIER_SWIER5_Pos (5U) 3301 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 3302 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 3303 #define EXTI_SWIER_SWIER6_Pos (6U) 3304 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 3305 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 3306 #define EXTI_SWIER_SWIER7_Pos (7U) 3307 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 3308 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 3309 #define EXTI_SWIER_SWIER8_Pos (8U) 3310 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 3311 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 3312 #define EXTI_SWIER_SWIER9_Pos (9U) 3313 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 3314 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 3315 #define EXTI_SWIER_SWIER10_Pos (10U) 3316 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 3317 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 3318 #define EXTI_SWIER_SWIER11_Pos (11U) 3319 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 3320 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 3321 #define EXTI_SWIER_SWIER12_Pos (12U) 3322 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 3323 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 3324 #define EXTI_SWIER_SWIER13_Pos (13U) 3325 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 3326 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 3327 #define EXTI_SWIER_SWIER14_Pos (14U) 3328 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 3329 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 3330 #define EXTI_SWIER_SWIER15_Pos (15U) 3331 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 3332 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 3333 #define EXTI_SWIER_SWIER16_Pos (16U) 3334 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 3335 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 3336 #define EXTI_SWIER_SWIER17_Pos (17U) 3337 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 3338 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 3339 #define EXTI_SWIER_SWIER19_Pos (19U) 3340 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 3341 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 3342 #define EXTI_SWIER_SWIER20_Pos (20U) 3343 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 3344 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 3345 #define EXTI_SWIER_SWIER22_Pos (22U) 3346 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 3347 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 3348 #define EXTI_SWIER_SWIER30_Pos (30U) 3349 #define EXTI_SWIER_SWIER30_Msk (0x1UL << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */ 3350 #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */ 3351 3352 /* References Defines */ 3353 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 3354 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 3355 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 3356 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 3357 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 3358 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 3359 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 3360 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 3361 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 3362 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 3363 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 3364 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 3365 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 3366 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 3367 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 3368 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 3369 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 3370 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 3371 #if defined(EXTI_SWIER_SWIER18) 3372 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 3373 #endif 3374 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 3375 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 3376 #if defined(EXTI_SWIER_SWIER21) 3377 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 3378 #endif 3379 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 3380 #if defined(EXTI_SWIER_SWIER23) 3381 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 3382 #endif 3383 #if defined(EXTI_SWIER_SWIER24) 3384 #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24 3385 #endif 3386 #if defined(EXTI_SWIER_SWIER25) 3387 #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25 3388 #endif 3389 #if defined(EXTI_SWIER_SWIER26) 3390 #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26 3391 #endif 3392 #if defined(EXTI_SWIER_SWIER27) 3393 #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27 3394 #endif 3395 #if defined(EXTI_SWIER_SWIER28) 3396 #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28 3397 #endif 3398 #if defined(EXTI_SWIER_SWIER29) 3399 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29 3400 #endif 3401 #if defined(EXTI_SWIER_SWIER30) 3402 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30 3403 #endif 3404 #if defined(EXTI_SWIER_SWIER31) 3405 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 3406 #endif 3407 3408 /******************* Bit definition for EXTI_PR register ********************/ 3409 #define EXTI_PR_PR0_Pos (0U) 3410 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 3411 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 3412 #define EXTI_PR_PR1_Pos (1U) 3413 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 3414 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 3415 #define EXTI_PR_PR2_Pos (2U) 3416 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 3417 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 3418 #define EXTI_PR_PR3_Pos (3U) 3419 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 3420 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 3421 #define EXTI_PR_PR4_Pos (4U) 3422 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 3423 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 3424 #define EXTI_PR_PR5_Pos (5U) 3425 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 3426 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 3427 #define EXTI_PR_PR6_Pos (6U) 3428 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 3429 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 3430 #define EXTI_PR_PR7_Pos (7U) 3431 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 3432 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 3433 #define EXTI_PR_PR8_Pos (8U) 3434 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 3435 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 3436 #define EXTI_PR_PR9_Pos (9U) 3437 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 3438 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 3439 #define EXTI_PR_PR10_Pos (10U) 3440 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 3441 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 3442 #define EXTI_PR_PR11_Pos (11U) 3443 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 3444 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 3445 #define EXTI_PR_PR12_Pos (12U) 3446 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 3447 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 3448 #define EXTI_PR_PR13_Pos (13U) 3449 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 3450 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 3451 #define EXTI_PR_PR14_Pos (14U) 3452 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 3453 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 3454 #define EXTI_PR_PR15_Pos (15U) 3455 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 3456 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 3457 #define EXTI_PR_PR16_Pos (16U) 3458 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 3459 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 3460 #define EXTI_PR_PR17_Pos (17U) 3461 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 3462 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 3463 #define EXTI_PR_PR19_Pos (19U) 3464 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 3465 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 3466 #define EXTI_PR_PR20_Pos (20U) 3467 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 3468 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 3469 #define EXTI_PR_PR22_Pos (22U) 3470 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 3471 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 3472 #define EXTI_PR_PR30_Pos (30U) 3473 #define EXTI_PR_PR30_Msk (0x1UL << EXTI_PR_PR30_Pos) /*!< 0x40000000 */ 3474 #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */ 3475 3476 /* References Defines */ 3477 #define EXTI_PR_PIF0 EXTI_PR_PR0 3478 #define EXTI_PR_PIF1 EXTI_PR_PR1 3479 #define EXTI_PR_PIF2 EXTI_PR_PR2 3480 #define EXTI_PR_PIF3 EXTI_PR_PR3 3481 #define EXTI_PR_PIF4 EXTI_PR_PR4 3482 #define EXTI_PR_PIF5 EXTI_PR_PR5 3483 #define EXTI_PR_PIF6 EXTI_PR_PR6 3484 #define EXTI_PR_PIF6 EXTI_PR_PR6 3485 #define EXTI_PR_PIF7 EXTI_PR_PR7 3486 #define EXTI_PR_PIF8 EXTI_PR_PR8 3487 #define EXTI_PR_PIF9 EXTI_PR_PR9 3488 #define EXTI_PR_PIF10 EXTI_PR_PR10 3489 #define EXTI_PR_PIF11 EXTI_PR_PR11 3490 #define EXTI_PR_PIF12 EXTI_PR_PR12 3491 #define EXTI_PR_PIF13 EXTI_PR_PR13 3492 #define EXTI_PR_PIF14 EXTI_PR_PR14 3493 #define EXTI_PR_PIF15 EXTI_PR_PR15 3494 #define EXTI_PR_PIF16 EXTI_PR_PR16 3495 #define EXTI_PR_PIF17 EXTI_PR_PR17 3496 #if defined(EXTI_PR_PR18) 3497 #define EXTI_PR_PIF18 EXTI_PR_PR18 3498 #endif 3499 #define EXTI_PR_PIF19 EXTI_PR_PR19 3500 #define EXTI_PR_PIF20 EXTI_PR_PR20 3501 #if defined(EXTI_PR_PR21) 3502 #define EXTI_PR_PIF21 EXTI_PR_PR21 3503 #endif 3504 #define EXTI_PR_PIF22 EXTI_PR_PR22 3505 #if defined(EXTI_PR_PR23) 3506 #define EXTI_PR_PIF23 EXTI_PR_PR23 3507 #endif 3508 #if defined(EXTI_PR_PR24) 3509 #define EXTI_PR_PIF24 EXTI_PR_PR24 3510 #endif 3511 #if defined(EXTI_PR_PR25) 3512 #define EXTI_PR_PIF25 EXTI_PR_PR25 3513 #endif 3514 #if defined(EXTI_PR_PR26) 3515 #define EXTI_PR_PIF26 EXTI_PR_PR26 3516 #endif 3517 #if defined(EXTI_PR_PR27) 3518 #define EXTI_PR_PIF27 EXTI_PR_PR27 3519 #endif 3520 #if defined(EXTI_PR_PR28) 3521 #define EXTI_PR_PIF28 EXTI_PR_PR28 3522 #endif 3523 #if defined(EXTI_PR_PR29) 3524 #define EXTI_PR_PIF29 EXTI_PR_PR29 3525 #endif 3526 #if defined(EXTI_PR_PR30) 3527 #define EXTI_PR_PIF30 EXTI_PR_PR30 3528 #endif 3529 #if defined(EXTI_PR_PR31) 3530 #define EXTI_PR_PIF31 EXTI_PR_PR31 3531 #endif 3532 3533 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */ 3534 3535 /******************* Bit definition for EXTI_IMR2 register ******************/ 3536 #define EXTI_IMR2_MR32_Pos (0U) 3537 #define EXTI_IMR2_MR32_Msk (0x1UL << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */ 3538 #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */ 3539 3540 /* References Defines */ 3541 3542 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32 3543 #if defined(EXTI_IMR2_MR33) 3544 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33 3545 #endif 3546 #if defined(EXTI_IMR2_MR34) 3547 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34 3548 #endif 3549 #if defined(EXTI_IMR2_MR35) 3550 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35 3551 #endif 3552 3553 #if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35) 3554 #define EXTI_IMR2_IM_Pos (0U) 3555 #define EXTI_IMR2_IM_Msk (0xFUL << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ 3556 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk 3557 #elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35) 3558 #define EXTI_IMR2_IM_Pos (0U) 3559 #define EXTI_IMR2_IM_Msk (0xDUL << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */ 3560 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk 3561 #else 3562 #define EXTI_IMR2_IM_Pos (0U) 3563 #define EXTI_IMR2_IM_Msk (0x1UL << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */ 3564 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk 3565 #endif 3566 3567 /******************* Bit definition for EXTI_EMR2 ****************************/ 3568 #define EXTI_EMR2_MR32_Pos (0U) 3569 #define EXTI_EMR2_MR32_Msk (0x1UL << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */ 3570 #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */ 3571 3572 /* References Defines */ 3573 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32 3574 #if defined(EXTI_EMR2_MR33) 3575 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33 3576 #endif 3577 #if defined(EXTI_EMR2_MR34) 3578 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34 3579 #endif 3580 #if defined(EXTI_EMR2_MR35) 3581 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35 3582 #endif 3583 3584 #if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35) 3585 #define EXTI_EMR2_EM_Pos (0U) 3586 #define EXTI_EMR2_EM_Msk (0xFUL << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */ 3587 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk 3588 #elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35) 3589 #define EXTI_EMR2_EM_Pos (0U) 3590 #define EXTI_EMR2_EM_Msk (0xDUL << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */ 3591 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk 3592 #else 3593 #define EXTI_EMR2_EM_Pos (0U) 3594 #define EXTI_EMR2_EM_Msk (0x1UL << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */ 3595 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk 3596 #endif 3597 3598 /****************** Bit definition for EXTI_RTSR2 register ********************/ 3599 #define EXTI_RTSR2_TR32_Pos (0U) 3600 #define EXTI_RTSR2_TR32_Msk (0x1UL << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ 3601 #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */ 3602 3603 /* References Defines */ 3604 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32 3605 #if defined(EXTI_RTSR2_TR33) 3606 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33 3607 #endif 3608 #if defined(EXTI_RTSR2_TR34) 3609 #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34 3610 #endif 3611 #if defined(EXTI_RTSR2_TR35) 3612 #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35 3613 #endif 3614 3615 /****************** Bit definition for EXTI_FTSR2 register ******************/ 3616 #define EXTI_FTSR2_TR32_Pos (0U) 3617 #define EXTI_FTSR2_TR32_Msk (0x1UL << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */ 3618 #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */ 3619 3620 /* References Defines */ 3621 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32 3622 #if defined(EXTI_FTSR2_TR33) 3623 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33 3624 #endif 3625 #if defined(EXTI_FTSR2_TR34) 3626 #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34 3627 #endif 3628 #if defined(EXTI_FTSR2_TR35) 3629 #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35 3630 #endif 3631 3632 /****************** Bit definition for EXTI_SWIER2 register *****************/ 3633 #define EXTI_SWIER2_SWIER32_Pos (0U) 3634 #define EXTI_SWIER2_SWIER32_Msk (0x1UL << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */ 3635 #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */ 3636 3637 /* References Defines */ 3638 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32 3639 #if defined(EXTI_SWIER2_SWIER33) 3640 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33 3641 #endif 3642 #if defined(EXTI_SWIER2_SWIER34) 3643 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34 3644 #endif 3645 #if defined(EXTI_SWIER2_SWIER35) 3646 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35 3647 #endif 3648 3649 /******************* Bit definition for EXTI_PR2 register *******************/ 3650 #define EXTI_PR2_PR32_Pos (0U) 3651 #define EXTI_PR2_PR32_Msk (0x1UL << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */ 3652 #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */ 3653 3654 /* References Defines */ 3655 #define EXTI_PR2_PIF32 EXTI_PR2_PR32 3656 #if defined(EXTI_PR2_PR33) 3657 #define EXTI_PR2_PIF33 EXTI_PR2_PR33 3658 #endif 3659 #if defined(EXTI_PR2_PR34) 3660 #define EXTI_PR2_PIF34 EXTI_PR2_PR34 3661 #endif 3662 #if defined(EXTI_PR2_PR35) 3663 #define EXTI_PR2_PIF35 EXTI_PR2_PR35 3664 #endif 3665 3666 3667 /******************************************************************************/ 3668 /* */ 3669 /* FLASH */ 3670 /* */ 3671 /******************************************************************************/ 3672 /******************* Bit definition for FLASH_ACR register ******************/ 3673 #define FLASH_ACR_LATENCY_Pos (0U) 3674 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 3675 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ 3676 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 3677 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 3678 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ 3679 3680 #define FLASH_ACR_HLFCYA_Pos (3U) 3681 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ 3682 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ 3683 #define FLASH_ACR_PRFTBE_Pos (4U) 3684 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 3685 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 3686 #define FLASH_ACR_PRFTBS_Pos (5U) 3687 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 3688 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 3689 3690 /****************** Bit definition for FLASH_KEYR register ******************/ 3691 #define FLASH_KEYR_FKEYR_Pos (0U) 3692 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 3693 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 3694 3695 #define RDP_KEY_Pos (0U) 3696 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ 3697 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ 3698 #define FLASH_KEY1_Pos (0U) 3699 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 3700 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ 3701 #define FLASH_KEY2_Pos (0U) 3702 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 3703 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ 3704 3705 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 3706 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 3707 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 3708 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 3709 3710 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 3711 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 3712 3713 /****************** Bit definition for FLASH_SR register *******************/ 3714 #define FLASH_SR_BSY_Pos (0U) 3715 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 3716 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 3717 #define FLASH_SR_PGERR_Pos (2U) 3718 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 3719 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 3720 #define FLASH_SR_WRPERR_Pos (4U) 3721 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 3722 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */ 3723 #define FLASH_SR_EOP_Pos (5U) 3724 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 3725 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 3726 3727 /******************* Bit definition for FLASH_CR register *******************/ 3728 #define FLASH_CR_PG_Pos (0U) 3729 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 3730 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 3731 #define FLASH_CR_PER_Pos (1U) 3732 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 3733 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 3734 #define FLASH_CR_MER_Pos (2U) 3735 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 3736 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 3737 #define FLASH_CR_OPTPG_Pos (4U) 3738 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 3739 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 3740 #define FLASH_CR_OPTER_Pos (5U) 3741 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 3742 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 3743 #define FLASH_CR_STRT_Pos (6U) 3744 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 3745 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 3746 #define FLASH_CR_LOCK_Pos (7U) 3747 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 3748 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 3749 #define FLASH_CR_OPTWRE_Pos (9U) 3750 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 3751 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 3752 #define FLASH_CR_ERRIE_Pos (10U) 3753 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 3754 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 3755 #define FLASH_CR_EOPIE_Pos (12U) 3756 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 3757 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 3758 #define FLASH_CR_OBL_LAUNCH_Pos (13U) 3759 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ 3760 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */ 3761 3762 /******************* Bit definition for FLASH_AR register *******************/ 3763 #define FLASH_AR_FAR_Pos (0U) 3764 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 3765 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 3766 3767 /****************** Bit definition for FLASH_OBR register *******************/ 3768 #define FLASH_OBR_OPTERR_Pos (0U) 3769 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 3770 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 3771 #define FLASH_OBR_RDPRT_Pos (1U) 3772 #define FLASH_OBR_RDPRT_Msk (0x3UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */ 3773 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ 3774 #define FLASH_OBR_RDPRT_1 (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ 3775 #define FLASH_OBR_RDPRT_2 (0x3UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */ 3776 3777 #define FLASH_OBR_USER_Pos (8U) 3778 #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ 3779 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 3780 #define FLASH_OBR_IWDG_SW_Pos (8U) 3781 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ 3782 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 3783 #define FLASH_OBR_nRST_STOP_Pos (9U) 3784 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ 3785 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 3786 #define FLASH_OBR_nRST_STDBY_Pos (10U) 3787 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ 3788 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 3789 #define FLASH_OBR_nBOOT1_Pos (12U) 3790 #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ 3791 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ 3792 #define FLASH_OBR_VDDA_MONITOR_Pos (13U) 3793 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ 3794 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */ 3795 #define FLASH_OBR_SRAM_PE_Pos (14U) 3796 #define FLASH_OBR_SRAM_PE_Msk (0x1UL << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */ 3797 #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */ 3798 #define FLASH_OBR_DATA0_Pos (16U) 3799 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ 3800 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 3801 #define FLASH_OBR_DATA1_Pos (24U) 3802 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ 3803 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 3804 3805 /* Legacy defines */ 3806 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW 3807 3808 /****************** Bit definition for FLASH_WRPR register ******************/ 3809 #define FLASH_WRPR_WRP_Pos (0U) 3810 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ 3811 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 3812 3813 /*----------------------------------------------------------------------------*/ 3814 3815 /****************** Bit definition for OB_RDP register **********************/ 3816 #define OB_RDP_RDP_Pos (0U) 3817 #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ 3818 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ 3819 #define OB_RDP_nRDP_Pos (8U) 3820 #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 3821 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 3822 3823 /****************** Bit definition for OB_USER register *********************/ 3824 #define OB_USER_USER_Pos (16U) 3825 #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ 3826 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ 3827 #define OB_USER_nUSER_Pos (24U) 3828 #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ 3829 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ 3830 3831 /****************** Bit definition for FLASH_WRP0 register ******************/ 3832 #define OB_WRP0_WRP0_Pos (0U) 3833 #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ 3834 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 3835 #define OB_WRP0_nWRP0_Pos (8U) 3836 #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 3837 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 3838 3839 /****************** Bit definition for FLASH_WRP1 register ******************/ 3840 #define OB_WRP1_WRP1_Pos (16U) 3841 #define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 3842 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 3843 #define OB_WRP1_nWRP1_Pos (24U) 3844 #define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 3845 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 3846 3847 3848 /******************************************************************************/ 3849 /* */ 3850 /* General Purpose I/O (GPIO) */ 3851 /* */ 3852 /******************************************************************************/ 3853 /******************* Bit definition for GPIO_MODER register *****************/ 3854 #define GPIO_MODER_MODER0_Pos (0U) 3855 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 3856 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 3857 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 3858 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 3859 #define GPIO_MODER_MODER1_Pos (2U) 3860 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 3861 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 3862 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 3863 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 3864 #define GPIO_MODER_MODER2_Pos (4U) 3865 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 3866 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 3867 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 3868 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 3869 #define GPIO_MODER_MODER3_Pos (6U) 3870 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 3871 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 3872 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 3873 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 3874 #define GPIO_MODER_MODER4_Pos (8U) 3875 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 3876 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 3877 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 3878 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 3879 #define GPIO_MODER_MODER5_Pos (10U) 3880 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 3881 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 3882 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 3883 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 3884 #define GPIO_MODER_MODER6_Pos (12U) 3885 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 3886 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 3887 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 3888 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 3889 #define GPIO_MODER_MODER7_Pos (14U) 3890 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 3891 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 3892 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 3893 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 3894 #define GPIO_MODER_MODER8_Pos (16U) 3895 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 3896 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 3897 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 3898 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 3899 #define GPIO_MODER_MODER9_Pos (18U) 3900 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 3901 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 3902 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 3903 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 3904 #define GPIO_MODER_MODER10_Pos (20U) 3905 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 3906 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 3907 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 3908 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 3909 #define GPIO_MODER_MODER11_Pos (22U) 3910 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 3911 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 3912 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 3913 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 3914 #define GPIO_MODER_MODER12_Pos (24U) 3915 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 3916 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 3917 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 3918 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 3919 #define GPIO_MODER_MODER13_Pos (26U) 3920 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 3921 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 3922 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 3923 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 3924 #define GPIO_MODER_MODER14_Pos (28U) 3925 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 3926 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 3927 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 3928 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 3929 #define GPIO_MODER_MODER15_Pos (30U) 3930 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 3931 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 3932 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 3933 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 3934 3935 /****************** Bit definition for GPIO_OTYPER register *****************/ 3936 #define GPIO_OTYPER_OT_0 (0x00000001U) 3937 #define GPIO_OTYPER_OT_1 (0x00000002U) 3938 #define GPIO_OTYPER_OT_2 (0x00000004U) 3939 #define GPIO_OTYPER_OT_3 (0x00000008U) 3940 #define GPIO_OTYPER_OT_4 (0x00000010U) 3941 #define GPIO_OTYPER_OT_5 (0x00000020U) 3942 #define GPIO_OTYPER_OT_6 (0x00000040U) 3943 #define GPIO_OTYPER_OT_7 (0x00000080U) 3944 #define GPIO_OTYPER_OT_8 (0x00000100U) 3945 #define GPIO_OTYPER_OT_9 (0x00000200U) 3946 #define GPIO_OTYPER_OT_10 (0x00000400U) 3947 #define GPIO_OTYPER_OT_11 (0x00000800U) 3948 #define GPIO_OTYPER_OT_12 (0x00001000U) 3949 #define GPIO_OTYPER_OT_13 (0x00002000U) 3950 #define GPIO_OTYPER_OT_14 (0x00004000U) 3951 #define GPIO_OTYPER_OT_15 (0x00008000U) 3952 3953 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 3954 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 3955 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ 3956 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 3957 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ 3958 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ 3959 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 3960 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ 3961 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 3962 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ 3963 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ 3964 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 3965 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ 3966 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 3967 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ 3968 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ 3969 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 3970 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ 3971 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 3972 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ 3973 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ 3974 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 3975 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ 3976 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 3977 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ 3978 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ 3979 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 3980 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ 3981 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 3982 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ 3983 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ 3984 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 3985 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ 3986 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 3987 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ 3988 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ 3989 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 3990 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ 3991 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 3992 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ 3993 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ 3994 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 3995 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ 3996 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 3997 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ 3998 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ 3999 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 4000 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ 4001 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 4002 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ 4003 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ 4004 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 4005 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ 4006 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 4007 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ 4008 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ 4009 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 4010 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ 4011 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 4012 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ 4013 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ 4014 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 4015 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ 4016 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 4017 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ 4018 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ 4019 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 4020 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ 4021 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 4022 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ 4023 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ 4024 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 4025 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ 4026 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 4027 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ 4028 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ 4029 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 4030 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ 4031 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 4032 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ 4033 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ 4034 4035 /******************* Bit definition for GPIO_PUPDR register ******************/ 4036 #define GPIO_PUPDR_PUPDR0_Pos (0U) 4037 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 4038 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 4039 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 4040 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 4041 #define GPIO_PUPDR_PUPDR1_Pos (2U) 4042 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 4043 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 4044 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 4045 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 4046 #define GPIO_PUPDR_PUPDR2_Pos (4U) 4047 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 4048 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 4049 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 4050 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 4051 #define GPIO_PUPDR_PUPDR3_Pos (6U) 4052 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 4053 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 4054 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 4055 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 4056 #define GPIO_PUPDR_PUPDR4_Pos (8U) 4057 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 4058 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 4059 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 4060 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 4061 #define GPIO_PUPDR_PUPDR5_Pos (10U) 4062 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 4063 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 4064 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 4065 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 4066 #define GPIO_PUPDR_PUPDR6_Pos (12U) 4067 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 4068 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 4069 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 4070 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 4071 #define GPIO_PUPDR_PUPDR7_Pos (14U) 4072 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 4073 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 4074 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 4075 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 4076 #define GPIO_PUPDR_PUPDR8_Pos (16U) 4077 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 4078 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 4079 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 4080 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 4081 #define GPIO_PUPDR_PUPDR9_Pos (18U) 4082 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 4083 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 4084 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 4085 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 4086 #define GPIO_PUPDR_PUPDR10_Pos (20U) 4087 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 4088 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 4089 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 4090 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 4091 #define GPIO_PUPDR_PUPDR11_Pos (22U) 4092 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 4093 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 4094 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 4095 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 4096 #define GPIO_PUPDR_PUPDR12_Pos (24U) 4097 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 4098 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 4099 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 4100 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 4101 #define GPIO_PUPDR_PUPDR13_Pos (26U) 4102 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 4103 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 4104 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 4105 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 4106 #define GPIO_PUPDR_PUPDR14_Pos (28U) 4107 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 4108 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 4109 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 4110 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 4111 #define GPIO_PUPDR_PUPDR15_Pos (30U) 4112 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 4113 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 4114 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 4115 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 4116 4117 /******************* Bit definition for GPIO_IDR register *******************/ 4118 #define GPIO_IDR_0 (0x00000001U) 4119 #define GPIO_IDR_1 (0x00000002U) 4120 #define GPIO_IDR_2 (0x00000004U) 4121 #define GPIO_IDR_3 (0x00000008U) 4122 #define GPIO_IDR_4 (0x00000010U) 4123 #define GPIO_IDR_5 (0x00000020U) 4124 #define GPIO_IDR_6 (0x00000040U) 4125 #define GPIO_IDR_7 (0x00000080U) 4126 #define GPIO_IDR_8 (0x00000100U) 4127 #define GPIO_IDR_9 (0x00000200U) 4128 #define GPIO_IDR_10 (0x00000400U) 4129 #define GPIO_IDR_11 (0x00000800U) 4130 #define GPIO_IDR_12 (0x00001000U) 4131 #define GPIO_IDR_13 (0x00002000U) 4132 #define GPIO_IDR_14 (0x00004000U) 4133 #define GPIO_IDR_15 (0x00008000U) 4134 4135 /****************** Bit definition for GPIO_ODR register ********************/ 4136 #define GPIO_ODR_0 (0x00000001U) 4137 #define GPIO_ODR_1 (0x00000002U) 4138 #define GPIO_ODR_2 (0x00000004U) 4139 #define GPIO_ODR_3 (0x00000008U) 4140 #define GPIO_ODR_4 (0x00000010U) 4141 #define GPIO_ODR_5 (0x00000020U) 4142 #define GPIO_ODR_6 (0x00000040U) 4143 #define GPIO_ODR_7 (0x00000080U) 4144 #define GPIO_ODR_8 (0x00000100U) 4145 #define GPIO_ODR_9 (0x00000200U) 4146 #define GPIO_ODR_10 (0x00000400U) 4147 #define GPIO_ODR_11 (0x00000800U) 4148 #define GPIO_ODR_12 (0x00001000U) 4149 #define GPIO_ODR_13 (0x00002000U) 4150 #define GPIO_ODR_14 (0x00004000U) 4151 #define GPIO_ODR_15 (0x00008000U) 4152 4153 /****************** Bit definition for GPIO_BSRR register ********************/ 4154 #define GPIO_BSRR_BS_0 (0x00000001U) 4155 #define GPIO_BSRR_BS_1 (0x00000002U) 4156 #define GPIO_BSRR_BS_2 (0x00000004U) 4157 #define GPIO_BSRR_BS_3 (0x00000008U) 4158 #define GPIO_BSRR_BS_4 (0x00000010U) 4159 #define GPIO_BSRR_BS_5 (0x00000020U) 4160 #define GPIO_BSRR_BS_6 (0x00000040U) 4161 #define GPIO_BSRR_BS_7 (0x00000080U) 4162 #define GPIO_BSRR_BS_8 (0x00000100U) 4163 #define GPIO_BSRR_BS_9 (0x00000200U) 4164 #define GPIO_BSRR_BS_10 (0x00000400U) 4165 #define GPIO_BSRR_BS_11 (0x00000800U) 4166 #define GPIO_BSRR_BS_12 (0x00001000U) 4167 #define GPIO_BSRR_BS_13 (0x00002000U) 4168 #define GPIO_BSRR_BS_14 (0x00004000U) 4169 #define GPIO_BSRR_BS_15 (0x00008000U) 4170 #define GPIO_BSRR_BR_0 (0x00010000U) 4171 #define GPIO_BSRR_BR_1 (0x00020000U) 4172 #define GPIO_BSRR_BR_2 (0x00040000U) 4173 #define GPIO_BSRR_BR_3 (0x00080000U) 4174 #define GPIO_BSRR_BR_4 (0x00100000U) 4175 #define GPIO_BSRR_BR_5 (0x00200000U) 4176 #define GPIO_BSRR_BR_6 (0x00400000U) 4177 #define GPIO_BSRR_BR_7 (0x00800000U) 4178 #define GPIO_BSRR_BR_8 (0x01000000U) 4179 #define GPIO_BSRR_BR_9 (0x02000000U) 4180 #define GPIO_BSRR_BR_10 (0x04000000U) 4181 #define GPIO_BSRR_BR_11 (0x08000000U) 4182 #define GPIO_BSRR_BR_12 (0x10000000U) 4183 #define GPIO_BSRR_BR_13 (0x20000000U) 4184 #define GPIO_BSRR_BR_14 (0x40000000U) 4185 #define GPIO_BSRR_BR_15 (0x80000000U) 4186 4187 /****************** Bit definition for GPIO_LCKR register ********************/ 4188 #define GPIO_LCKR_LCK0_Pos (0U) 4189 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 4190 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 4191 #define GPIO_LCKR_LCK1_Pos (1U) 4192 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 4193 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 4194 #define GPIO_LCKR_LCK2_Pos (2U) 4195 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 4196 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 4197 #define GPIO_LCKR_LCK3_Pos (3U) 4198 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 4199 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 4200 #define GPIO_LCKR_LCK4_Pos (4U) 4201 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 4202 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 4203 #define GPIO_LCKR_LCK5_Pos (5U) 4204 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 4205 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 4206 #define GPIO_LCKR_LCK6_Pos (6U) 4207 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 4208 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 4209 #define GPIO_LCKR_LCK7_Pos (7U) 4210 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 4211 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 4212 #define GPIO_LCKR_LCK8_Pos (8U) 4213 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 4214 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 4215 #define GPIO_LCKR_LCK9_Pos (9U) 4216 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 4217 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 4218 #define GPIO_LCKR_LCK10_Pos (10U) 4219 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 4220 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 4221 #define GPIO_LCKR_LCK11_Pos (11U) 4222 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 4223 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 4224 #define GPIO_LCKR_LCK12_Pos (12U) 4225 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 4226 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 4227 #define GPIO_LCKR_LCK13_Pos (13U) 4228 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 4229 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 4230 #define GPIO_LCKR_LCK14_Pos (14U) 4231 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 4232 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 4233 #define GPIO_LCKR_LCK15_Pos (15U) 4234 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 4235 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 4236 #define GPIO_LCKR_LCKK_Pos (16U) 4237 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 4238 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 4239 4240 /****************** Bit definition for GPIO_AFRL register ********************/ 4241 #define GPIO_AFRL_AFRL0_Pos (0U) 4242 #define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ 4243 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk 4244 #define GPIO_AFRL_AFRL1_Pos (4U) 4245 #define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ 4246 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk 4247 #define GPIO_AFRL_AFRL2_Pos (8U) 4248 #define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ 4249 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk 4250 #define GPIO_AFRL_AFRL3_Pos (12U) 4251 #define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ 4252 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk 4253 #define GPIO_AFRL_AFRL4_Pos (16U) 4254 #define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ 4255 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk 4256 #define GPIO_AFRL_AFRL5_Pos (20U) 4257 #define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ 4258 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk 4259 #define GPIO_AFRL_AFRL6_Pos (24U) 4260 #define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ 4261 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk 4262 #define GPIO_AFRL_AFRL7_Pos (28U) 4263 #define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ 4264 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk 4265 4266 /****************** Bit definition for GPIO_AFRH register ********************/ 4267 #define GPIO_AFRH_AFRH0_Pos (0U) 4268 #define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ 4269 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk 4270 #define GPIO_AFRH_AFRH1_Pos (4U) 4271 #define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ 4272 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk 4273 #define GPIO_AFRH_AFRH2_Pos (8U) 4274 #define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ 4275 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk 4276 #define GPIO_AFRH_AFRH3_Pos (12U) 4277 #define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ 4278 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk 4279 #define GPIO_AFRH_AFRH4_Pos (16U) 4280 #define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ 4281 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk 4282 #define GPIO_AFRH_AFRH5_Pos (20U) 4283 #define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ 4284 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk 4285 #define GPIO_AFRH_AFRH6_Pos (24U) 4286 #define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ 4287 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk 4288 #define GPIO_AFRH_AFRH7_Pos (28U) 4289 #define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ 4290 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk 4291 4292 /****************** Bit definition for GPIO_BRR register *********************/ 4293 #define GPIO_BRR_BR_0 (0x00000001U) 4294 #define GPIO_BRR_BR_1 (0x00000002U) 4295 #define GPIO_BRR_BR_2 (0x00000004U) 4296 #define GPIO_BRR_BR_3 (0x00000008U) 4297 #define GPIO_BRR_BR_4 (0x00000010U) 4298 #define GPIO_BRR_BR_5 (0x00000020U) 4299 #define GPIO_BRR_BR_6 (0x00000040U) 4300 #define GPIO_BRR_BR_7 (0x00000080U) 4301 #define GPIO_BRR_BR_8 (0x00000100U) 4302 #define GPIO_BRR_BR_9 (0x00000200U) 4303 #define GPIO_BRR_BR_10 (0x00000400U) 4304 #define GPIO_BRR_BR_11 (0x00000800U) 4305 #define GPIO_BRR_BR_12 (0x00001000U) 4306 #define GPIO_BRR_BR_13 (0x00002000U) 4307 #define GPIO_BRR_BR_14 (0x00004000U) 4308 #define GPIO_BRR_BR_15 (0x00008000U) 4309 4310 /******************************************************************************/ 4311 /* */ 4312 /* Inter-integrated Circuit Interface (I2C) */ 4313 /* */ 4314 /******************************************************************************/ 4315 /******************* Bit definition for I2C_CR1 register *******************/ 4316 #define I2C_CR1_PE_Pos (0U) 4317 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 4318 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 4319 #define I2C_CR1_TXIE_Pos (1U) 4320 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 4321 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 4322 #define I2C_CR1_RXIE_Pos (2U) 4323 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 4324 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 4325 #define I2C_CR1_ADDRIE_Pos (3U) 4326 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 4327 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 4328 #define I2C_CR1_NACKIE_Pos (4U) 4329 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 4330 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 4331 #define I2C_CR1_STOPIE_Pos (5U) 4332 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 4333 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 4334 #define I2C_CR1_TCIE_Pos (6U) 4335 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 4336 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 4337 #define I2C_CR1_ERRIE_Pos (7U) 4338 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 4339 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 4340 #define I2C_CR1_DNF_Pos (8U) 4341 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 4342 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 4343 #define I2C_CR1_ANFOFF_Pos (12U) 4344 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 4345 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 4346 #define I2C_CR1_SWRST_Pos (13U) 4347 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 4348 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 4349 #define I2C_CR1_TXDMAEN_Pos (14U) 4350 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 4351 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 4352 #define I2C_CR1_RXDMAEN_Pos (15U) 4353 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 4354 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 4355 #define I2C_CR1_SBC_Pos (16U) 4356 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 4357 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 4358 #define I2C_CR1_NOSTRETCH_Pos (17U) 4359 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 4360 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 4361 #define I2C_CR1_WUPEN_Pos (18U) 4362 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 4363 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 4364 #define I2C_CR1_GCEN_Pos (19U) 4365 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 4366 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 4367 #define I2C_CR1_SMBHEN_Pos (20U) 4368 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 4369 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 4370 #define I2C_CR1_SMBDEN_Pos (21U) 4371 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 4372 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 4373 #define I2C_CR1_ALERTEN_Pos (22U) 4374 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 4375 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 4376 #define I2C_CR1_PECEN_Pos (23U) 4377 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 4378 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 4379 4380 /* Legacy defines */ 4381 #define I2C_CR1_DFN I2C_CR1_DNF 4382 4383 /****************** Bit definition for I2C_CR2 register ********************/ 4384 #define I2C_CR2_SADD_Pos (0U) 4385 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 4386 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 4387 #define I2C_CR2_RD_WRN_Pos (10U) 4388 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 4389 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 4390 #define I2C_CR2_ADD10_Pos (11U) 4391 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 4392 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 4393 #define I2C_CR2_HEAD10R_Pos (12U) 4394 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 4395 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 4396 #define I2C_CR2_START_Pos (13U) 4397 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 4398 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 4399 #define I2C_CR2_STOP_Pos (14U) 4400 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 4401 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 4402 #define I2C_CR2_NACK_Pos (15U) 4403 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 4404 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 4405 #define I2C_CR2_NBYTES_Pos (16U) 4406 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 4407 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 4408 #define I2C_CR2_RELOAD_Pos (24U) 4409 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 4410 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 4411 #define I2C_CR2_AUTOEND_Pos (25U) 4412 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 4413 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 4414 #define I2C_CR2_PECBYTE_Pos (26U) 4415 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 4416 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 4417 4418 /******************* Bit definition for I2C_OAR1 register ******************/ 4419 #define I2C_OAR1_OA1_Pos (0U) 4420 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 4421 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 4422 #define I2C_OAR1_OA1MODE_Pos (10U) 4423 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 4424 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 4425 #define I2C_OAR1_OA1EN_Pos (15U) 4426 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 4427 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 4428 4429 /******************* Bit definition for I2C_OAR2 register *******************/ 4430 #define I2C_OAR2_OA2_Pos (1U) 4431 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 4432 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 4433 #define I2C_OAR2_OA2MSK_Pos (8U) 4434 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 4435 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 4436 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 4437 #define I2C_OAR2_OA2MASK01_Pos (8U) 4438 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 4439 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 4440 #define I2C_OAR2_OA2MASK02_Pos (9U) 4441 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 4442 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 4443 #define I2C_OAR2_OA2MASK03_Pos (8U) 4444 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 4445 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 4446 #define I2C_OAR2_OA2MASK04_Pos (10U) 4447 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 4448 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 4449 #define I2C_OAR2_OA2MASK05_Pos (8U) 4450 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 4451 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 4452 #define I2C_OAR2_OA2MASK06_Pos (9U) 4453 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 4454 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 4455 #define I2C_OAR2_OA2MASK07_Pos (8U) 4456 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 4457 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 4458 #define I2C_OAR2_OA2EN_Pos (15U) 4459 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 4460 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 4461 4462 /******************* Bit definition for I2C_TIMINGR register *****************/ 4463 #define I2C_TIMINGR_SCLL_Pos (0U) 4464 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 4465 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 4466 #define I2C_TIMINGR_SCLH_Pos (8U) 4467 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 4468 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 4469 #define I2C_TIMINGR_SDADEL_Pos (16U) 4470 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 4471 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 4472 #define I2C_TIMINGR_SCLDEL_Pos (20U) 4473 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 4474 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 4475 #define I2C_TIMINGR_PRESC_Pos (28U) 4476 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 4477 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 4478 4479 /******************* Bit definition for I2C_TIMEOUTR register *****************/ 4480 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 4481 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 4482 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 4483 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 4484 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 4485 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 4486 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 4487 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 4488 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 4489 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 4490 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 4491 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 4492 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 4493 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 4494 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 4495 4496 /****************** Bit definition for I2C_ISR register *********************/ 4497 #define I2C_ISR_TXE_Pos (0U) 4498 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 4499 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 4500 #define I2C_ISR_TXIS_Pos (1U) 4501 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 4502 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 4503 #define I2C_ISR_RXNE_Pos (2U) 4504 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 4505 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 4506 #define I2C_ISR_ADDR_Pos (3U) 4507 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 4508 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 4509 #define I2C_ISR_NACKF_Pos (4U) 4510 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 4511 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 4512 #define I2C_ISR_STOPF_Pos (5U) 4513 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 4514 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 4515 #define I2C_ISR_TC_Pos (6U) 4516 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 4517 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 4518 #define I2C_ISR_TCR_Pos (7U) 4519 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 4520 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 4521 #define I2C_ISR_BERR_Pos (8U) 4522 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 4523 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 4524 #define I2C_ISR_ARLO_Pos (9U) 4525 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 4526 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 4527 #define I2C_ISR_OVR_Pos (10U) 4528 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 4529 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 4530 #define I2C_ISR_PECERR_Pos (11U) 4531 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 4532 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 4533 #define I2C_ISR_TIMEOUT_Pos (12U) 4534 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 4535 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 4536 #define I2C_ISR_ALERT_Pos (13U) 4537 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 4538 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 4539 #define I2C_ISR_BUSY_Pos (15U) 4540 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 4541 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 4542 #define I2C_ISR_DIR_Pos (16U) 4543 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 4544 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 4545 #define I2C_ISR_ADDCODE_Pos (17U) 4546 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 4547 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 4548 4549 /****************** Bit definition for I2C_ICR register *********************/ 4550 #define I2C_ICR_ADDRCF_Pos (3U) 4551 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 4552 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 4553 #define I2C_ICR_NACKCF_Pos (4U) 4554 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 4555 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 4556 #define I2C_ICR_STOPCF_Pos (5U) 4557 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 4558 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 4559 #define I2C_ICR_BERRCF_Pos (8U) 4560 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 4561 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 4562 #define I2C_ICR_ARLOCF_Pos (9U) 4563 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 4564 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 4565 #define I2C_ICR_OVRCF_Pos (10U) 4566 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 4567 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 4568 #define I2C_ICR_PECCF_Pos (11U) 4569 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 4570 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 4571 #define I2C_ICR_TIMOUTCF_Pos (12U) 4572 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 4573 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 4574 #define I2C_ICR_ALERTCF_Pos (13U) 4575 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 4576 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 4577 4578 /****************** Bit definition for I2C_PECR register ********************/ 4579 #define I2C_PECR_PEC_Pos (0U) 4580 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 4581 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 4582 4583 /****************** Bit definition for I2C_RXDR register *********************/ 4584 #define I2C_RXDR_RXDATA_Pos (0U) 4585 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 4586 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 4587 4588 /****************** Bit definition for I2C_TXDR register *********************/ 4589 #define I2C_TXDR_TXDATA_Pos (0U) 4590 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 4591 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 4592 4593 4594 /******************************************************************************/ 4595 /* */ 4596 /* Independent WATCHDOG (IWDG) */ 4597 /* */ 4598 /******************************************************************************/ 4599 /******************* Bit definition for IWDG_KR register ********************/ 4600 #define IWDG_KR_KEY_Pos (0U) 4601 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 4602 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 4603 4604 /******************* Bit definition for IWDG_PR register ********************/ 4605 #define IWDG_PR_PR_Pos (0U) 4606 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 4607 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 4608 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 4609 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 4610 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 4611 4612 /******************* Bit definition for IWDG_RLR register *******************/ 4613 #define IWDG_RLR_RL_Pos (0U) 4614 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 4615 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 4616 4617 /******************* Bit definition for IWDG_SR register ********************/ 4618 #define IWDG_SR_PVU_Pos (0U) 4619 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 4620 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 4621 #define IWDG_SR_RVU_Pos (1U) 4622 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 4623 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 4624 #define IWDG_SR_WVU_Pos (2U) 4625 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 4626 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 4627 4628 /******************* Bit definition for IWDG_KR register ********************/ 4629 #define IWDG_WINR_WIN_Pos (0U) 4630 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 4631 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 4632 4633 /******************************************************************************/ 4634 /* */ 4635 /* Power Control */ 4636 /* */ 4637 /******************************************************************************/ 4638 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ 4639 /******************** Bit definition for PWR_CR register ********************/ 4640 #define PWR_CR_LPDS_Pos (0U) 4641 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 4642 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ 4643 #define PWR_CR_PDDS_Pos (1U) 4644 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 4645 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 4646 #define PWR_CR_CWUF_Pos (2U) 4647 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 4648 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 4649 #define PWR_CR_CSBF_Pos (3U) 4650 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 4651 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 4652 #define PWR_CR_PVDE_Pos (4U) 4653 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 4654 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 4655 4656 #define PWR_CR_PLS_Pos (5U) 4657 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 4658 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 4659 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 4660 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 4661 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 4662 4663 /*!< PVD level configuration */ 4664 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 4665 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 4666 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 4667 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 4668 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 4669 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 4670 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 4671 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 4672 4673 #define PWR_CR_DBP_Pos (8U) 4674 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 4675 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 4676 4677 /******************* Bit definition for PWR_CSR register ********************/ 4678 #define PWR_CSR_WUF_Pos (0U) 4679 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 4680 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 4681 #define PWR_CSR_SBF_Pos (1U) 4682 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 4683 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 4684 #define PWR_CSR_PVDO_Pos (2U) 4685 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 4686 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 4687 #define PWR_CSR_VREFINTRDYF_Pos (3U) 4688 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 4689 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 4690 4691 #define PWR_CSR_EWUP1_Pos (8U) 4692 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 4693 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 4694 #define PWR_CSR_EWUP2_Pos (9U) 4695 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 4696 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 4697 #define PWR_CSR_EWUP3_Pos (10U) 4698 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 4699 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 4700 4701 /******************************************************************************/ 4702 /* */ 4703 /* Reset and Clock Control */ 4704 /* */ 4705 /******************************************************************************/ 4706 /******************** Bit definition for RCC_CR register ********************/ 4707 #define RCC_CR_HSION_Pos (0U) 4708 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 4709 #define RCC_CR_HSION RCC_CR_HSION_Msk 4710 #define RCC_CR_HSIRDY_Pos (1U) 4711 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 4712 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk 4713 4714 #define RCC_CR_HSITRIM_Pos (3U) 4715 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 4716 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk 4717 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 4718 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 4719 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 4720 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 4721 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 4722 4723 #define RCC_CR_HSICAL_Pos (8U) 4724 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 4725 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk 4726 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 4727 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 4728 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 4729 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 4730 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 4731 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 4732 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 4733 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 4734 4735 #define RCC_CR_HSEON_Pos (16U) 4736 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 4737 #define RCC_CR_HSEON RCC_CR_HSEON_Msk 4738 #define RCC_CR_HSERDY_Pos (17U) 4739 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 4740 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk 4741 #define RCC_CR_HSEBYP_Pos (18U) 4742 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 4743 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk 4744 #define RCC_CR_CSSON_Pos (19U) 4745 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 4746 #define RCC_CR_CSSON RCC_CR_CSSON_Msk 4747 #define RCC_CR_PLLON_Pos (24U) 4748 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 4749 #define RCC_CR_PLLON RCC_CR_PLLON_Msk 4750 #define RCC_CR_PLLRDY_Pos (25U) 4751 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 4752 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk 4753 4754 /******************** Bit definition for RCC_CFGR register ******************/ 4755 /*!< SW configuration */ 4756 #define RCC_CFGR_SW_Pos (0U) 4757 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 4758 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 4759 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 4760 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 4761 4762 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ 4763 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ 4764 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ 4765 4766 /*!< SWS configuration */ 4767 #define RCC_CFGR_SWS_Pos (2U) 4768 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 4769 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 4770 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 4771 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 4772 4773 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ 4774 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ 4775 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ 4776 4777 /*!< HPRE configuration */ 4778 #define RCC_CFGR_HPRE_Pos (4U) 4779 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 4780 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 4781 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 4782 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 4783 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 4784 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 4785 4786 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 4787 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 4788 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 4789 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 4790 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 4791 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 4792 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 4793 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 4794 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 4795 4796 /*!< PPRE1 configuration */ 4797 #define RCC_CFGR_PPRE1_Pos (8U) 4798 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 4799 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 4800 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 4801 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 4802 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 4803 4804 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 4805 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 4806 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 4807 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 4808 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 4809 4810 /*!< PPRE2 configuration */ 4811 #define RCC_CFGR_PPRE2_Pos (11U) 4812 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 4813 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 4814 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 4815 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 4816 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 4817 4818 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 4819 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 4820 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 4821 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 4822 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 4823 4824 #define RCC_CFGR_PLLSRC_Pos (16U) 4825 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 4826 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 4827 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 4828 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ 4829 4830 #define RCC_CFGR_PLLXTPRE_Pos (17U) 4831 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 4832 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 4833 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ 4834 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ 4835 4836 /*!< PLLMUL configuration */ 4837 #define RCC_CFGR_PLLMUL_Pos (18U) 4838 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 4839 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 4840 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 4841 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 4842 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 4843 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 4844 4845 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ 4846 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ 4847 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ 4848 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ 4849 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ 4850 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ 4851 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ 4852 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ 4853 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ 4854 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ 4855 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ 4856 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ 4857 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ 4858 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ 4859 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ 4860 4861 /*!< I2S configuration */ 4862 #define RCC_CFGR_I2SSRC_Pos (23U) 4863 #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */ 4864 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk /*!< I2S external clock source selection */ 4865 4866 #define RCC_CFGR_I2SSRC_SYSCLK (0x00000000U) /*!< System clock selected as I2S clock source */ 4867 #define RCC_CFGR_I2SSRC_EXT (0x00800000U) /*!< External clock selected as I2S clock source */ 4868 4869 /*!< MCO configuration */ 4870 #define RCC_CFGR_MCO_Pos (24U) 4871 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ 4872 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 4873 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 4874 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 4875 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 4876 4877 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ 4878 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ 4879 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ 4880 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ 4881 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ 4882 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ 4883 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ 4884 4885 #define RCC_CFGR_MCOPRE_Pos (28U) 4886 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4887 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */ 4888 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4889 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4890 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4891 4892 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 4893 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 4894 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 4895 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 4896 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 4897 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */ 4898 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */ 4899 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */ 4900 4901 #define RCC_CFGR_PLLNODIV_Pos (31U) 4902 #define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */ 4903 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< Do not divide PLL to MCO */ 4904 4905 /* Reference defines */ 4906 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 4907 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 4908 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 4909 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 4910 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 4911 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI 4912 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE 4913 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 4914 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 4915 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 4916 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL 4917 4918 /********************* Bit definition for RCC_CIR register ********************/ 4919 #define RCC_CIR_LSIRDYF_Pos (0U) 4920 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 4921 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 4922 #define RCC_CIR_LSERDYF_Pos (1U) 4923 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 4924 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 4925 #define RCC_CIR_HSIRDYF_Pos (2U) 4926 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 4927 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 4928 #define RCC_CIR_HSERDYF_Pos (3U) 4929 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 4930 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 4931 #define RCC_CIR_PLLRDYF_Pos (4U) 4932 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 4933 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 4934 #define RCC_CIR_CSSF_Pos (7U) 4935 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 4936 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 4937 #define RCC_CIR_LSIRDYIE_Pos (8U) 4938 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 4939 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 4940 #define RCC_CIR_LSERDYIE_Pos (9U) 4941 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 4942 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 4943 #define RCC_CIR_HSIRDYIE_Pos (10U) 4944 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 4945 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 4946 #define RCC_CIR_HSERDYIE_Pos (11U) 4947 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 4948 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 4949 #define RCC_CIR_PLLRDYIE_Pos (12U) 4950 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 4951 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 4952 #define RCC_CIR_LSIRDYC_Pos (16U) 4953 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 4954 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 4955 #define RCC_CIR_LSERDYC_Pos (17U) 4956 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 4957 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 4958 #define RCC_CIR_HSIRDYC_Pos (18U) 4959 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 4960 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 4961 #define RCC_CIR_HSERDYC_Pos (19U) 4962 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 4963 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 4964 #define RCC_CIR_PLLRDYC_Pos (20U) 4965 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 4966 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 4967 #define RCC_CIR_CSSC_Pos (23U) 4968 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 4969 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 4970 4971 /****************** Bit definition for RCC_APB2RSTR register *****************/ 4972 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 4973 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 4974 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 4975 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 4976 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 4977 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ 4978 #define RCC_APB2RSTR_USART1RST_Pos (14U) 4979 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 4980 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 4981 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 4982 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 4983 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ 4984 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 4985 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 4986 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ 4987 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 4988 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 4989 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ 4990 4991 /****************** Bit definition for RCC_APB1RSTR register ******************/ 4992 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 4993 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 4994 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 4995 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 4996 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 4997 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 4998 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 4999 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 5000 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 5001 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 5002 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 5003 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ 5004 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 5005 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ 5006 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI3 reset */ 5007 #define RCC_APB1RSTR_USART2RST_Pos (17U) 5008 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 5009 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 5010 #define RCC_APB1RSTR_USART3RST_Pos (18U) 5011 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 5012 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 5013 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 5014 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 5015 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 5016 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 5017 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 5018 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 5019 #define RCC_APB1RSTR_PWRRST_Pos (28U) 5020 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 5021 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 5022 #define RCC_APB1RSTR_DAC1RST_Pos (29U) 5023 #define RCC_APB1RSTR_DAC1RST_Msk (0x1UL << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */ 5024 #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */ 5025 #define RCC_APB1RSTR_I2C3RST_Pos (30U) 5026 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */ 5027 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 reset */ 5028 5029 /****************** Bit definition for RCC_AHBENR register ******************/ 5030 #define RCC_AHBENR_DMA1EN_Pos (0U) 5031 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 5032 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 5033 #define RCC_AHBENR_SRAMEN_Pos (2U) 5034 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 5035 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 5036 #define RCC_AHBENR_FLITFEN_Pos (4U) 5037 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 5038 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 5039 #define RCC_AHBENR_CRCEN_Pos (6U) 5040 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 5041 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 5042 #define RCC_AHBENR_GPIOAEN_Pos (17U) 5043 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ 5044 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ 5045 #define RCC_AHBENR_GPIOBEN_Pos (18U) 5046 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ 5047 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ 5048 #define RCC_AHBENR_GPIOCEN_Pos (19U) 5049 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ 5050 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ 5051 #define RCC_AHBENR_GPIODEN_Pos (20U) 5052 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ 5053 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ 5054 #define RCC_AHBENR_GPIOFEN_Pos (22U) 5055 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ 5056 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ 5057 #define RCC_AHBENR_TSCEN_Pos (24U) 5058 #define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */ 5059 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */ 5060 #define RCC_AHBENR_ADC1EN_Pos (28U) 5061 #define RCC_AHBENR_ADC1EN_Msk (0x1UL << RCC_AHBENR_ADC1EN_Pos) /*!< 0x10000000 */ 5062 #define RCC_AHBENR_ADC1EN RCC_AHBENR_ADC1EN_Msk /*!< ADC1 clock enable */ 5063 5064 /***************** Bit definition for RCC_APB2ENR register ******************/ 5065 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 5066 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 5067 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ 5068 #define RCC_APB2ENR_TIM1EN_Pos (11U) 5069 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 5070 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ 5071 #define RCC_APB2ENR_USART1EN_Pos (14U) 5072 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 5073 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 5074 #define RCC_APB2ENR_TIM15EN_Pos (16U) 5075 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 5076 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ 5077 #define RCC_APB2ENR_TIM16EN_Pos (17U) 5078 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 5079 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ 5080 #define RCC_APB2ENR_TIM17EN_Pos (18U) 5081 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 5082 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ 5083 5084 /****************** Bit definition for RCC_APB1ENR register ******************/ 5085 #define RCC_APB1ENR_TIM2EN_Pos (0U) 5086 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 5087 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 5088 #define RCC_APB1ENR_TIM6EN_Pos (4U) 5089 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 5090 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 5091 #define RCC_APB1ENR_WWDGEN_Pos (11U) 5092 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 5093 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 5094 #define RCC_APB1ENR_SPI2EN_Pos (14U) 5095 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 5096 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 5097 #define RCC_APB1ENR_SPI3EN_Pos (15U) 5098 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ 5099 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI3 clock enable */ 5100 #define RCC_APB1ENR_USART2EN_Pos (17U) 5101 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 5102 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 5103 #define RCC_APB1ENR_USART3EN_Pos (18U) 5104 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 5105 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 5106 #define RCC_APB1ENR_I2C1EN_Pos (21U) 5107 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 5108 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 5109 #define RCC_APB1ENR_I2C2EN_Pos (22U) 5110 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 5111 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 5112 #define RCC_APB1ENR_PWREN_Pos (28U) 5113 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 5114 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 5115 #define RCC_APB1ENR_DAC1EN_Pos (29U) 5116 #define RCC_APB1ENR_DAC1EN_Msk (0x1UL << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */ 5117 #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */ 5118 #define RCC_APB1ENR_I2C3EN_Pos (30U) 5119 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */ 5120 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock enable */ 5121 5122 /******************** Bit definition for RCC_BDCR register ******************/ 5123 #define RCC_BDCR_LSE_Pos (0U) 5124 #define RCC_BDCR_LSE_Msk (0x7UL << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */ 5125 #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */ 5126 #define RCC_BDCR_LSEON_Pos (0U) 5127 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 5128 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 5129 #define RCC_BDCR_LSERDY_Pos (1U) 5130 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 5131 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 5132 #define RCC_BDCR_LSEBYP_Pos (2U) 5133 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 5134 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 5135 5136 #define RCC_BDCR_LSEDRV_Pos (3U) 5137 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 5138 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 5139 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 5140 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 5141 5142 #define RCC_BDCR_RTCSEL_Pos (8U) 5143 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 5144 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 5145 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 5146 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 5147 5148 /*!< RTC configuration */ 5149 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 5150 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ 5151 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ 5152 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */ 5153 5154 #define RCC_BDCR_RTCEN_Pos (15U) 5155 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 5156 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 5157 #define RCC_BDCR_BDRST_Pos (16U) 5158 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 5159 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 5160 5161 /******************** Bit definition for RCC_CSR register *******************/ 5162 #define RCC_CSR_LSION_Pos (0U) 5163 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 5164 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 5165 #define RCC_CSR_LSIRDY_Pos (1U) 5166 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 5167 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 5168 #define RCC_CSR_V18PWRRSTF_Pos (23U) 5169 #define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */ 5170 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */ 5171 #define RCC_CSR_RMVF_Pos (24U) 5172 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 5173 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 5174 #define RCC_CSR_OBLRSTF_Pos (25U) 5175 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 5176 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 5177 #define RCC_CSR_PINRSTF_Pos (26U) 5178 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 5179 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 5180 #define RCC_CSR_PORRSTF_Pos (27U) 5181 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 5182 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 5183 #define RCC_CSR_SFTRSTF_Pos (28U) 5184 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 5185 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 5186 #define RCC_CSR_IWDGRSTF_Pos (29U) 5187 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 5188 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 5189 #define RCC_CSR_WWDGRSTF_Pos (30U) 5190 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 5191 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 5192 #define RCC_CSR_LPWRRSTF_Pos (31U) 5193 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 5194 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 5195 5196 /******************* Bit definition for RCC_AHBRSTR register ****************/ 5197 #define RCC_AHBRSTR_GPIOARST_Pos (17U) 5198 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ 5199 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ 5200 #define RCC_AHBRSTR_GPIOBRST_Pos (18U) 5201 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ 5202 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ 5203 #define RCC_AHBRSTR_GPIOCRST_Pos (19U) 5204 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ 5205 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ 5206 #define RCC_AHBRSTR_GPIODRST_Pos (20U) 5207 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ 5208 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ 5209 #define RCC_AHBRSTR_GPIOFRST_Pos (22U) 5210 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ 5211 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ 5212 #define RCC_AHBRSTR_TSCRST_Pos (24U) 5213 #define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ 5214 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ 5215 #define RCC_AHBRSTR_ADC1RST_Pos (28U) 5216 #define RCC_AHBRSTR_ADC1RST_Msk (0x1UL << RCC_AHBRSTR_ADC1RST_Pos) /*!< 0x10000000 */ 5217 #define RCC_AHBRSTR_ADC1RST RCC_AHBRSTR_ADC1RST_Msk /*!< ADC1 reset */ 5218 5219 /******************* Bit definition for RCC_CFGR2 register ******************/ 5220 /*!< PREDIV configuration */ 5221 #define RCC_CFGR2_PREDIV_Pos (0U) 5222 #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ 5223 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ 5224 #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ 5225 #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ 5226 #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ 5227 #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ 5228 5229 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ 5230 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ 5231 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ 5232 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ 5233 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ 5234 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ 5235 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ 5236 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ 5237 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ 5238 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ 5239 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ 5240 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ 5241 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ 5242 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ 5243 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ 5244 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ 5245 5246 /*!< ADC1PRES configuration */ 5247 #define RCC_CFGR2_ADC1PRES_Pos (4U) 5248 #define RCC_CFGR2_ADC1PRES_Msk (0x1FUL << RCC_CFGR2_ADC1PRES_Pos) /*!< 0x000001F0 */ 5249 #define RCC_CFGR2_ADC1PRES RCC_CFGR2_ADC1PRES_Msk /*!< ADC1PRES[8:4] bits */ 5250 #define RCC_CFGR2_ADC1PRES_0 (0x01UL << RCC_CFGR2_ADC1PRES_Pos) /*!< 0x00000010 */ 5251 #define RCC_CFGR2_ADC1PRES_1 (0x02UL << RCC_CFGR2_ADC1PRES_Pos) /*!< 0x00000020 */ 5252 #define RCC_CFGR2_ADC1PRES_2 (0x04UL << RCC_CFGR2_ADC1PRES_Pos) /*!< 0x00000040 */ 5253 #define RCC_CFGR2_ADC1PRES_3 (0x08UL << RCC_CFGR2_ADC1PRES_Pos) /*!< 0x00000080 */ 5254 #define RCC_CFGR2_ADC1PRES_4 (0x10UL << RCC_CFGR2_ADC1PRES_Pos) /*!< 0x00000100 */ 5255 5256 #define RCC_CFGR2_ADC1PRES_NO (0x00000000U) /*!< ADC1 clock disabled, ADC1 can use AHB clock */ 5257 #define RCC_CFGR2_ADC1PRES_DIV1 (0x00000100U) /*!< ADC1 PLL clock divided by 1 */ 5258 #define RCC_CFGR2_ADC1PRES_DIV2 (0x00000110U) /*!< ADC1 PLL clock divided by 2 */ 5259 #define RCC_CFGR2_ADC1PRES_DIV4 (0x00000120U) /*!< ADC1 PLL clock divided by 4 */ 5260 #define RCC_CFGR2_ADC1PRES_DIV6 (0x00000130U) /*!< ADC1 PLL clock divided by 6 */ 5261 #define RCC_CFGR2_ADC1PRES_DIV8 (0x00000140U) /*!< ADC1 PLL clock divided by 8 */ 5262 #define RCC_CFGR2_ADC1PRES_DIV10 (0x00000150U) /*!< ADC1 PLL clock divided by 10 */ 5263 #define RCC_CFGR2_ADC1PRES_DIV12 (0x00000160U) /*!< ADC1 PLL clock divided by 12 */ 5264 #define RCC_CFGR2_ADC1PRES_DIV16 (0x00000170U) /*!< ADC1 PLL clock divided by 16 */ 5265 #define RCC_CFGR2_ADC1PRES_DIV32 (0x00000180U) /*!< ADC1 PLL clock divided by 32 */ 5266 #define RCC_CFGR2_ADC1PRES_DIV64 (0x00000190U) /*!< ADC1 PLL clock divided by 64 */ 5267 #define RCC_CFGR2_ADC1PRES_DIV128 (0x000001A0U) /*!< ADC1 PLL clock divided by 128 */ 5268 #define RCC_CFGR2_ADC1PRES_DIV256 (0x000001B0U) /*!< ADC1 PLL clock divided by 256 */ 5269 5270 /******************* Bit definition for RCC_CFGR3 register ******************/ 5271 #define RCC_CFGR3_USART1SW_Pos (0U) 5272 #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ 5273 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ 5274 #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ 5275 #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ 5276 5277 #define RCC_CFGR3_USART1SW_PCLK1 (0x00000000U) /*!< PCLK1 clock used as USART1 clock source */ 5278 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ 5279 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ 5280 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ 5281 /* Legacy defines */ 5282 #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1 5283 5284 #define RCC_CFGR3_I2CSW_Pos (4U) 5285 #define RCC_CFGR3_I2CSW_Msk (0x7UL << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000070 */ 5286 #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */ 5287 #define RCC_CFGR3_I2C1SW_Pos (4U) 5288 #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ 5289 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ 5290 #define RCC_CFGR3_I2C2SW_Pos (5U) 5291 #define RCC_CFGR3_I2C2SW_Msk (0x1UL << RCC_CFGR3_I2C2SW_Pos) /*!< 0x00000020 */ 5292 #define RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk /*!< I2C2SW bits */ 5293 #define RCC_CFGR3_I2C3SW_Pos (6U) 5294 #define RCC_CFGR3_I2C3SW_Msk (0x1UL << RCC_CFGR3_I2C3SW_Pos) /*!< 0x00000040 */ 5295 #define RCC_CFGR3_I2C3SW RCC_CFGR3_I2C3SW_Msk /*!< I2C3SW bits */ 5296 5297 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ 5298 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) 5299 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ 5300 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ 5301 #define RCC_CFGR3_I2C2SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C2 clock source */ 5302 #define RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U) 5303 #define RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C2SW_SYSCLK_Pos) /*!< 0x00000020 */ 5304 #define RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk /*!< System clock selected as I2C2 clock source */ 5305 #define RCC_CFGR3_I2C3SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C3 clock source */ 5306 #define RCC_CFGR3_I2C3SW_SYSCLK_Pos (6U) 5307 #define RCC_CFGR3_I2C3SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C3SW_SYSCLK_Pos) /*!< 0x00000040 */ 5308 #define RCC_CFGR3_I2C3SW_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK_Msk /*!< System clock selected as I2C3 clock source */ 5309 5310 #define RCC_CFGR3_TIMSW_Pos (8U) 5311 #define RCC_CFGR3_TIMSW_Msk (0x2DUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00002D00 */ 5312 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */ 5313 #define RCC_CFGR3_TIM1SW_Pos (8U) 5314 #define RCC_CFGR3_TIM1SW_Msk (0x1UL << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */ 5315 #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */ 5316 #define RCC_CFGR3_TIM15SW_Pos (10U) 5317 #define RCC_CFGR3_TIM15SW_Msk (0x1UL << RCC_CFGR3_TIM15SW_Pos) /*!< 0x00000400 */ 5318 #define RCC_CFGR3_TIM15SW RCC_CFGR3_TIM15SW_Msk /*!< TIM15SW bits */ 5319 #define RCC_CFGR3_TIM16SW_Pos (11U) 5320 #define RCC_CFGR3_TIM16SW_Msk (0x1UL << RCC_CFGR3_TIM16SW_Pos) /*!< 0x00000800 */ 5321 #define RCC_CFGR3_TIM16SW RCC_CFGR3_TIM16SW_Msk /*!< TIM16SW bits */ 5322 #define RCC_CFGR3_TIM17SW_Pos (13U) 5323 #define RCC_CFGR3_TIM17SW_Msk (0x1UL << RCC_CFGR3_TIM17SW_Pos) /*!< 0x00002000 */ 5324 #define RCC_CFGR3_TIM17SW RCC_CFGR3_TIM17SW_Msk /*!< TIM17SW bits */ 5325 #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */ 5326 #define RCC_CFGR3_TIM1SW_PLL_Pos (8U) 5327 #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */ 5328 #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */ 5329 #define RCC_CFGR3_TIM15SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM15 clock source */ 5330 #define RCC_CFGR3_TIM15SW_PLL_Pos (10U) 5331 #define RCC_CFGR3_TIM15SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM15SW_PLL_Pos) /*!< 0x00000400 */ 5332 #define RCC_CFGR3_TIM15SW_PLL RCC_CFGR3_TIM15SW_PLL_Msk /*!< PLL clock used as TIM15 clock source */ 5333 #define RCC_CFGR3_TIM16SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM16 clock source */ 5334 #define RCC_CFGR3_TIM16SW_PLL_Pos (11U) 5335 #define RCC_CFGR3_TIM16SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM16SW_PLL_Pos) /*!< 0x00000800 */ 5336 #define RCC_CFGR3_TIM16SW_PLL RCC_CFGR3_TIM16SW_PLL_Msk /*!< PLL clock used as TIM16 clock source */ 5337 #define RCC_CFGR3_TIM17SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM17 clock source */ 5338 #define RCC_CFGR3_TIM17SW_PLL_Pos (13U) 5339 #define RCC_CFGR3_TIM17SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM17SW_PLL_Pos) /*!< 0x00002000 */ 5340 #define RCC_CFGR3_TIM17SW_PLL RCC_CFGR3_TIM17SW_PLL_Msk /*!< PLL clock used as TIM17 clock source */ 5341 5342 /* Legacy defines */ 5343 #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2 5344 #define RCC_CFGR3_TIM15SW_HCLK RCC_CFGR3_TIM15SW_PCLK2 5345 #define RCC_CFGR3_TIM16SW_HCLK RCC_CFGR3_TIM16SW_PCLK2 5346 #define RCC_CFGR3_TIM17SW_HCLK RCC_CFGR3_TIM17SW_PCLK2 5347 5348 /******************************************************************************/ 5349 /* */ 5350 /* Real-Time Clock (RTC) */ 5351 /* */ 5352 /******************************************************************************/ 5353 /* 5354 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 5355 */ 5356 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 5357 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 5358 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 5359 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 5360 5361 /******************** Bits definition for RTC_TR register *******************/ 5362 #define RTC_TR_PM_Pos (22U) 5363 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 5364 #define RTC_TR_PM RTC_TR_PM_Msk 5365 #define RTC_TR_HT_Pos (20U) 5366 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 5367 #define RTC_TR_HT RTC_TR_HT_Msk 5368 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 5369 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 5370 #define RTC_TR_HU_Pos (16U) 5371 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 5372 #define RTC_TR_HU RTC_TR_HU_Msk 5373 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 5374 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 5375 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 5376 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 5377 #define RTC_TR_MNT_Pos (12U) 5378 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 5379 #define RTC_TR_MNT RTC_TR_MNT_Msk 5380 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 5381 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 5382 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 5383 #define RTC_TR_MNU_Pos (8U) 5384 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 5385 #define RTC_TR_MNU RTC_TR_MNU_Msk 5386 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 5387 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 5388 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 5389 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 5390 #define RTC_TR_ST_Pos (4U) 5391 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 5392 #define RTC_TR_ST RTC_TR_ST_Msk 5393 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 5394 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 5395 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 5396 #define RTC_TR_SU_Pos (0U) 5397 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 5398 #define RTC_TR_SU RTC_TR_SU_Msk 5399 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 5400 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 5401 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 5402 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 5403 5404 /******************** Bits definition for RTC_DR register *******************/ 5405 #define RTC_DR_YT_Pos (20U) 5406 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 5407 #define RTC_DR_YT RTC_DR_YT_Msk 5408 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 5409 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 5410 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 5411 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 5412 #define RTC_DR_YU_Pos (16U) 5413 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 5414 #define RTC_DR_YU RTC_DR_YU_Msk 5415 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 5416 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 5417 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 5418 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 5419 #define RTC_DR_WDU_Pos (13U) 5420 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 5421 #define RTC_DR_WDU RTC_DR_WDU_Msk 5422 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 5423 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 5424 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 5425 #define RTC_DR_MT_Pos (12U) 5426 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 5427 #define RTC_DR_MT RTC_DR_MT_Msk 5428 #define RTC_DR_MU_Pos (8U) 5429 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 5430 #define RTC_DR_MU RTC_DR_MU_Msk 5431 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 5432 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 5433 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 5434 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 5435 #define RTC_DR_DT_Pos (4U) 5436 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 5437 #define RTC_DR_DT RTC_DR_DT_Msk 5438 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 5439 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 5440 #define RTC_DR_DU_Pos (0U) 5441 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 5442 #define RTC_DR_DU RTC_DR_DU_Msk 5443 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 5444 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 5445 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 5446 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 5447 5448 /******************** Bits definition for RTC_CR register *******************/ 5449 #define RTC_CR_COE_Pos (23U) 5450 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 5451 #define RTC_CR_COE RTC_CR_COE_Msk 5452 #define RTC_CR_OSEL_Pos (21U) 5453 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 5454 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 5455 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 5456 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 5457 #define RTC_CR_POL_Pos (20U) 5458 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 5459 #define RTC_CR_POL RTC_CR_POL_Msk 5460 #define RTC_CR_COSEL_Pos (19U) 5461 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 5462 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 5463 #define RTC_CR_BKP_Pos (18U) 5464 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 5465 #define RTC_CR_BKP RTC_CR_BKP_Msk 5466 #define RTC_CR_SUB1H_Pos (17U) 5467 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 5468 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 5469 #define RTC_CR_ADD1H_Pos (16U) 5470 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 5471 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 5472 #define RTC_CR_TSIE_Pos (15U) 5473 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 5474 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 5475 #define RTC_CR_WUTIE_Pos (14U) 5476 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 5477 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 5478 #define RTC_CR_ALRBIE_Pos (13U) 5479 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 5480 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 5481 #define RTC_CR_ALRAIE_Pos (12U) 5482 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 5483 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 5484 #define RTC_CR_TSE_Pos (11U) 5485 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 5486 #define RTC_CR_TSE RTC_CR_TSE_Msk 5487 #define RTC_CR_WUTE_Pos (10U) 5488 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 5489 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 5490 #define RTC_CR_ALRBE_Pos (9U) 5491 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 5492 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 5493 #define RTC_CR_ALRAE_Pos (8U) 5494 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 5495 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 5496 #define RTC_CR_FMT_Pos (6U) 5497 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 5498 #define RTC_CR_FMT RTC_CR_FMT_Msk 5499 #define RTC_CR_BYPSHAD_Pos (5U) 5500 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 5501 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 5502 #define RTC_CR_REFCKON_Pos (4U) 5503 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 5504 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 5505 #define RTC_CR_TSEDGE_Pos (3U) 5506 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 5507 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 5508 #define RTC_CR_WUCKSEL_Pos (0U) 5509 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 5510 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 5511 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 5512 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 5513 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 5514 5515 /* Legacy defines */ 5516 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 5517 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 5518 #define RTC_CR_BCK RTC_CR_BKP 5519 5520 /******************** Bits definition for RTC_ISR register ******************/ 5521 #define RTC_ISR_RECALPF_Pos (16U) 5522 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 5523 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 5524 #define RTC_ISR_TAMP2F_Pos (14U) 5525 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 5526 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 5527 #define RTC_ISR_TAMP1F_Pos (13U) 5528 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 5529 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 5530 #define RTC_ISR_TSOVF_Pos (12U) 5531 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 5532 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 5533 #define RTC_ISR_TSF_Pos (11U) 5534 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 5535 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 5536 #define RTC_ISR_WUTF_Pos (10U) 5537 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 5538 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 5539 #define RTC_ISR_ALRBF_Pos (9U) 5540 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 5541 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 5542 #define RTC_ISR_ALRAF_Pos (8U) 5543 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 5544 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 5545 #define RTC_ISR_INIT_Pos (7U) 5546 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 5547 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 5548 #define RTC_ISR_INITF_Pos (6U) 5549 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 5550 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 5551 #define RTC_ISR_RSF_Pos (5U) 5552 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 5553 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 5554 #define RTC_ISR_INITS_Pos (4U) 5555 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 5556 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 5557 #define RTC_ISR_SHPF_Pos (3U) 5558 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 5559 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 5560 #define RTC_ISR_WUTWF_Pos (2U) 5561 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 5562 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 5563 #define RTC_ISR_ALRBWF_Pos (1U) 5564 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 5565 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 5566 #define RTC_ISR_ALRAWF_Pos (0U) 5567 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 5568 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 5569 5570 /******************** Bits definition for RTC_PRER register *****************/ 5571 #define RTC_PRER_PREDIV_A_Pos (16U) 5572 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 5573 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 5574 #define RTC_PRER_PREDIV_S_Pos (0U) 5575 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 5576 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 5577 5578 /******************** Bits definition for RTC_WUTR register *****************/ 5579 #define RTC_WUTR_WUT_Pos (0U) 5580 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 5581 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 5582 5583 /******************** Bits definition for RTC_ALRMAR register ***************/ 5584 #define RTC_ALRMAR_MSK4_Pos (31U) 5585 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 5586 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 5587 #define RTC_ALRMAR_WDSEL_Pos (30U) 5588 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 5589 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 5590 #define RTC_ALRMAR_DT_Pos (28U) 5591 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 5592 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 5593 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 5594 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 5595 #define RTC_ALRMAR_DU_Pos (24U) 5596 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 5597 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 5598 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 5599 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 5600 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 5601 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 5602 #define RTC_ALRMAR_MSK3_Pos (23U) 5603 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 5604 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 5605 #define RTC_ALRMAR_PM_Pos (22U) 5606 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 5607 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 5608 #define RTC_ALRMAR_HT_Pos (20U) 5609 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 5610 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 5611 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 5612 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 5613 #define RTC_ALRMAR_HU_Pos (16U) 5614 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 5615 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 5616 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 5617 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 5618 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 5619 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 5620 #define RTC_ALRMAR_MSK2_Pos (15U) 5621 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 5622 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 5623 #define RTC_ALRMAR_MNT_Pos (12U) 5624 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 5625 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 5626 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 5627 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 5628 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 5629 #define RTC_ALRMAR_MNU_Pos (8U) 5630 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 5631 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 5632 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 5633 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 5634 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 5635 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 5636 #define RTC_ALRMAR_MSK1_Pos (7U) 5637 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 5638 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 5639 #define RTC_ALRMAR_ST_Pos (4U) 5640 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 5641 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 5642 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 5643 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 5644 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 5645 #define RTC_ALRMAR_SU_Pos (0U) 5646 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 5647 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 5648 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 5649 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 5650 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 5651 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 5652 5653 /******************** Bits definition for RTC_ALRMBR register ***************/ 5654 #define RTC_ALRMBR_MSK4_Pos (31U) 5655 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 5656 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 5657 #define RTC_ALRMBR_WDSEL_Pos (30U) 5658 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 5659 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 5660 #define RTC_ALRMBR_DT_Pos (28U) 5661 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 5662 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 5663 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 5664 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 5665 #define RTC_ALRMBR_DU_Pos (24U) 5666 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 5667 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 5668 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 5669 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 5670 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 5671 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 5672 #define RTC_ALRMBR_MSK3_Pos (23U) 5673 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 5674 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 5675 #define RTC_ALRMBR_PM_Pos (22U) 5676 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 5677 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 5678 #define RTC_ALRMBR_HT_Pos (20U) 5679 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 5680 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 5681 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 5682 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 5683 #define RTC_ALRMBR_HU_Pos (16U) 5684 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 5685 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 5686 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 5687 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 5688 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 5689 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 5690 #define RTC_ALRMBR_MSK2_Pos (15U) 5691 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 5692 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 5693 #define RTC_ALRMBR_MNT_Pos (12U) 5694 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 5695 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 5696 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 5697 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 5698 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 5699 #define RTC_ALRMBR_MNU_Pos (8U) 5700 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 5701 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 5702 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 5703 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 5704 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 5705 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 5706 #define RTC_ALRMBR_MSK1_Pos (7U) 5707 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 5708 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 5709 #define RTC_ALRMBR_ST_Pos (4U) 5710 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 5711 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 5712 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 5713 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 5714 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 5715 #define RTC_ALRMBR_SU_Pos (0U) 5716 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 5717 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 5718 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 5719 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 5720 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 5721 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 5722 5723 /******************** Bits definition for RTC_WPR register ******************/ 5724 #define RTC_WPR_KEY_Pos (0U) 5725 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 5726 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 5727 5728 /******************** Bits definition for RTC_SSR register ******************/ 5729 #define RTC_SSR_SS_Pos (0U) 5730 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 5731 #define RTC_SSR_SS RTC_SSR_SS_Msk 5732 5733 /******************** Bits definition for RTC_SHIFTR register ***************/ 5734 #define RTC_SHIFTR_SUBFS_Pos (0U) 5735 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 5736 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 5737 #define RTC_SHIFTR_ADD1S_Pos (31U) 5738 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 5739 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 5740 5741 /******************** Bits definition for RTC_TSTR register *****************/ 5742 #define RTC_TSTR_PM_Pos (22U) 5743 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 5744 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 5745 #define RTC_TSTR_HT_Pos (20U) 5746 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 5747 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 5748 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 5749 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 5750 #define RTC_TSTR_HU_Pos (16U) 5751 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 5752 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 5753 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 5754 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 5755 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 5756 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 5757 #define RTC_TSTR_MNT_Pos (12U) 5758 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 5759 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 5760 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 5761 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 5762 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 5763 #define RTC_TSTR_MNU_Pos (8U) 5764 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 5765 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 5766 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 5767 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 5768 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 5769 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 5770 #define RTC_TSTR_ST_Pos (4U) 5771 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 5772 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 5773 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 5774 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 5775 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 5776 #define RTC_TSTR_SU_Pos (0U) 5777 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 5778 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 5779 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 5780 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 5781 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 5782 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 5783 5784 /******************** Bits definition for RTC_TSDR register *****************/ 5785 #define RTC_TSDR_WDU_Pos (13U) 5786 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 5787 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 5788 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 5789 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 5790 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 5791 #define RTC_TSDR_MT_Pos (12U) 5792 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 5793 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 5794 #define RTC_TSDR_MU_Pos (8U) 5795 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 5796 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 5797 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 5798 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 5799 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 5800 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 5801 #define RTC_TSDR_DT_Pos (4U) 5802 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 5803 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 5804 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 5805 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 5806 #define RTC_TSDR_DU_Pos (0U) 5807 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 5808 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 5809 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 5810 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 5811 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 5812 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 5813 5814 /******************** Bits definition for RTC_TSSSR register ****************/ 5815 #define RTC_TSSSR_SS_Pos (0U) 5816 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 5817 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 5818 5819 /******************** Bits definition for RTC_CAL register *****************/ 5820 #define RTC_CALR_CALP_Pos (15U) 5821 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 5822 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 5823 #define RTC_CALR_CALW8_Pos (14U) 5824 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 5825 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 5826 #define RTC_CALR_CALW16_Pos (13U) 5827 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 5828 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 5829 #define RTC_CALR_CALM_Pos (0U) 5830 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 5831 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 5832 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 5833 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 5834 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 5835 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 5836 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 5837 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 5838 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 5839 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 5840 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 5841 5842 /******************** Bits definition for RTC_TAFCR register ****************/ 5843 #define RTC_TAFCR_PC15MODE_Pos (23U) 5844 #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ 5845 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk 5846 #define RTC_TAFCR_PC15VALUE_Pos (22U) 5847 #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ 5848 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk 5849 #define RTC_TAFCR_PC14MODE_Pos (21U) 5850 #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ 5851 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk 5852 #define RTC_TAFCR_PC14VALUE_Pos (20U) 5853 #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ 5854 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk 5855 #define RTC_TAFCR_PC13MODE_Pos (19U) 5856 #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ 5857 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk 5858 #define RTC_TAFCR_PC13VALUE_Pos (18U) 5859 #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ 5860 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk 5861 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 5862 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 5863 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 5864 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 5865 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 5866 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 5867 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 5868 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 5869 #define RTC_TAFCR_TAMPFLT_Pos (11U) 5870 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 5871 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 5872 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 5873 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 5874 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 5875 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 5876 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 5877 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 5878 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 5879 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 5880 #define RTC_TAFCR_TAMPTS_Pos (7U) 5881 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 5882 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 5883 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 5884 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 5885 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 5886 #define RTC_TAFCR_TAMP2E_Pos (3U) 5887 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 5888 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 5889 #define RTC_TAFCR_TAMPIE_Pos (2U) 5890 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 5891 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 5892 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 5893 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 5894 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 5895 #define RTC_TAFCR_TAMP1E_Pos (0U) 5896 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 5897 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 5898 5899 /* Reference defines */ 5900 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 5901 5902 /******************** Bits definition for RTC_ALRMASSR register *************/ 5903 #define RTC_ALRMASSR_MASKSS_Pos (24U) 5904 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 5905 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 5906 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 5907 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 5908 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 5909 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 5910 #define RTC_ALRMASSR_SS_Pos (0U) 5911 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 5912 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 5913 5914 /******************** Bits definition for RTC_ALRMBSSR register *************/ 5915 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 5916 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 5917 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 5918 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 5919 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 5920 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 5921 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 5922 #define RTC_ALRMBSSR_SS_Pos (0U) 5923 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 5924 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 5925 5926 /******************** Bits definition for RTC_BKP0R register ****************/ 5927 #define RTC_BKP0R_Pos (0U) 5928 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 5929 #define RTC_BKP0R RTC_BKP0R_Msk 5930 5931 /******************** Bits definition for RTC_BKP1R register ****************/ 5932 #define RTC_BKP1R_Pos (0U) 5933 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 5934 #define RTC_BKP1R RTC_BKP1R_Msk 5935 5936 /******************** Bits definition for RTC_BKP2R register ****************/ 5937 #define RTC_BKP2R_Pos (0U) 5938 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 5939 #define RTC_BKP2R RTC_BKP2R_Msk 5940 5941 /******************** Bits definition for RTC_BKP3R register ****************/ 5942 #define RTC_BKP3R_Pos (0U) 5943 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 5944 #define RTC_BKP3R RTC_BKP3R_Msk 5945 5946 /******************** Bits definition for RTC_BKP4R register ****************/ 5947 #define RTC_BKP4R_Pos (0U) 5948 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 5949 #define RTC_BKP4R RTC_BKP4R_Msk 5950 5951 /******************** Bits definition for RTC_BKP5R register ****************/ 5952 #define RTC_BKP5R_Pos (0U) 5953 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 5954 #define RTC_BKP5R RTC_BKP5R_Msk 5955 5956 /******************** Bits definition for RTC_BKP6R register ****************/ 5957 #define RTC_BKP6R_Pos (0U) 5958 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 5959 #define RTC_BKP6R RTC_BKP6R_Msk 5960 5961 /******************** Bits definition for RTC_BKP7R register ****************/ 5962 #define RTC_BKP7R_Pos (0U) 5963 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 5964 #define RTC_BKP7R RTC_BKP7R_Msk 5965 5966 /******************** Bits definition for RTC_BKP8R register ****************/ 5967 #define RTC_BKP8R_Pos (0U) 5968 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 5969 #define RTC_BKP8R RTC_BKP8R_Msk 5970 5971 /******************** Bits definition for RTC_BKP9R register ****************/ 5972 #define RTC_BKP9R_Pos (0U) 5973 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 5974 #define RTC_BKP9R RTC_BKP9R_Msk 5975 5976 /******************** Bits definition for RTC_BKP10R register ***************/ 5977 #define RTC_BKP10R_Pos (0U) 5978 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 5979 #define RTC_BKP10R RTC_BKP10R_Msk 5980 5981 /******************** Bits definition for RTC_BKP11R register ***************/ 5982 #define RTC_BKP11R_Pos (0U) 5983 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 5984 #define RTC_BKP11R RTC_BKP11R_Msk 5985 5986 /******************** Bits definition for RTC_BKP12R register ***************/ 5987 #define RTC_BKP12R_Pos (0U) 5988 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 5989 #define RTC_BKP12R RTC_BKP12R_Msk 5990 5991 /******************** Bits definition for RTC_BKP13R register ***************/ 5992 #define RTC_BKP13R_Pos (0U) 5993 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 5994 #define RTC_BKP13R RTC_BKP13R_Msk 5995 5996 /******************** Bits definition for RTC_BKP14R register ***************/ 5997 #define RTC_BKP14R_Pos (0U) 5998 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 5999 #define RTC_BKP14R RTC_BKP14R_Msk 6000 6001 /******************** Bits definition for RTC_BKP15R register ***************/ 6002 #define RTC_BKP15R_Pos (0U) 6003 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 6004 #define RTC_BKP15R RTC_BKP15R_Msk 6005 6006 /******************** Bits definition for RTC_BKP16R register ***************/ 6007 #define RTC_BKP16R_Pos (0U) 6008 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 6009 #define RTC_BKP16R RTC_BKP16R_Msk 6010 6011 /******************** Bits definition for RTC_BKP17R register ***************/ 6012 #define RTC_BKP17R_Pos (0U) 6013 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 6014 #define RTC_BKP17R RTC_BKP17R_Msk 6015 6016 /******************** Bits definition for RTC_BKP18R register ***************/ 6017 #define RTC_BKP18R_Pos (0U) 6018 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 6019 #define RTC_BKP18R RTC_BKP18R_Msk 6020 6021 /******************** Bits definition for RTC_BKP19R register ***************/ 6022 #define RTC_BKP19R_Pos (0U) 6023 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 6024 #define RTC_BKP19R RTC_BKP19R_Msk 6025 6026 /******************** Number of backup registers ******************************/ 6027 #define RTC_BKP_NUMBER 20 6028 6029 /******************************************************************************/ 6030 /* */ 6031 /* Serial Peripheral Interface (SPI) */ 6032 /* */ 6033 /******************************************************************************/ 6034 6035 /* 6036 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 6037 */ 6038 #define SPI_I2S_SUPPORT /*!< I2S support */ 6039 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */ 6040 6041 /******************* Bit definition for SPI_CR1 register ********************/ 6042 #define SPI_CR1_CPHA_Pos (0U) 6043 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 6044 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 6045 #define SPI_CR1_CPOL_Pos (1U) 6046 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 6047 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 6048 #define SPI_CR1_MSTR_Pos (2U) 6049 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 6050 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 6051 #define SPI_CR1_BR_Pos (3U) 6052 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 6053 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 6054 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 6055 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 6056 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 6057 #define SPI_CR1_SPE_Pos (6U) 6058 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 6059 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 6060 #define SPI_CR1_LSBFIRST_Pos (7U) 6061 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 6062 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 6063 #define SPI_CR1_SSI_Pos (8U) 6064 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 6065 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 6066 #define SPI_CR1_SSM_Pos (9U) 6067 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 6068 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 6069 #define SPI_CR1_RXONLY_Pos (10U) 6070 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 6071 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 6072 #define SPI_CR1_CRCL_Pos (11U) 6073 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 6074 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 6075 #define SPI_CR1_CRCNEXT_Pos (12U) 6076 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 6077 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 6078 #define SPI_CR1_CRCEN_Pos (13U) 6079 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 6080 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 6081 #define SPI_CR1_BIDIOE_Pos (14U) 6082 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 6083 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 6084 #define SPI_CR1_BIDIMODE_Pos (15U) 6085 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 6086 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 6087 6088 /******************* Bit definition for SPI_CR2 register ********************/ 6089 #define SPI_CR2_RXDMAEN_Pos (0U) 6090 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 6091 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 6092 #define SPI_CR2_TXDMAEN_Pos (1U) 6093 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 6094 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 6095 #define SPI_CR2_SSOE_Pos (2U) 6096 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 6097 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 6098 #define SPI_CR2_NSSP_Pos (3U) 6099 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 6100 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 6101 #define SPI_CR2_FRF_Pos (4U) 6102 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 6103 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 6104 #define SPI_CR2_ERRIE_Pos (5U) 6105 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 6106 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 6107 #define SPI_CR2_RXNEIE_Pos (6U) 6108 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 6109 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 6110 #define SPI_CR2_TXEIE_Pos (7U) 6111 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 6112 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 6113 #define SPI_CR2_DS_Pos (8U) 6114 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 6115 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 6116 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 6117 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 6118 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 6119 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 6120 #define SPI_CR2_FRXTH_Pos (12U) 6121 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 6122 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 6123 #define SPI_CR2_LDMARX_Pos (13U) 6124 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 6125 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 6126 #define SPI_CR2_LDMATX_Pos (14U) 6127 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 6128 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 6129 6130 /******************** Bit definition for SPI_SR register ********************/ 6131 #define SPI_SR_RXNE_Pos (0U) 6132 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 6133 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 6134 #define SPI_SR_TXE_Pos (1U) 6135 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 6136 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 6137 #define SPI_SR_CHSIDE_Pos (2U) 6138 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 6139 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 6140 #define SPI_SR_UDR_Pos (3U) 6141 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 6142 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 6143 #define SPI_SR_CRCERR_Pos (4U) 6144 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 6145 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 6146 #define SPI_SR_MODF_Pos (5U) 6147 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 6148 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 6149 #define SPI_SR_OVR_Pos (6U) 6150 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 6151 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 6152 #define SPI_SR_BSY_Pos (7U) 6153 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 6154 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 6155 #define SPI_SR_FRE_Pos (8U) 6156 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 6157 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 6158 #define SPI_SR_FRLVL_Pos (9U) 6159 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 6160 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 6161 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 6162 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 6163 #define SPI_SR_FTLVL_Pos (11U) 6164 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 6165 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 6166 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 6167 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 6168 6169 /******************** Bit definition for SPI_DR register ********************/ 6170 #define SPI_DR_DR_Pos (0U) 6171 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 6172 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 6173 6174 /******************* Bit definition for SPI_CRCPR register ******************/ 6175 #define SPI_CRCPR_CRCPOLY_Pos (0U) 6176 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 6177 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 6178 6179 /****************** Bit definition for SPI_RXCRCR register ******************/ 6180 #define SPI_RXCRCR_RXCRC_Pos (0U) 6181 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 6182 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 6183 6184 /****************** Bit definition for SPI_TXCRCR register ******************/ 6185 #define SPI_TXCRCR_TXCRC_Pos (0U) 6186 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 6187 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 6188 6189 /****************** Bit definition for SPI_I2SCFGR register *****************/ 6190 #define SPI_I2SCFGR_CHLEN_Pos (0U) 6191 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 6192 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 6193 #define SPI_I2SCFGR_DATLEN_Pos (1U) 6194 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 6195 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 6196 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 6197 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 6198 #define SPI_I2SCFGR_CKPOL_Pos (3U) 6199 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 6200 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 6201 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 6202 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 6203 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 6204 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 6205 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 6206 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 6207 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 6208 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 6209 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 6210 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 6211 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 6212 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 6213 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 6214 #define SPI_I2SCFGR_I2SE_Pos (10U) 6215 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 6216 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 6217 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 6218 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 6219 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 6220 6221 /****************** Bit definition for SPI_I2SPR register *******************/ 6222 #define SPI_I2SPR_I2SDIV_Pos (0U) 6223 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 6224 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 6225 #define SPI_I2SPR_ODD_Pos (8U) 6226 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 6227 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 6228 #define SPI_I2SPR_MCKOE_Pos (9U) 6229 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 6230 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 6231 6232 /******************************************************************************/ 6233 /* */ 6234 /* System Configuration(SYSCFG) */ 6235 /* */ 6236 /******************************************************************************/ 6237 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 6238 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 6239 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 6240 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 6241 #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */ 6242 #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */ 6243 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U) 6244 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */ 6245 #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */ 6246 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U) 6247 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */ 6248 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */ 6249 #define SYSCFG_CFGR1_DMA_RMP_Pos (11U) 6250 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x7UL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00003800 */ 6251 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ 6252 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) 6253 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ 6254 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ 6255 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) 6256 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ 6257 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ 6258 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U) 6259 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */ 6260 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */ 6261 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 6262 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 6263 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 6264 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 6265 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 6266 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 6267 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 6268 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ 6269 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 6270 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 6271 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ 6272 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 6273 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 6274 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 6275 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 6276 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) 6277 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ 6278 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */ 6279 #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U) 6280 #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */ 6281 #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */ 6282 #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */ 6283 #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */ 6284 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U) 6285 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */ 6286 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 6287 #define SYSCFG_CFGR1_I2C3_FMP_Pos (24U) 6288 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x01000000 */ 6289 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */ 6290 #define SYSCFG_CFGR1_FPU_IE_Pos (26U) 6291 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */ 6292 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */ 6293 #define SYSCFG_CFGR1_FPU_IE_0 (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */ 6294 #define SYSCFG_CFGR1_FPU_IE_1 (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */ 6295 #define SYSCFG_CFGR1_FPU_IE_2 (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */ 6296 #define SYSCFG_CFGR1_FPU_IE_3 (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */ 6297 #define SYSCFG_CFGR1_FPU_IE_4 (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */ 6298 #define SYSCFG_CFGR1_FPU_IE_5 (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */ 6299 6300 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 6301 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 6302 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 6303 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 6304 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 6305 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 6306 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 6307 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 6308 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 6309 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 6310 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 6311 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 6312 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 6313 6314 /*!<* 6315 * @brief EXTI0 configuration 6316 */ 6317 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 6318 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 6319 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 6320 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 6321 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 6322 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ 6323 6324 /*!<* 6325 * @brief EXTI1 configuration 6326 */ 6327 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 6328 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 6329 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 6330 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 6331 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 6332 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ 6333 6334 /*!<* 6335 * @brief EXTI2 configuration 6336 */ 6337 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 6338 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 6339 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 6340 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 6341 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 6342 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ 6343 6344 /*!<* 6345 * @brief EXTI3 configuration 6346 */ 6347 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 6348 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 6349 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 6350 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 6351 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 6352 6353 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 6354 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 6355 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 6356 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 6357 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 6358 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 6359 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 6360 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 6361 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 6362 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 6363 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 6364 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 6365 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 6366 6367 /*!<* 6368 * @brief EXTI4 configuration 6369 */ 6370 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 6371 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 6372 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 6373 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 6374 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 6375 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ 6376 6377 /*!<* 6378 * @brief EXTI5 configuration 6379 */ 6380 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 6381 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 6382 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 6383 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 6384 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 6385 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ 6386 6387 /*!<* 6388 * @brief EXTI6 configuration 6389 */ 6390 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 6391 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 6392 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 6393 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 6394 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 6395 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ 6396 6397 /*!<* 6398 * @brief EXTI7 configuration 6399 */ 6400 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 6401 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 6402 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 6403 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 6404 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 6405 6406 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 6407 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 6408 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 6409 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 6410 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 6411 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 6412 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 6413 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 6414 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 6415 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 6416 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 6417 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 6418 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 6419 6420 /*!<* 6421 * @brief EXTI8 configuration 6422 */ 6423 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 6424 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 6425 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 6426 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 6427 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 6428 6429 /*!<* 6430 * @brief EXTI9 configuration 6431 */ 6432 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 6433 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 6434 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 6435 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 6436 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 6437 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ 6438 6439 /*!<* 6440 * @brief EXTI10 configuration 6441 */ 6442 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 6443 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 6444 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 6445 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 6446 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 6447 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ 6448 6449 /*!<* 6450 * @brief EXTI11 configuration 6451 */ 6452 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 6453 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 6454 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 6455 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 6456 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 6457 6458 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 6459 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 6460 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 6461 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 6462 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 6463 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 6464 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 6465 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 6466 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 6467 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 6468 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 6469 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 6470 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 6471 6472 /*!<* 6473 * @brief EXTI12 configuration 6474 */ 6475 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 6476 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 6477 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 6478 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 6479 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 6480 6481 /*!<* 6482 * @brief EXTI13 configuration 6483 */ 6484 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 6485 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 6486 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 6487 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 6488 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 6489 6490 /*!<* 6491 * @brief EXTI14 configuration 6492 */ 6493 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 6494 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 6495 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 6496 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 6497 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 6498 6499 /*!<* 6500 * @brief EXTI15 configuration 6501 */ 6502 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 6503 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 6504 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 6505 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 6506 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 6507 6508 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 6509 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) 6510 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ 6511 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */ 6512 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) 6513 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ 6514 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */ 6515 6516 /******************************************************************************/ 6517 /* */ 6518 /* TIM */ 6519 /* */ 6520 /******************************************************************************/ 6521 /******************* Bit definition for TIM_CR1 register ********************/ 6522 #define TIM_CR1_CEN_Pos (0U) 6523 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 6524 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 6525 #define TIM_CR1_UDIS_Pos (1U) 6526 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 6527 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 6528 #define TIM_CR1_URS_Pos (2U) 6529 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 6530 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 6531 #define TIM_CR1_OPM_Pos (3U) 6532 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 6533 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 6534 #define TIM_CR1_DIR_Pos (4U) 6535 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 6536 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 6537 6538 #define TIM_CR1_CMS_Pos (5U) 6539 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 6540 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 6541 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 6542 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 6543 6544 #define TIM_CR1_ARPE_Pos (7U) 6545 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 6546 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 6547 6548 #define TIM_CR1_CKD_Pos (8U) 6549 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 6550 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 6551 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 6552 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 6553 6554 #define TIM_CR1_UIFREMAP_Pos (11U) 6555 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 6556 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 6557 6558 /******************* Bit definition for TIM_CR2 register ********************/ 6559 #define TIM_CR2_CCPC_Pos (0U) 6560 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 6561 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 6562 #define TIM_CR2_CCUS_Pos (2U) 6563 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 6564 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 6565 #define TIM_CR2_CCDS_Pos (3U) 6566 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 6567 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 6568 6569 #define TIM_CR2_MMS_Pos (4U) 6570 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 6571 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 6572 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 6573 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 6574 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 6575 6576 #define TIM_CR2_TI1S_Pos (7U) 6577 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 6578 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 6579 #define TIM_CR2_OIS1_Pos (8U) 6580 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 6581 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 6582 #define TIM_CR2_OIS1N_Pos (9U) 6583 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 6584 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 6585 #define TIM_CR2_OIS2_Pos (10U) 6586 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 6587 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 6588 #define TIM_CR2_OIS2N_Pos (11U) 6589 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 6590 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 6591 #define TIM_CR2_OIS3_Pos (12U) 6592 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 6593 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 6594 #define TIM_CR2_OIS3N_Pos (13U) 6595 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 6596 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 6597 #define TIM_CR2_OIS4_Pos (14U) 6598 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 6599 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 6600 6601 #define TIM_CR2_OIS5_Pos (16U) 6602 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 6603 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */ 6604 #define TIM_CR2_OIS6_Pos (18U) 6605 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 6606 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */ 6607 6608 #define TIM_CR2_MMS2_Pos (20U) 6609 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 6610 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 6611 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 6612 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 6613 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 6614 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 6615 6616 /******************* Bit definition for TIM_SMCR register *******************/ 6617 #define TIM_SMCR_SMS_Pos (0U) 6618 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 6619 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 6620 #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */ 6621 #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */ 6622 #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */ 6623 #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */ 6624 6625 #define TIM_SMCR_OCCS_Pos (3U) 6626 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 6627 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 6628 6629 #define TIM_SMCR_TS_Pos (4U) 6630 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 6631 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 6632 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 6633 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 6634 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 6635 6636 #define TIM_SMCR_MSM_Pos (7U) 6637 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 6638 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 6639 6640 #define TIM_SMCR_ETF_Pos (8U) 6641 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 6642 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 6643 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 6644 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 6645 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 6646 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 6647 6648 #define TIM_SMCR_ETPS_Pos (12U) 6649 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 6650 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 6651 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 6652 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 6653 6654 #define TIM_SMCR_ECE_Pos (14U) 6655 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 6656 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 6657 #define TIM_SMCR_ETP_Pos (15U) 6658 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 6659 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 6660 6661 /******************* Bit definition for TIM_DIER register *******************/ 6662 #define TIM_DIER_UIE_Pos (0U) 6663 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 6664 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 6665 #define TIM_DIER_CC1IE_Pos (1U) 6666 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 6667 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 6668 #define TIM_DIER_CC2IE_Pos (2U) 6669 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 6670 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 6671 #define TIM_DIER_CC3IE_Pos (3U) 6672 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 6673 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 6674 #define TIM_DIER_CC4IE_Pos (4U) 6675 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 6676 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 6677 #define TIM_DIER_COMIE_Pos (5U) 6678 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 6679 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 6680 #define TIM_DIER_TIE_Pos (6U) 6681 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 6682 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 6683 #define TIM_DIER_BIE_Pos (7U) 6684 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 6685 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 6686 #define TIM_DIER_UDE_Pos (8U) 6687 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 6688 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 6689 #define TIM_DIER_CC1DE_Pos (9U) 6690 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 6691 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 6692 #define TIM_DIER_CC2DE_Pos (10U) 6693 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 6694 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 6695 #define TIM_DIER_CC3DE_Pos (11U) 6696 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 6697 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 6698 #define TIM_DIER_CC4DE_Pos (12U) 6699 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 6700 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 6701 #define TIM_DIER_COMDE_Pos (13U) 6702 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 6703 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 6704 #define TIM_DIER_TDE_Pos (14U) 6705 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 6706 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 6707 6708 /******************** Bit definition for TIM_SR register ********************/ 6709 #define TIM_SR_UIF_Pos (0U) 6710 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 6711 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 6712 #define TIM_SR_CC1IF_Pos (1U) 6713 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 6714 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 6715 #define TIM_SR_CC2IF_Pos (2U) 6716 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 6717 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 6718 #define TIM_SR_CC3IF_Pos (3U) 6719 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 6720 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 6721 #define TIM_SR_CC4IF_Pos (4U) 6722 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 6723 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 6724 #define TIM_SR_COMIF_Pos (5U) 6725 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 6726 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 6727 #define TIM_SR_TIF_Pos (6U) 6728 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 6729 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 6730 #define TIM_SR_BIF_Pos (7U) 6731 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 6732 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 6733 #define TIM_SR_B2IF_Pos (8U) 6734 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 6735 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */ 6736 #define TIM_SR_CC1OF_Pos (9U) 6737 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 6738 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 6739 #define TIM_SR_CC2OF_Pos (10U) 6740 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 6741 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 6742 #define TIM_SR_CC3OF_Pos (11U) 6743 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 6744 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 6745 #define TIM_SR_CC4OF_Pos (12U) 6746 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 6747 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 6748 #define TIM_SR_CC5IF_Pos (16U) 6749 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 6750 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 6751 #define TIM_SR_CC6IF_Pos (17U) 6752 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 6753 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 6754 6755 /******************* Bit definition for TIM_EGR register ********************/ 6756 #define TIM_EGR_UG_Pos (0U) 6757 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 6758 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 6759 #define TIM_EGR_CC1G_Pos (1U) 6760 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 6761 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 6762 #define TIM_EGR_CC2G_Pos (2U) 6763 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 6764 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 6765 #define TIM_EGR_CC3G_Pos (3U) 6766 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 6767 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 6768 #define TIM_EGR_CC4G_Pos (4U) 6769 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 6770 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 6771 #define TIM_EGR_COMG_Pos (5U) 6772 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 6773 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 6774 #define TIM_EGR_TG_Pos (6U) 6775 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 6776 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 6777 #define TIM_EGR_BG_Pos (7U) 6778 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 6779 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 6780 #define TIM_EGR_B2G_Pos (8U) 6781 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 6782 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */ 6783 6784 /****************** Bit definition for TIM_CCMR1 register *******************/ 6785 #define TIM_CCMR1_CC1S_Pos (0U) 6786 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 6787 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 6788 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 6789 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 6790 6791 #define TIM_CCMR1_OC1FE_Pos (2U) 6792 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 6793 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 6794 #define TIM_CCMR1_OC1PE_Pos (3U) 6795 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 6796 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 6797 6798 #define TIM_CCMR1_OC1M_Pos (4U) 6799 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 6800 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 6801 #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */ 6802 #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */ 6803 #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */ 6804 #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */ 6805 6806 #define TIM_CCMR1_OC1CE_Pos (7U) 6807 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 6808 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 6809 6810 #define TIM_CCMR1_CC2S_Pos (8U) 6811 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 6812 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 6813 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 6814 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 6815 6816 #define TIM_CCMR1_OC2FE_Pos (10U) 6817 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 6818 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 6819 #define TIM_CCMR1_OC2PE_Pos (11U) 6820 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 6821 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 6822 6823 #define TIM_CCMR1_OC2M_Pos (12U) 6824 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 6825 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 6826 #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */ 6827 #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */ 6828 #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */ 6829 #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */ 6830 6831 #define TIM_CCMR1_OC2CE_Pos (15U) 6832 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 6833 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 6834 6835 /*----------------------------------------------------------------------------*/ 6836 6837 #define TIM_CCMR1_IC1PSC_Pos (2U) 6838 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 6839 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 6840 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 6841 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 6842 6843 #define TIM_CCMR1_IC1F_Pos (4U) 6844 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 6845 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 6846 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 6847 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 6848 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 6849 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 6850 6851 #define TIM_CCMR1_IC2PSC_Pos (10U) 6852 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 6853 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 6854 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 6855 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 6856 6857 #define TIM_CCMR1_IC2F_Pos (12U) 6858 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 6859 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 6860 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 6861 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 6862 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 6863 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 6864 6865 /****************** Bit definition for TIM_CCMR2 register *******************/ 6866 #define TIM_CCMR2_CC3S_Pos (0U) 6867 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 6868 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 6869 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 6870 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 6871 6872 #define TIM_CCMR2_OC3FE_Pos (2U) 6873 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 6874 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 6875 #define TIM_CCMR2_OC3PE_Pos (3U) 6876 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 6877 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 6878 6879 #define TIM_CCMR2_OC3M_Pos (4U) 6880 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 6881 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 6882 #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */ 6883 #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */ 6884 #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */ 6885 #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */ 6886 6887 #define TIM_CCMR2_OC3CE_Pos (7U) 6888 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 6889 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 6890 6891 #define TIM_CCMR2_CC4S_Pos (8U) 6892 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 6893 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 6894 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 6895 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 6896 6897 #define TIM_CCMR2_OC4FE_Pos (10U) 6898 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 6899 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 6900 #define TIM_CCMR2_OC4PE_Pos (11U) 6901 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 6902 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 6903 6904 #define TIM_CCMR2_OC4M_Pos (12U) 6905 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 6906 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 6907 #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */ 6908 #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */ 6909 #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */ 6910 #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */ 6911 6912 #define TIM_CCMR2_OC4CE_Pos (15U) 6913 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 6914 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 6915 6916 /*----------------------------------------------------------------------------*/ 6917 6918 #define TIM_CCMR2_IC3PSC_Pos (2U) 6919 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 6920 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 6921 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 6922 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 6923 6924 #define TIM_CCMR2_IC3F_Pos (4U) 6925 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 6926 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 6927 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 6928 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 6929 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 6930 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 6931 6932 #define TIM_CCMR2_IC4PSC_Pos (10U) 6933 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 6934 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 6935 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 6936 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 6937 6938 #define TIM_CCMR2_IC4F_Pos (12U) 6939 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 6940 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 6941 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 6942 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 6943 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 6944 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 6945 6946 /******************* Bit definition for TIM_CCER register *******************/ 6947 #define TIM_CCER_CC1E_Pos (0U) 6948 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 6949 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 6950 #define TIM_CCER_CC1P_Pos (1U) 6951 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 6952 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 6953 #define TIM_CCER_CC1NE_Pos (2U) 6954 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 6955 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 6956 #define TIM_CCER_CC1NP_Pos (3U) 6957 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 6958 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 6959 #define TIM_CCER_CC2E_Pos (4U) 6960 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 6961 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 6962 #define TIM_CCER_CC2P_Pos (5U) 6963 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 6964 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 6965 #define TIM_CCER_CC2NE_Pos (6U) 6966 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 6967 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 6968 #define TIM_CCER_CC2NP_Pos (7U) 6969 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 6970 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 6971 #define TIM_CCER_CC3E_Pos (8U) 6972 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 6973 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 6974 #define TIM_CCER_CC3P_Pos (9U) 6975 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 6976 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 6977 #define TIM_CCER_CC3NE_Pos (10U) 6978 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 6979 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 6980 #define TIM_CCER_CC3NP_Pos (11U) 6981 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 6982 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 6983 #define TIM_CCER_CC4E_Pos (12U) 6984 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 6985 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 6986 #define TIM_CCER_CC4P_Pos (13U) 6987 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 6988 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 6989 #define TIM_CCER_CC4NP_Pos (15U) 6990 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 6991 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 6992 #define TIM_CCER_CC5E_Pos (16U) 6993 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 6994 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 6995 #define TIM_CCER_CC5P_Pos (17U) 6996 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 6997 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 6998 #define TIM_CCER_CC6E_Pos (20U) 6999 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 7000 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 7001 #define TIM_CCER_CC6P_Pos (21U) 7002 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 7003 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 7004 7005 /******************* Bit definition for TIM_CNT register ********************/ 7006 #define TIM_CNT_CNT_Pos (0U) 7007 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 7008 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 7009 #define TIM_CNT_UIFCPY_Pos (31U) 7010 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 7011 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */ 7012 7013 /******************* Bit definition for TIM_PSC register ********************/ 7014 #define TIM_PSC_PSC_Pos (0U) 7015 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 7016 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 7017 7018 /******************* Bit definition for TIM_ARR register ********************/ 7019 #define TIM_ARR_ARR_Pos (0U) 7020 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 7021 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 7022 7023 /******************* Bit definition for TIM_RCR register ********************/ 7024 #define TIM_RCR_REP_Pos (0U) 7025 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 7026 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 7027 7028 /******************* Bit definition for TIM_CCR1 register *******************/ 7029 #define TIM_CCR1_CCR1_Pos (0U) 7030 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 7031 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 7032 7033 /******************* Bit definition for TIM_CCR2 register *******************/ 7034 #define TIM_CCR2_CCR2_Pos (0U) 7035 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 7036 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 7037 7038 /******************* Bit definition for TIM_CCR3 register *******************/ 7039 #define TIM_CCR3_CCR3_Pos (0U) 7040 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 7041 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 7042 7043 /******************* Bit definition for TIM_CCR4 register *******************/ 7044 #define TIM_CCR4_CCR4_Pos (0U) 7045 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 7046 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 7047 7048 /******************* Bit definition for TIM_CCR5 register *******************/ 7049 #define TIM_CCR5_CCR5_Pos (0U) 7050 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ 7051 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 7052 #define TIM_CCR5_GC5C1_Pos (29U) 7053 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 7054 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 7055 #define TIM_CCR5_GC5C2_Pos (30U) 7056 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 7057 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 7058 #define TIM_CCR5_GC5C3_Pos (31U) 7059 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 7060 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 7061 7062 /******************* Bit definition for TIM_CCR6 register *******************/ 7063 #define TIM_CCR6_CCR6_Pos (0U) 7064 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 7065 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 7066 7067 /******************* Bit definition for TIM_BDTR register *******************/ 7068 #define TIM_BDTR_DTG_Pos (0U) 7069 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 7070 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 7071 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 7072 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 7073 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 7074 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 7075 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 7076 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 7077 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 7078 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 7079 7080 #define TIM_BDTR_LOCK_Pos (8U) 7081 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 7082 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 7083 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 7084 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 7085 7086 #define TIM_BDTR_OSSI_Pos (10U) 7087 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 7088 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 7089 #define TIM_BDTR_OSSR_Pos (11U) 7090 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 7091 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 7092 #define TIM_BDTR_BKE_Pos (12U) 7093 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 7094 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */ 7095 #define TIM_BDTR_BKP_Pos (13U) 7096 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 7097 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */ 7098 #define TIM_BDTR_AOE_Pos (14U) 7099 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 7100 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 7101 #define TIM_BDTR_MOE_Pos (15U) 7102 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 7103 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 7104 7105 #define TIM_BDTR_BKF_Pos (16U) 7106 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 7107 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */ 7108 #define TIM_BDTR_BK2F_Pos (20U) 7109 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 7110 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */ 7111 7112 #define TIM_BDTR_BK2E_Pos (24U) 7113 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 7114 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */ 7115 #define TIM_BDTR_BK2P_Pos (25U) 7116 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 7117 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */ 7118 7119 /******************* Bit definition for TIM_DCR register ********************/ 7120 #define TIM_DCR_DBA_Pos (0U) 7121 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 7122 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 7123 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 7124 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 7125 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 7126 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 7127 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 7128 7129 #define TIM_DCR_DBL_Pos (8U) 7130 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 7131 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 7132 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 7133 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 7134 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 7135 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 7136 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 7137 7138 /******************* Bit definition for TIM_DMAR register *******************/ 7139 #define TIM_DMAR_DMAB_Pos (0U) 7140 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 7141 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 7142 7143 /******************* Bit definition for TIM16_OR register *********************/ 7144 #define TIM16_OR_TI1_RMP_Pos (0U) 7145 #define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 7146 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ 7147 #define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 7148 #define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 7149 7150 /******************* Bit definition for TIM1_OR register *********************/ 7151 #define TIM1_OR_ETR_RMP_Pos (0U) 7152 #define TIM1_OR_ETR_RMP_Msk (0xFUL << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */ 7153 #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ 7154 #define TIM1_OR_ETR_RMP_0 (0x1UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 7155 #define TIM1_OR_ETR_RMP_1 (0x2UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 7156 #define TIM1_OR_ETR_RMP_2 (0x4UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 7157 #define TIM1_OR_ETR_RMP_3 (0x8UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */ 7158 7159 /****************** Bit definition for TIM_CCMR3 register *******************/ 7160 #define TIM_CCMR3_OC5FE_Pos (2U) 7161 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 7162 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 7163 #define TIM_CCMR3_OC5PE_Pos (3U) 7164 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 7165 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 7166 7167 #define TIM_CCMR3_OC5M_Pos (4U) 7168 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 7169 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ 7170 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 7171 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 7172 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 7173 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 7174 7175 #define TIM_CCMR3_OC5CE_Pos (7U) 7176 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 7177 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 7178 7179 #define TIM_CCMR3_OC6FE_Pos (10U) 7180 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 7181 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 7182 #define TIM_CCMR3_OC6PE_Pos (11U) 7183 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 7184 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 7185 7186 #define TIM_CCMR3_OC6M_Pos (12U) 7187 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 7188 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */ 7189 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 7190 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 7191 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 7192 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 7193 7194 #define TIM_CCMR3_OC6CE_Pos (15U) 7195 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 7196 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 7197 7198 /******************************************************************************/ 7199 /* */ 7200 /* Touch Sensing Controller (TSC) */ 7201 /* */ 7202 /******************************************************************************/ 7203 /******************* Bit definition for TSC_CR register *********************/ 7204 #define TSC_CR_TSCE_Pos (0U) 7205 #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ 7206 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ 7207 #define TSC_CR_START_Pos (1U) 7208 #define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */ 7209 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ 7210 #define TSC_CR_AM_Pos (2U) 7211 #define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */ 7212 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ 7213 #define TSC_CR_SYNCPOL_Pos (3U) 7214 #define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ 7215 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ 7216 #define TSC_CR_IODEF_Pos (4U) 7217 #define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ 7218 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ 7219 7220 #define TSC_CR_MCV_Pos (5U) 7221 #define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ 7222 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ 7223 #define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */ 7224 #define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */ 7225 #define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */ 7226 7227 #define TSC_CR_PGPSC_Pos (12U) 7228 #define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ 7229 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ 7230 #define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ 7231 #define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ 7232 #define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ 7233 7234 #define TSC_CR_SSPSC_Pos (15U) 7235 #define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ 7236 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ 7237 #define TSC_CR_SSE_Pos (16U) 7238 #define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */ 7239 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ 7240 7241 #define TSC_CR_SSD_Pos (17U) 7242 #define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ 7243 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ 7244 #define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */ 7245 #define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */ 7246 #define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */ 7247 #define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */ 7248 #define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */ 7249 #define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */ 7250 #define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */ 7251 7252 #define TSC_CR_CTPL_Pos (24U) 7253 #define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ 7254 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ 7255 #define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ 7256 #define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ 7257 #define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ 7258 #define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ 7259 7260 #define TSC_CR_CTPH_Pos (28U) 7261 #define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ 7262 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ 7263 #define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ 7264 #define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ 7265 #define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ 7266 #define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ 7267 7268 /******************* Bit definition for TSC_IER register ********************/ 7269 #define TSC_IER_EOAIE_Pos (0U) 7270 #define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ 7271 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ 7272 #define TSC_IER_MCEIE_Pos (1U) 7273 #define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ 7274 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ 7275 7276 /******************* Bit definition for TSC_ICR register ********************/ 7277 #define TSC_ICR_EOAIC_Pos (0U) 7278 #define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ 7279 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ 7280 #define TSC_ICR_MCEIC_Pos (1U) 7281 #define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ 7282 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ 7283 7284 /******************* Bit definition for TSC_ISR register ********************/ 7285 #define TSC_ISR_EOAF_Pos (0U) 7286 #define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ 7287 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ 7288 #define TSC_ISR_MCEF_Pos (1U) 7289 #define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ 7290 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ 7291 7292 /******************* Bit definition for TSC_IOHCR register ******************/ 7293 #define TSC_IOHCR_G1_IO1_Pos (0U) 7294 #define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ 7295 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ 7296 #define TSC_IOHCR_G1_IO2_Pos (1U) 7297 #define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ 7298 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ 7299 #define TSC_IOHCR_G1_IO3_Pos (2U) 7300 #define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ 7301 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ 7302 #define TSC_IOHCR_G1_IO4_Pos (3U) 7303 #define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ 7304 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ 7305 #define TSC_IOHCR_G2_IO1_Pos (4U) 7306 #define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ 7307 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ 7308 #define TSC_IOHCR_G2_IO2_Pos (5U) 7309 #define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ 7310 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ 7311 #define TSC_IOHCR_G2_IO3_Pos (6U) 7312 #define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ 7313 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ 7314 #define TSC_IOHCR_G2_IO4_Pos (7U) 7315 #define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ 7316 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ 7317 #define TSC_IOHCR_G3_IO1_Pos (8U) 7318 #define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ 7319 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ 7320 #define TSC_IOHCR_G3_IO2_Pos (9U) 7321 #define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ 7322 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ 7323 #define TSC_IOHCR_G3_IO3_Pos (10U) 7324 #define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ 7325 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ 7326 #define TSC_IOHCR_G3_IO4_Pos (11U) 7327 #define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ 7328 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ 7329 #define TSC_IOHCR_G4_IO1_Pos (12U) 7330 #define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ 7331 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ 7332 #define TSC_IOHCR_G4_IO2_Pos (13U) 7333 #define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ 7334 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ 7335 #define TSC_IOHCR_G4_IO3_Pos (14U) 7336 #define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ 7337 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ 7338 #define TSC_IOHCR_G4_IO4_Pos (15U) 7339 #define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ 7340 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ 7341 #define TSC_IOHCR_G5_IO1_Pos (16U) 7342 #define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ 7343 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ 7344 #define TSC_IOHCR_G5_IO2_Pos (17U) 7345 #define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ 7346 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ 7347 #define TSC_IOHCR_G5_IO3_Pos (18U) 7348 #define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ 7349 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ 7350 #define TSC_IOHCR_G5_IO4_Pos (19U) 7351 #define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ 7352 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ 7353 #define TSC_IOHCR_G6_IO1_Pos (20U) 7354 #define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ 7355 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ 7356 #define TSC_IOHCR_G6_IO2_Pos (21U) 7357 #define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ 7358 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ 7359 #define TSC_IOHCR_G6_IO3_Pos (22U) 7360 #define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ 7361 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ 7362 #define TSC_IOHCR_G6_IO4_Pos (23U) 7363 #define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ 7364 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ 7365 #define TSC_IOHCR_G7_IO1_Pos (24U) 7366 #define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ 7367 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ 7368 #define TSC_IOHCR_G7_IO2_Pos (25U) 7369 #define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ 7370 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ 7371 #define TSC_IOHCR_G7_IO3_Pos (26U) 7372 #define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ 7373 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ 7374 #define TSC_IOHCR_G7_IO4_Pos (27U) 7375 #define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ 7376 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ 7377 #define TSC_IOHCR_G8_IO1_Pos (28U) 7378 #define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */ 7379 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ 7380 #define TSC_IOHCR_G8_IO2_Pos (29U) 7381 #define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */ 7382 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ 7383 #define TSC_IOHCR_G8_IO3_Pos (30U) 7384 #define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */ 7385 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ 7386 #define TSC_IOHCR_G8_IO4_Pos (31U) 7387 #define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */ 7388 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ 7389 7390 /******************* Bit definition for TSC_IOASCR register *****************/ 7391 #define TSC_IOASCR_G1_IO1_Pos (0U) 7392 #define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ 7393 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ 7394 #define TSC_IOASCR_G1_IO2_Pos (1U) 7395 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ 7396 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ 7397 #define TSC_IOASCR_G1_IO3_Pos (2U) 7398 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ 7399 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ 7400 #define TSC_IOASCR_G1_IO4_Pos (3U) 7401 #define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ 7402 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ 7403 #define TSC_IOASCR_G2_IO1_Pos (4U) 7404 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ 7405 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ 7406 #define TSC_IOASCR_G2_IO2_Pos (5U) 7407 #define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ 7408 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ 7409 #define TSC_IOASCR_G2_IO3_Pos (6U) 7410 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ 7411 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ 7412 #define TSC_IOASCR_G2_IO4_Pos (7U) 7413 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ 7414 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ 7415 #define TSC_IOASCR_G3_IO1_Pos (8U) 7416 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ 7417 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ 7418 #define TSC_IOASCR_G3_IO2_Pos (9U) 7419 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ 7420 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ 7421 #define TSC_IOASCR_G3_IO3_Pos (10U) 7422 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ 7423 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ 7424 #define TSC_IOASCR_G3_IO4_Pos (11U) 7425 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ 7426 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ 7427 #define TSC_IOASCR_G4_IO1_Pos (12U) 7428 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ 7429 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ 7430 #define TSC_IOASCR_G4_IO2_Pos (13U) 7431 #define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ 7432 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ 7433 #define TSC_IOASCR_G4_IO3_Pos (14U) 7434 #define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ 7435 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ 7436 #define TSC_IOASCR_G4_IO4_Pos (15U) 7437 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ 7438 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ 7439 #define TSC_IOASCR_G5_IO1_Pos (16U) 7440 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ 7441 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ 7442 #define TSC_IOASCR_G5_IO2_Pos (17U) 7443 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ 7444 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ 7445 #define TSC_IOASCR_G5_IO3_Pos (18U) 7446 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ 7447 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ 7448 #define TSC_IOASCR_G5_IO4_Pos (19U) 7449 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ 7450 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ 7451 #define TSC_IOASCR_G6_IO1_Pos (20U) 7452 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ 7453 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ 7454 #define TSC_IOASCR_G6_IO2_Pos (21U) 7455 #define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ 7456 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ 7457 #define TSC_IOASCR_G6_IO3_Pos (22U) 7458 #define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ 7459 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ 7460 #define TSC_IOASCR_G6_IO4_Pos (23U) 7461 #define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ 7462 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ 7463 #define TSC_IOASCR_G7_IO1_Pos (24U) 7464 #define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ 7465 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ 7466 #define TSC_IOASCR_G7_IO2_Pos (25U) 7467 #define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ 7468 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ 7469 #define TSC_IOASCR_G7_IO3_Pos (26U) 7470 #define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ 7471 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ 7472 #define TSC_IOASCR_G7_IO4_Pos (27U) 7473 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ 7474 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ 7475 #define TSC_IOASCR_G8_IO1_Pos (28U) 7476 #define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */ 7477 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */ 7478 #define TSC_IOASCR_G8_IO2_Pos (29U) 7479 #define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */ 7480 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */ 7481 #define TSC_IOASCR_G8_IO3_Pos (30U) 7482 #define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */ 7483 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */ 7484 #define TSC_IOASCR_G8_IO4_Pos (31U) 7485 #define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */ 7486 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */ 7487 7488 /******************* Bit definition for TSC_IOSCR register ******************/ 7489 #define TSC_IOSCR_G1_IO1_Pos (0U) 7490 #define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ 7491 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ 7492 #define TSC_IOSCR_G1_IO2_Pos (1U) 7493 #define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ 7494 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ 7495 #define TSC_IOSCR_G1_IO3_Pos (2U) 7496 #define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ 7497 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ 7498 #define TSC_IOSCR_G1_IO4_Pos (3U) 7499 #define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ 7500 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ 7501 #define TSC_IOSCR_G2_IO1_Pos (4U) 7502 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ 7503 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ 7504 #define TSC_IOSCR_G2_IO2_Pos (5U) 7505 #define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ 7506 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ 7507 #define TSC_IOSCR_G2_IO3_Pos (6U) 7508 #define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ 7509 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ 7510 #define TSC_IOSCR_G2_IO4_Pos (7U) 7511 #define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ 7512 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ 7513 #define TSC_IOSCR_G3_IO1_Pos (8U) 7514 #define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ 7515 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ 7516 #define TSC_IOSCR_G3_IO2_Pos (9U) 7517 #define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ 7518 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ 7519 #define TSC_IOSCR_G3_IO3_Pos (10U) 7520 #define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ 7521 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ 7522 #define TSC_IOSCR_G3_IO4_Pos (11U) 7523 #define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ 7524 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ 7525 #define TSC_IOSCR_G4_IO1_Pos (12U) 7526 #define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ 7527 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ 7528 #define TSC_IOSCR_G4_IO2_Pos (13U) 7529 #define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ 7530 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ 7531 #define TSC_IOSCR_G4_IO3_Pos (14U) 7532 #define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ 7533 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ 7534 #define TSC_IOSCR_G4_IO4_Pos (15U) 7535 #define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ 7536 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ 7537 #define TSC_IOSCR_G5_IO1_Pos (16U) 7538 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ 7539 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ 7540 #define TSC_IOSCR_G5_IO2_Pos (17U) 7541 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ 7542 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ 7543 #define TSC_IOSCR_G5_IO3_Pos (18U) 7544 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ 7545 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ 7546 #define TSC_IOSCR_G5_IO4_Pos (19U) 7547 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ 7548 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ 7549 #define TSC_IOSCR_G6_IO1_Pos (20U) 7550 #define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ 7551 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ 7552 #define TSC_IOSCR_G6_IO2_Pos (21U) 7553 #define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ 7554 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ 7555 #define TSC_IOSCR_G6_IO3_Pos (22U) 7556 #define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ 7557 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ 7558 #define TSC_IOSCR_G6_IO4_Pos (23U) 7559 #define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ 7560 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ 7561 #define TSC_IOSCR_G7_IO1_Pos (24U) 7562 #define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ 7563 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ 7564 #define TSC_IOSCR_G7_IO2_Pos (25U) 7565 #define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ 7566 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ 7567 #define TSC_IOSCR_G7_IO3_Pos (26U) 7568 #define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ 7569 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ 7570 #define TSC_IOSCR_G7_IO4_Pos (27U) 7571 #define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ 7572 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ 7573 #define TSC_IOSCR_G8_IO1_Pos (28U) 7574 #define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */ 7575 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */ 7576 #define TSC_IOSCR_G8_IO2_Pos (29U) 7577 #define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */ 7578 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */ 7579 #define TSC_IOSCR_G8_IO3_Pos (30U) 7580 #define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */ 7581 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */ 7582 #define TSC_IOSCR_G8_IO4_Pos (31U) 7583 #define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */ 7584 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */ 7585 7586 /******************* Bit definition for TSC_IOCCR register ******************/ 7587 #define TSC_IOCCR_G1_IO1_Pos (0U) 7588 #define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ 7589 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ 7590 #define TSC_IOCCR_G1_IO2_Pos (1U) 7591 #define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ 7592 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ 7593 #define TSC_IOCCR_G1_IO3_Pos (2U) 7594 #define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ 7595 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ 7596 #define TSC_IOCCR_G1_IO4_Pos (3U) 7597 #define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ 7598 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ 7599 #define TSC_IOCCR_G2_IO1_Pos (4U) 7600 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ 7601 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ 7602 #define TSC_IOCCR_G2_IO2_Pos (5U) 7603 #define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ 7604 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ 7605 #define TSC_IOCCR_G2_IO3_Pos (6U) 7606 #define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ 7607 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ 7608 #define TSC_IOCCR_G2_IO4_Pos (7U) 7609 #define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ 7610 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ 7611 #define TSC_IOCCR_G3_IO1_Pos (8U) 7612 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ 7613 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ 7614 #define TSC_IOCCR_G3_IO2_Pos (9U) 7615 #define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ 7616 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ 7617 #define TSC_IOCCR_G3_IO3_Pos (10U) 7618 #define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ 7619 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ 7620 #define TSC_IOCCR_G3_IO4_Pos (11U) 7621 #define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ 7622 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ 7623 #define TSC_IOCCR_G4_IO1_Pos (12U) 7624 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ 7625 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ 7626 #define TSC_IOCCR_G4_IO2_Pos (13U) 7627 #define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ 7628 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ 7629 #define TSC_IOCCR_G4_IO3_Pos (14U) 7630 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ 7631 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ 7632 #define TSC_IOCCR_G4_IO4_Pos (15U) 7633 #define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ 7634 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ 7635 #define TSC_IOCCR_G5_IO1_Pos (16U) 7636 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ 7637 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ 7638 #define TSC_IOCCR_G5_IO2_Pos (17U) 7639 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ 7640 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ 7641 #define TSC_IOCCR_G5_IO3_Pos (18U) 7642 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ 7643 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ 7644 #define TSC_IOCCR_G5_IO4_Pos (19U) 7645 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ 7646 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ 7647 #define TSC_IOCCR_G6_IO1_Pos (20U) 7648 #define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ 7649 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ 7650 #define TSC_IOCCR_G6_IO2_Pos (21U) 7651 #define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ 7652 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ 7653 #define TSC_IOCCR_G6_IO3_Pos (22U) 7654 #define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ 7655 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ 7656 #define TSC_IOCCR_G6_IO4_Pos (23U) 7657 #define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ 7658 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ 7659 #define TSC_IOCCR_G7_IO1_Pos (24U) 7660 #define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ 7661 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ 7662 #define TSC_IOCCR_G7_IO2_Pos (25U) 7663 #define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ 7664 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ 7665 #define TSC_IOCCR_G7_IO3_Pos (26U) 7666 #define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ 7667 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ 7668 #define TSC_IOCCR_G7_IO4_Pos (27U) 7669 #define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ 7670 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ 7671 #define TSC_IOCCR_G8_IO1_Pos (28U) 7672 #define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */ 7673 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */ 7674 #define TSC_IOCCR_G8_IO2_Pos (29U) 7675 #define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */ 7676 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */ 7677 #define TSC_IOCCR_G8_IO3_Pos (30U) 7678 #define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */ 7679 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */ 7680 #define TSC_IOCCR_G8_IO4_Pos (31U) 7681 #define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */ 7682 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */ 7683 7684 /******************* Bit definition for TSC_IOGCSR register *****************/ 7685 #define TSC_IOGCSR_G1E_Pos (0U) 7686 #define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ 7687 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ 7688 #define TSC_IOGCSR_G2E_Pos (1U) 7689 #define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ 7690 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ 7691 #define TSC_IOGCSR_G3E_Pos (2U) 7692 #define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ 7693 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ 7694 #define TSC_IOGCSR_G4E_Pos (3U) 7695 #define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ 7696 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ 7697 #define TSC_IOGCSR_G5E_Pos (4U) 7698 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ 7699 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ 7700 #define TSC_IOGCSR_G6E_Pos (5U) 7701 #define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ 7702 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ 7703 #define TSC_IOGCSR_G7E_Pos (6U) 7704 #define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ 7705 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ 7706 #define TSC_IOGCSR_G8E_Pos (7U) 7707 #define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */ 7708 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */ 7709 #define TSC_IOGCSR_G1S_Pos (16U) 7710 #define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ 7711 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ 7712 #define TSC_IOGCSR_G2S_Pos (17U) 7713 #define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ 7714 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ 7715 #define TSC_IOGCSR_G3S_Pos (18U) 7716 #define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ 7717 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ 7718 #define TSC_IOGCSR_G4S_Pos (19U) 7719 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ 7720 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ 7721 #define TSC_IOGCSR_G5S_Pos (20U) 7722 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ 7723 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ 7724 #define TSC_IOGCSR_G6S_Pos (21U) 7725 #define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ 7726 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ 7727 #define TSC_IOGCSR_G7S_Pos (22U) 7728 #define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ 7729 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ 7730 #define TSC_IOGCSR_G8S_Pos (23U) 7731 #define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */ 7732 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */ 7733 7734 /******************* Bit definition for TSC_IOGXCR register *****************/ 7735 #define TSC_IOGXCR_CNT_Pos (0U) 7736 #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ 7737 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ 7738 7739 /******************************************************************************/ 7740 /* */ 7741 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 7742 /* */ 7743 /******************************************************************************/ 7744 7745 /* 7746 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 7747 */ 7748 7749 /* Support of 7 bits data length feature */ 7750 #define USART_7BITS_SUPPORT 7751 7752 /****************** Bit definition for USART_CR1 register *******************/ 7753 #define USART_CR1_UE_Pos (0U) 7754 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 7755 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 7756 #define USART_CR1_UESM_Pos (1U) 7757 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 7758 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 7759 #define USART_CR1_RE_Pos (2U) 7760 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 7761 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 7762 #define USART_CR1_TE_Pos (3U) 7763 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 7764 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 7765 #define USART_CR1_IDLEIE_Pos (4U) 7766 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 7767 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 7768 #define USART_CR1_RXNEIE_Pos (5U) 7769 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 7770 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 7771 #define USART_CR1_TCIE_Pos (6U) 7772 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 7773 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 7774 #define USART_CR1_TXEIE_Pos (7U) 7775 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 7776 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 7777 #define USART_CR1_PEIE_Pos (8U) 7778 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 7779 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 7780 #define USART_CR1_PS_Pos (9U) 7781 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 7782 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 7783 #define USART_CR1_PCE_Pos (10U) 7784 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 7785 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 7786 #define USART_CR1_WAKE_Pos (11U) 7787 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 7788 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 7789 #define USART_CR1_M0_Pos (12U) 7790 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 7791 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */ 7792 #define USART_CR1_MME_Pos (13U) 7793 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 7794 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 7795 #define USART_CR1_CMIE_Pos (14U) 7796 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 7797 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 7798 #define USART_CR1_OVER8_Pos (15U) 7799 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 7800 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 7801 #define USART_CR1_DEDT_Pos (16U) 7802 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 7803 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 7804 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 7805 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 7806 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 7807 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 7808 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 7809 #define USART_CR1_DEAT_Pos (21U) 7810 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 7811 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 7812 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 7813 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 7814 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 7815 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 7816 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 7817 #define USART_CR1_RTOIE_Pos (26U) 7818 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 7819 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 7820 #define USART_CR1_EOBIE_Pos (27U) 7821 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 7822 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 7823 #define USART_CR1_M1_Pos (28U) 7824 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 7825 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */ 7826 #define USART_CR1_M_Pos (12U) 7827 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 7828 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */ 7829 7830 /****************** Bit definition for USART_CR2 register *******************/ 7831 #define USART_CR2_ADDM7_Pos (4U) 7832 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 7833 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 7834 #define USART_CR2_LBDL_Pos (5U) 7835 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 7836 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 7837 #define USART_CR2_LBDIE_Pos (6U) 7838 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 7839 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 7840 #define USART_CR2_LBCL_Pos (8U) 7841 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 7842 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 7843 #define USART_CR2_CPHA_Pos (9U) 7844 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 7845 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 7846 #define USART_CR2_CPOL_Pos (10U) 7847 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 7848 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 7849 #define USART_CR2_CLKEN_Pos (11U) 7850 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 7851 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 7852 #define USART_CR2_STOP_Pos (12U) 7853 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 7854 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 7855 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 7856 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 7857 #define USART_CR2_LINEN_Pos (14U) 7858 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 7859 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 7860 #define USART_CR2_SWAP_Pos (15U) 7861 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 7862 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 7863 #define USART_CR2_RXINV_Pos (16U) 7864 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 7865 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 7866 #define USART_CR2_TXINV_Pos (17U) 7867 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 7868 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 7869 #define USART_CR2_DATAINV_Pos (18U) 7870 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 7871 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 7872 #define USART_CR2_MSBFIRST_Pos (19U) 7873 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 7874 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 7875 #define USART_CR2_ABREN_Pos (20U) 7876 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 7877 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 7878 #define USART_CR2_ABRMODE_Pos (21U) 7879 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 7880 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 7881 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 7882 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 7883 #define USART_CR2_RTOEN_Pos (23U) 7884 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 7885 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 7886 #define USART_CR2_ADD_Pos (24U) 7887 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 7888 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 7889 7890 /****************** Bit definition for USART_CR3 register *******************/ 7891 #define USART_CR3_EIE_Pos (0U) 7892 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 7893 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 7894 #define USART_CR3_IREN_Pos (1U) 7895 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 7896 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 7897 #define USART_CR3_IRLP_Pos (2U) 7898 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 7899 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 7900 #define USART_CR3_HDSEL_Pos (3U) 7901 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 7902 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 7903 #define USART_CR3_NACK_Pos (4U) 7904 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 7905 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 7906 #define USART_CR3_SCEN_Pos (5U) 7907 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 7908 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 7909 #define USART_CR3_DMAR_Pos (6U) 7910 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 7911 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 7912 #define USART_CR3_DMAT_Pos (7U) 7913 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 7914 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 7915 #define USART_CR3_RTSE_Pos (8U) 7916 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 7917 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 7918 #define USART_CR3_CTSE_Pos (9U) 7919 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 7920 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 7921 #define USART_CR3_CTSIE_Pos (10U) 7922 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 7923 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 7924 #define USART_CR3_ONEBIT_Pos (11U) 7925 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 7926 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 7927 #define USART_CR3_OVRDIS_Pos (12U) 7928 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 7929 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 7930 #define USART_CR3_DDRE_Pos (13U) 7931 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 7932 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 7933 #define USART_CR3_DEM_Pos (14U) 7934 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 7935 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 7936 #define USART_CR3_DEP_Pos (15U) 7937 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 7938 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 7939 #define USART_CR3_SCARCNT_Pos (17U) 7940 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 7941 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 7942 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 7943 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 7944 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 7945 #define USART_CR3_WUS_Pos (20U) 7946 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 7947 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 7948 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 7949 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 7950 #define USART_CR3_WUFIE_Pos (22U) 7951 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 7952 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 7953 7954 /****************** Bit definition for USART_BRR register *******************/ 7955 #define USART_BRR_DIV_FRACTION_Pos (0U) 7956 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 7957 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 7958 #define USART_BRR_DIV_MANTISSA_Pos (4U) 7959 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 7960 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 7961 7962 /****************** Bit definition for USART_GTPR register ******************/ 7963 #define USART_GTPR_PSC_Pos (0U) 7964 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 7965 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 7966 #define USART_GTPR_GT_Pos (8U) 7967 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 7968 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 7969 7970 7971 /******************* Bit definition for USART_RTOR register *****************/ 7972 #define USART_RTOR_RTO_Pos (0U) 7973 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 7974 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 7975 #define USART_RTOR_BLEN_Pos (24U) 7976 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 7977 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 7978 7979 /******************* Bit definition for USART_RQR register ******************/ 7980 #define USART_RQR_ABRRQ_Pos (0U) 7981 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 7982 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 7983 #define USART_RQR_SBKRQ_Pos (1U) 7984 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 7985 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 7986 #define USART_RQR_MMRQ_Pos (2U) 7987 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 7988 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 7989 #define USART_RQR_RXFRQ_Pos (3U) 7990 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 7991 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 7992 #define USART_RQR_TXFRQ_Pos (4U) 7993 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 7994 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 7995 7996 /******************* Bit definition for USART_ISR register ******************/ 7997 #define USART_ISR_PE_Pos (0U) 7998 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 7999 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 8000 #define USART_ISR_FE_Pos (1U) 8001 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 8002 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 8003 #define USART_ISR_NE_Pos (2U) 8004 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 8005 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 8006 #define USART_ISR_ORE_Pos (3U) 8007 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 8008 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 8009 #define USART_ISR_IDLE_Pos (4U) 8010 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 8011 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 8012 #define USART_ISR_RXNE_Pos (5U) 8013 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 8014 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 8015 #define USART_ISR_TC_Pos (6U) 8016 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 8017 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 8018 #define USART_ISR_TXE_Pos (7U) 8019 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 8020 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 8021 #define USART_ISR_LBDF_Pos (8U) 8022 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 8023 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 8024 #define USART_ISR_CTSIF_Pos (9U) 8025 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 8026 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 8027 #define USART_ISR_CTS_Pos (10U) 8028 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 8029 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 8030 #define USART_ISR_RTOF_Pos (11U) 8031 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 8032 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 8033 #define USART_ISR_EOBF_Pos (12U) 8034 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 8035 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 8036 #define USART_ISR_ABRE_Pos (14U) 8037 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 8038 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 8039 #define USART_ISR_ABRF_Pos (15U) 8040 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 8041 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 8042 #define USART_ISR_BUSY_Pos (16U) 8043 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 8044 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 8045 #define USART_ISR_CMF_Pos (17U) 8046 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 8047 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 8048 #define USART_ISR_SBKF_Pos (18U) 8049 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 8050 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 8051 #define USART_ISR_RWU_Pos (19U) 8052 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 8053 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 8054 #define USART_ISR_WUF_Pos (20U) 8055 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 8056 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 8057 #define USART_ISR_TEACK_Pos (21U) 8058 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 8059 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 8060 #define USART_ISR_REACK_Pos (22U) 8061 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 8062 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 8063 8064 /******************* Bit definition for USART_ICR register ******************/ 8065 #define USART_ICR_PECF_Pos (0U) 8066 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 8067 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 8068 #define USART_ICR_FECF_Pos (1U) 8069 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 8070 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 8071 #define USART_ICR_NCF_Pos (2U) 8072 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 8073 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 8074 #define USART_ICR_ORECF_Pos (3U) 8075 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 8076 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 8077 #define USART_ICR_IDLECF_Pos (4U) 8078 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 8079 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 8080 #define USART_ICR_TCCF_Pos (6U) 8081 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 8082 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 8083 #define USART_ICR_LBDCF_Pos (8U) 8084 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 8085 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 8086 #define USART_ICR_CTSCF_Pos (9U) 8087 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 8088 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 8089 #define USART_ICR_RTOCF_Pos (11U) 8090 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 8091 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 8092 #define USART_ICR_EOBCF_Pos (12U) 8093 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 8094 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 8095 #define USART_ICR_CMCF_Pos (17U) 8096 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 8097 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 8098 #define USART_ICR_WUCF_Pos (20U) 8099 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 8100 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 8101 8102 /******************* Bit definition for USART_RDR register ******************/ 8103 #define USART_RDR_RDR_Pos (0U) 8104 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 8105 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 8106 8107 /******************* Bit definition for USART_TDR register ******************/ 8108 #define USART_TDR_TDR_Pos (0U) 8109 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 8110 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 8111 8112 /******************************************************************************/ 8113 /* */ 8114 /* Window WATCHDOG */ 8115 /* */ 8116 /******************************************************************************/ 8117 /******************* Bit definition for WWDG_CR register ********************/ 8118 #define WWDG_CR_T_Pos (0U) 8119 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 8120 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 8121 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 8122 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 8123 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 8124 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 8125 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 8126 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 8127 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 8128 8129 /* Legacy defines */ 8130 #define WWDG_CR_T0 WWDG_CR_T_0 8131 #define WWDG_CR_T1 WWDG_CR_T_1 8132 #define WWDG_CR_T2 WWDG_CR_T_2 8133 #define WWDG_CR_T3 WWDG_CR_T_3 8134 #define WWDG_CR_T4 WWDG_CR_T_4 8135 #define WWDG_CR_T5 WWDG_CR_T_5 8136 #define WWDG_CR_T6 WWDG_CR_T_6 8137 8138 #define WWDG_CR_WDGA_Pos (7U) 8139 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 8140 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 8141 8142 /******************* Bit definition for WWDG_CFR register *******************/ 8143 #define WWDG_CFR_W_Pos (0U) 8144 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 8145 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 8146 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 8147 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 8148 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 8149 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 8150 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 8151 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 8152 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 8153 8154 /* Legacy defines */ 8155 #define WWDG_CFR_W0 WWDG_CFR_W_0 8156 #define WWDG_CFR_W1 WWDG_CFR_W_1 8157 #define WWDG_CFR_W2 WWDG_CFR_W_2 8158 #define WWDG_CFR_W3 WWDG_CFR_W_3 8159 #define WWDG_CFR_W4 WWDG_CFR_W_4 8160 #define WWDG_CFR_W5 WWDG_CFR_W_5 8161 #define WWDG_CFR_W6 WWDG_CFR_W_6 8162 8163 #define WWDG_CFR_WDGTB_Pos (7U) 8164 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 8165 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 8166 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 8167 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 8168 8169 /* Legacy defines */ 8170 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 8171 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 8172 8173 #define WWDG_CFR_EWI_Pos (9U) 8174 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 8175 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 8176 8177 /******************* Bit definition for WWDG_SR register ********************/ 8178 #define WWDG_SR_EWIF_Pos (0U) 8179 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 8180 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 8181 8182 /** 8183 * @} 8184 */ 8185 8186 /** 8187 * @} 8188 */ 8189 8190 /** @addtogroup Exported_macros 8191 * @{ 8192 */ 8193 8194 /****************************** ADC Instances *********************************/ 8195 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 8196 8197 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 8198 8199 /****************************** COMP Instances ********************************/ 8200 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \ 8201 ((INSTANCE) == COMP4) || \ 8202 ((INSTANCE) == COMP6)) 8203 8204 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (0U) 8205 8206 /******************** COMP Instances with switch on DAC1 Channel1 output ******/ 8207 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) 8208 8209 /******************** COMP Instances with window mode capability **************/ 8210 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U) 8211 8212 /****************************** CRC Instances *********************************/ 8213 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 8214 8215 /****************************** DAC Instances *********************************/ 8216 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) 8217 8218 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \ 8219 (((INSTANCE) == DAC1) && \ 8220 ((CHANNEL) == DAC_CHANNEL_1)) 8221 8222 /****************************** DMA Instances *********************************/ 8223 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 8224 ((INSTANCE) == DMA1_Channel2) || \ 8225 ((INSTANCE) == DMA1_Channel3) || \ 8226 ((INSTANCE) == DMA1_Channel4) || \ 8227 ((INSTANCE) == DMA1_Channel5) || \ 8228 ((INSTANCE) == DMA1_Channel6) || \ 8229 ((INSTANCE) == DMA1_Channel7)) 8230 8231 /****************************** GPIO Instances ********************************/ 8232 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 8233 ((INSTANCE) == GPIOB) || \ 8234 ((INSTANCE) == GPIOC) || \ 8235 ((INSTANCE) == GPIOD) || \ 8236 ((INSTANCE) == GPIOF)) 8237 8238 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 8239 ((INSTANCE) == GPIOB) || \ 8240 ((INSTANCE) == GPIOC) || \ 8241 ((INSTANCE) == GPIOD) || \ 8242 ((INSTANCE) == GPIOF)) 8243 8244 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 8245 ((INSTANCE) == GPIOB) || \ 8246 ((INSTANCE) == GPIOC) || \ 8247 ((INSTANCE) == GPIOD) || \ 8248 ((INSTANCE) == GPIOF)) 8249 8250 /****************************** I2C Instances *********************************/ 8251 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 8252 ((INSTANCE) == I2C2) || \ 8253 ((INSTANCE) == I2C3)) 8254 8255 /****************** I2C Instances : wakeup capability from stop modes *********/ 8256 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 8257 8258 /****************************** I2S Instances *********************************/ 8259 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ 8260 ((INSTANCE) == SPI3)) 8261 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \ 8262 ((INSTANCE) == I2S3ext)) 8263 8264 /****************************** OPAMP Instances *******************************/ 8265 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2) 8266 8267 /****************************** IWDG Instances ********************************/ 8268 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 8269 8270 /****************************** RTC Instances *********************************/ 8271 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 8272 8273 /****************************** SMBUS Instances *******************************/ 8274 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 8275 ((INSTANCE) == I2C2) || \ 8276 ((INSTANCE) == I2C3)) 8277 8278 /****************************** SPI Instances *********************************/ 8279 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ 8280 ((INSTANCE) == SPI3)) 8281 8282 /******************* TIM Instances : All supported instances ******************/ 8283 #define IS_TIM_INSTANCE(INSTANCE)\ 8284 (((INSTANCE) == TIM1) || \ 8285 ((INSTANCE) == TIM2) || \ 8286 ((INSTANCE) == TIM6) || \ 8287 ((INSTANCE) == TIM15) || \ 8288 ((INSTANCE) == TIM16) || \ 8289 ((INSTANCE) == TIM17)) 8290 8291 /******************* TIM Instances : at least 1 capture/compare channel *******/ 8292 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 8293 (((INSTANCE) == TIM1) || \ 8294 ((INSTANCE) == TIM2) || \ 8295 ((INSTANCE) == TIM15) || \ 8296 ((INSTANCE) == TIM16) || \ 8297 ((INSTANCE) == TIM17)) 8298 8299 /****************** TIM Instances : at least 2 capture/compare channels *******/ 8300 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 8301 (((INSTANCE) == TIM1) || \ 8302 ((INSTANCE) == TIM2) || \ 8303 ((INSTANCE) == TIM15)) 8304 8305 /****************** TIM Instances : at least 3 capture/compare channels *******/ 8306 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 8307 (((INSTANCE) == TIM1) || \ 8308 ((INSTANCE) == TIM2)) 8309 8310 /****************** TIM Instances : at least 4 capture/compare channels *******/ 8311 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 8312 (((INSTANCE) == TIM1) || \ 8313 ((INSTANCE) == TIM2)) 8314 8315 /****************** TIM Instances : at least 5 capture/compare channels *******/ 8316 #define IS_TIM_CC5_INSTANCE(INSTANCE)\ 8317 ((INSTANCE) == TIM1) 8318 8319 /****************** TIM Instances : at least 6 capture/compare channels *******/ 8320 #define IS_TIM_CC6_INSTANCE(INSTANCE)\ 8321 ((INSTANCE) == TIM1) 8322 8323 /************************** TIM Instances : Advanced-control timers ***********/ 8324 8325 /****************** TIM Instances : Advanced timer instances *******************/ 8326 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ 8327 ((INSTANCE) == TIM1) 8328 8329 /****************** TIM Instances : supporting clock selection ****************/ 8330 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\ 8331 (((INSTANCE) == TIM1) || \ 8332 ((INSTANCE) == TIM2) || \ 8333 ((INSTANCE) == TIM15)) 8334 8335 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */ 8336 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 8337 (((INSTANCE) == TIM1) || \ 8338 ((INSTANCE) == TIM2)) 8339 8340 /****************** TIM Instances : supporting external clock mode 2 **********/ 8341 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 8342 (((INSTANCE) == TIM1) || \ 8343 ((INSTANCE) == TIM2)) 8344 8345 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 8346 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 8347 (((INSTANCE) == TIM1) || \ 8348 ((INSTANCE) == TIM2) || \ 8349 ((INSTANCE) == TIM15)) 8350 8351 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 8352 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 8353 (((INSTANCE) == TIM1) || \ 8354 ((INSTANCE) == TIM2) || \ 8355 ((INSTANCE) == TIM15)) 8356 8357 /****************** TIM Instances : supporting OCxREF clear *******************/ 8358 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 8359 (((INSTANCE) == TIM1) || \ 8360 ((INSTANCE) == TIM2)) 8361 8362 /****************** TIM Instances : supporting encoder interface **************/ 8363 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 8364 (((INSTANCE) == TIM1) || \ 8365 ((INSTANCE) == TIM2)) 8366 8367 /****************** TIM Instances : supporting Hall interface *****************/ 8368 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ 8369 ((INSTANCE) == TIM1) 8370 8371 /**************** TIM Instances : external trigger input available ************/ 8372 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 8373 ((INSTANCE) == TIM2)) 8374 8375 8376 /****************** TIM Instances : supporting input XOR function *************/ 8377 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 8378 (((INSTANCE) == TIM1) || \ 8379 ((INSTANCE) == TIM2) || \ 8380 ((INSTANCE) == TIM15)) 8381 8382 /****************** TIM Instances : supporting master mode ********************/ 8383 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 8384 (((INSTANCE) == TIM1) || \ 8385 ((INSTANCE) == TIM2) || \ 8386 ((INSTANCE) == TIM6) || \ 8387 ((INSTANCE) == TIM15)) 8388 8389 /****************** TIM Instances : supporting slave mode *********************/ 8390 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 8391 (((INSTANCE) == TIM1) || \ 8392 ((INSTANCE) == TIM2) || \ 8393 ((INSTANCE) == TIM15)) 8394 8395 /****************** TIM Instances : supporting 32 bits counter ****************/ 8396 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ 8397 ((INSTANCE) == TIM2) 8398 8399 /****************** TIM Instances : supporting DMA burst **********************/ 8400 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 8401 (((INSTANCE) == TIM1) || \ 8402 ((INSTANCE) == TIM2) || \ 8403 ((INSTANCE) == TIM15) || \ 8404 ((INSTANCE) == TIM16) || \ 8405 ((INSTANCE) == TIM17)) 8406 8407 /****************** TIM Instances : supporting the break function *************/ 8408 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 8409 (((INSTANCE) == TIM1) || \ 8410 ((INSTANCE) == TIM15) || \ 8411 ((INSTANCE) == TIM16) || \ 8412 ((INSTANCE) == TIM17)) 8413 8414 /****************** TIM Instances : supporting input/output channel(s) ********/ 8415 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 8416 ((((INSTANCE) == TIM1) && \ 8417 (((CHANNEL) == TIM_CHANNEL_1) || \ 8418 ((CHANNEL) == TIM_CHANNEL_2) || \ 8419 ((CHANNEL) == TIM_CHANNEL_3) || \ 8420 ((CHANNEL) == TIM_CHANNEL_4) || \ 8421 ((CHANNEL) == TIM_CHANNEL_5) || \ 8422 ((CHANNEL) == TIM_CHANNEL_6))) \ 8423 || \ 8424 (((INSTANCE) == TIM2) && \ 8425 (((CHANNEL) == TIM_CHANNEL_1) || \ 8426 ((CHANNEL) == TIM_CHANNEL_2) || \ 8427 ((CHANNEL) == TIM_CHANNEL_3) || \ 8428 ((CHANNEL) == TIM_CHANNEL_4))) \ 8429 || \ 8430 (((INSTANCE) == TIM15) && \ 8431 (((CHANNEL) == TIM_CHANNEL_1) || \ 8432 ((CHANNEL) == TIM_CHANNEL_2))) \ 8433 || \ 8434 (((INSTANCE) == TIM16) && \ 8435 (((CHANNEL) == TIM_CHANNEL_1))) \ 8436 || \ 8437 (((INSTANCE) == TIM17) && \ 8438 (((CHANNEL) == TIM_CHANNEL_1)))) 8439 8440 /****************** TIM Instances : supporting complementary output(s) ********/ 8441 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 8442 ((((INSTANCE) == TIM1) && \ 8443 (((CHANNEL) == TIM_CHANNEL_1) || \ 8444 ((CHANNEL) == TIM_CHANNEL_2) || \ 8445 ((CHANNEL) == TIM_CHANNEL_3))) \ 8446 || \ 8447 (((INSTANCE) == TIM15) && \ 8448 ((CHANNEL) == TIM_CHANNEL_1)) \ 8449 || \ 8450 (((INSTANCE) == TIM16) && \ 8451 ((CHANNEL) == TIM_CHANNEL_1)) \ 8452 || \ 8453 (((INSTANCE) == TIM17) && \ 8454 ((CHANNEL) == TIM_CHANNEL_1))) 8455 8456 /****************** TIM Instances : supporting counting mode selection ********/ 8457 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 8458 (((INSTANCE) == TIM1) || \ 8459 ((INSTANCE) == TIM2)) 8460 8461 /****************** TIM Instances : supporting repetition counter *************/ 8462 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 8463 (((INSTANCE) == TIM1) || \ 8464 ((INSTANCE) == TIM15) || \ 8465 ((INSTANCE) == TIM16) || \ 8466 ((INSTANCE) == TIM17)) 8467 8468 /****************** TIM Instances : supporting clock division *****************/ 8469 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 8470 (((INSTANCE) == TIM1) || \ 8471 ((INSTANCE) == TIM2) || \ 8472 ((INSTANCE) == TIM15) || \ 8473 ((INSTANCE) == TIM16) || \ 8474 ((INSTANCE) == TIM17)) 8475 8476 /****************** TIM Instances : supporting 2 break inputs *****************/ 8477 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\ 8478 ((INSTANCE) == TIM1) 8479 8480 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 8481 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\ 8482 ((INSTANCE) == TIM1) 8483 8484 /****************** TIM Instances : supporting DMA generation on Update events*/ 8485 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 8486 (((INSTANCE) == TIM1) || \ 8487 ((INSTANCE) == TIM2) || \ 8488 ((INSTANCE) == TIM6) || \ 8489 ((INSTANCE) == TIM15) || \ 8490 ((INSTANCE) == TIM16) || \ 8491 ((INSTANCE) == TIM17)) 8492 8493 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */ 8494 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 8495 (((INSTANCE) == TIM1) || \ 8496 ((INSTANCE) == TIM2) || \ 8497 ((INSTANCE) == TIM15) || \ 8498 ((INSTANCE) == TIM16) || \ 8499 ((INSTANCE) == TIM17)) 8500 8501 /****************** TIM Instances : supporting commutation event generation ***/ 8502 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 8503 (((INSTANCE) == TIM1) || \ 8504 ((INSTANCE) == TIM15) || \ 8505 ((INSTANCE) == TIM16) || \ 8506 ((INSTANCE) == TIM17)) 8507 8508 /****************** TIM Instances : supporting remapping capability ***********/ 8509 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ 8510 (((INSTANCE) == TIM2) || \ 8511 ((INSTANCE) == TIM16)) 8512 8513 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 8514 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \ 8515 (((INSTANCE) == TIM1)) 8516 8517 /****************************** TSC Instances *********************************/ 8518 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) 8519 8520 /******************** USART Instances : Synchronous mode **********************/ 8521 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 8522 ((INSTANCE) == USART2) || \ 8523 ((INSTANCE) == USART3)) 8524 8525 /****************** USART Instances : Auto Baud Rate detection ****************/ 8526 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 8527 8528 /******************** UART Instances : Asynchronous mode **********************/ 8529 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 8530 ((INSTANCE) == USART2) || \ 8531 ((INSTANCE) == USART3)) 8532 8533 /******************** UART Instances : Half-Duplex mode **********************/ 8534 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 8535 ((INSTANCE) == USART2) || \ 8536 ((INSTANCE) == USART3)) 8537 8538 /******************** UART Instances : LIN mode **********************/ 8539 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 8540 8541 /******************** UART Instances : Wake-up from Stop mode **********************/ 8542 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 8543 8544 /****************** UART Instances : Hardware Flow control ********************/ 8545 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 8546 ((INSTANCE) == USART2) || \ 8547 ((INSTANCE) == USART3)) 8548 8549 /****************** UART Instances : Driver Enable ****************************/ 8550 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 8551 ((INSTANCE) == USART2) || \ 8552 ((INSTANCE) == USART3)) 8553 8554 /********************* UART Instances : Smard card mode ***********************/ 8555 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 8556 8557 /*********************** UART Instances : IRDA mode ***************************/ 8558 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 8559 8560 /******************** UART Instances : Support of continuous communication using DMA ****/ 8561 #define IS_UART_DMA_INSTANCE(INSTANCE) (1) 8562 /****************************** WWDG Instances ********************************/ 8563 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 8564 8565 /** 8566 * @} 8567 */ 8568 8569 8570 /******************************************************************************/ 8571 /* For a painless codes migration between the STM32F3xx device product */ 8572 /* lines, the aliases defined below are put in place to overcome the */ 8573 /* differences in the interrupt handlers and IRQn definitions. */ 8574 /* No need to update developed interrupt code when moving across */ 8575 /* product lines within the same STM32F3 Family */ 8576 /******************************************************************************/ 8577 8578 /* Aliases for __IRQn */ 8579 #define ADC1_2_IRQn ADC1_IRQn 8580 #define COMP1_2_IRQn COMP2_IRQn 8581 #define COMP_IRQn COMP2_IRQn 8582 #define COMP1_2_3_IRQn COMP2_IRQn 8583 #define COMP4_5_6_IRQn COMP4_6_IRQn 8584 #define HRTIM1_FLT_IRQn I2C3_ER_IRQn 8585 #define HRTIM1_TIME_IRQn I2C3_EV_IRQn 8586 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn 8587 #define TIM18_DAC2_IRQn TIM1_CC_IRQn 8588 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn 8589 #define TIM16_IRQn TIM1_UP_TIM16_IRQn 8590 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn 8591 8592 8593 /* Aliases for __IRQHandler */ 8594 #define ADC1_2_IRQHandler ADC1_IRQHandler 8595 #define COMP1_2_IRQHandler COMP2_IRQHandler 8596 #define COMP_IRQHandler COMP2_IRQHandler 8597 #define COMP1_2_3_IRQHandler COMP2_IRQHandler 8598 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler 8599 #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler 8600 #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler 8601 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler 8602 #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler 8603 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 8604 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler 8605 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler 8606 8607 8608 #ifdef __cplusplus 8609 } 8610 #endif /* __cplusplus */ 8611 8612 #endif /* __STM32F301x8_H */ 8613 8614 /** 8615 * @} 8616 */ 8617 8618 /** 8619 * @} 8620 */ 8621
