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Searched refs:resets (Results 101 – 125 of 174) sorted by relevance

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/Zephyr-latest/dts/arm/st/n6/
Dstm32n6.dtsi437 resets = <&rctl STM32_RESET(APB2, 4)>;
446 resets = <&rctl STM32_RESET(APB1L, 17)>;
455 resets = <&rctl STM32_RESET(APB1L, 18)>;
464 resets = <&rctl STM32_RESET(APB1L, 19)>;
473 resets = <&rctl STM32_RESET(APB1L, 20)>;
482 resets = <&rctl STM32_RESET(APB2, 5)>;
491 resets = <&rctl STM32_RESET(APB1L, 30)>;
500 resets = <&rctl STM32_RESET(APB1L, 31)>;
509 resets = <&rctl STM32_RESET(APB2, 6)>;
518 resets = <&rctl STM32_RESET(APB2, 7)>;
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7b0.dtsi22 resets = <&rctl STM32_RESET(AHB2, 4U)>;
/Zephyr-latest/dts/arm/st/l0/
Dstm32l010Xb.dtsi30 resets = <&rctl STM32_RESET(APB2, 5U)>;
/Zephyr-latest/drivers/counter/
Dcounter_dw_timer.c57 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
315 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks) || DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets) in counter_dw_timer_init()
339 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets) in counter_dw_timer_init()
384 IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, resets), \
DKconfig.stm32_rtc21 bool "Save rtc time value between resets"
/Zephyr-latest/dts/arm/st/f4/
Dstm32f429.dtsi28 resets = <&rctl STM32_RESET(APB2, 26U)>;
Dstm32f446.dtsi38 resets = <&rctl STM32_RESET(APB1, 18U)>;
47 resets = <&rctl STM32_RESET(APB1, 19U)>;
56 resets = <&rctl STM32_RESET(APB1, 20U)>;
Dstm32f427.dtsi39 resets = <&rctl STM32_RESET(APB1, 30U)>;
48 resets = <&rctl STM32_RESET(APB1, 31U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4.dtsi219 resets = <&rctl STM32_RESET(APB2, 14U)>;
228 resets = <&rctl STM32_RESET(APB1L, 17U)>;
237 resets = <&rctl STM32_RESET(APB1H, 0U)>;
291 resets = <&rctl STM32_RESET(APB2, 11U)>;
308 resets = <&rctl STM32_RESET(APB1L, 0U)>;
330 resets = <&rctl STM32_RESET(APB1L, 4U)>;
346 resets = <&rctl STM32_RESET(APB2, 16U)>;
368 resets = <&rctl STM32_RESET(APB2, 17U)>;
/Zephyr-latest/dts/arm/st/wba/
Dstm32wba.dtsi245 resets = <&rctl STM32_RESET(APB2, 14U)>;
254 resets = <&rctl STM32_RESET(APB1L, 17U)>;
263 resets = <&rctl STM32_RESET(APB7, 6U)>;
316 resets = <&rctl STM32_RESET(APB2, 11U)>;
338 resets = <&rctl STM32_RESET(APB1L, 0U)>;
360 resets = <&rctl STM32_RESET(APB1L, 1U)>;
382 resets = <&rctl STM32_RESET(APB2, 17U)>;
403 resets = <&rctl STM32_RESET(APB2, 18U)>;
/Zephyr-latest/include/zephyr/drivers/
Dreset.h94 COND_CODE_1(DT_NODE_HAS_PROP(node_id, resets), \
143 COND_CODE_1(DT_PROP_HAS_IDX(DT_DRV_INST(inst), resets, idx), \
/Zephyr-latest/dts/arm/nxp/
Dnxp_rw6xx_common.dtsi225 resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
236 resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
247 resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
258 resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
269 resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
390 resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
423 resets = <&rstctl0 NXP_SYSCON_RESET(2, 26)>;
/Zephyr-latest/dts/arm/st/wl/
Dstm32wl.dtsi245 resets = <&rctl STM32_RESET(APB2, 14U)>;
254 resets = <&rctl STM32_RESET(APB1L, 17U)>;
263 resets = <&rctl STM32_RESET(APB1H, 0U)>;
373 resets = <&rctl STM32_RESET(APB2, 11U)>;
390 resets = <&rctl STM32_RESET(APB1L, 0U)>;
412 resets = <&rctl STM32_RESET(APB2, 17U)>;
434 resets = <&rctl STM32_RESET(APB2, 18U)>;
456 resets = <&rctl STM32_RESET(AHB3, 16U)>;
/Zephyr-latest/dts/arm/st/g0/
Dstm32g0.dtsi227 resets = <&rctl STM32_RESET(APB1H, 14U)>;
236 resets = <&rctl STM32_RESET(APB1L, 17U)>;
256 resets = <&rctl STM32_RESET(APB1H, 11U)>;
278 resets = <&rctl STM32_RESET(APB1L, 1U)>;
300 resets = <&rctl STM32_RESET(APB1H, 15U)>;
322 resets = <&rctl STM32_RESET(APB1H, 17U)>;
344 resets = <&rctl STM32_RESET(APB1H, 18U)>;
/Zephyr-latest/dts/arm/st/l1/
Dstm32l151Xc.dtsi26 resets = <&rctl STM32_RESET(APB1, 3U)>;
Dstm32l152Xc.dtsi26 resets = <&rctl STM32_RESET(APB1, 3U)>;
Dstm32l152Xe.dtsi26 resets = <&rctl STM32_RESET(APB1, 3U)>;
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l233rc.dtsi28 resets = <&rctl GD32_RESET_UART4>;
/Zephyr-latest/dts/arm/st/f3/
Dstm32f302.dtsi75 resets = <&rctl STM32_RESET(APB2, 11U)>;
92 resets = <&rctl STM32_RESET(APB1, 2U)>;
Dstm32f334.dtsi18 resets = <&rctl STM32_RESET(APB2, 11U)>;
/Zephyr-latest/dts/arm/st/wb/
Dstm32wb.dtsi258 resets = <&rctl STM32_RESET(APB2, 14U)>;
328 resets = <&rctl STM32_RESET(APB1H, 0U)>;
337 resets = <&rctl STM32_RESET(APB2, 11U)>;
354 resets = <&rctl STM32_RESET(APB1L, 0U)>;
376 resets = <&rctl STM32_RESET(APB2, 17U)>;
398 resets = <&rctl STM32_RESET(APB2, 18U)>;
518 resets = <&rctl STM32_RESET(AHB2, 16U)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi40 resets = <&rctl STM32_RESET(APB2, 7U)>;
/Zephyr-latest/tests/boot/test_mcuboot/
Dsysbuild.cmake22 # This order means that if the debugger resets the MCU in between flash
/Zephyr-latest/dts/arm/st/f0/
Dstm32f031.dtsi17 resets = <&rctl STM32_RESET(APB1, 0U)>;
/Zephyr-latest/dts/arm/st/c0/
Dstm32c071.dtsi17 resets = <&rctl STM32_RESET(APB1L, 0U)>;

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