1/*
2 * Copyright (c) 2021 Wouter Cappelle <wouter.cappelle@crodeon.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/l0/stm32l010.dtsi>
9
10/ {
11	sram0: memory@20000000 {
12		reg = <0x20000000 DT_SIZE_K(20)>;
13	};
14
15	soc {
16		eeprom: eeprom@8080000{
17			reg = <0x08080000 512>;
18		};
19
20		flash-controller@40022000 {
21			flash0: flash@8000000 {
22				reg = <0x08000000 DT_SIZE_K(128)>;
23			};
24		};
25
26		timers22: timers@40011400 {
27			compatible = "st,stm32-timers";
28			reg = <0x40011400 0x400>;
29			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
30			resets = <&rctl STM32_RESET(APB2, 5U)>;
31			interrupts = <22 0>;
32			interrupt-names = "global";
33			status = "disabled";
34
35			pwm {
36				compatible = "st,stm32-pwm";
37				status = "disabled";
38				#pwm-cells = <3>;
39			};
40		};
41	};
42};
43