Searched refs:cores (Results 101 – 125 of 158) sorted by relevance
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| /Zephyr-latest/boards/phytec/phyboard_nash/doc/ |
| D | index.rst | 15 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
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| /Zephyr-latest/boards/nordic/nrf54h20dk/doc/ |
| D | index.rst | 136 cores only, using :ref:`nordic_segger`.
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| /Zephyr-latest/boards/nxp/frdm_rw612/doc/ |
| D | index.rst | 20 - 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4
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| /Zephyr-latest/boards/amd/kv260_r5/doc/ |
| D | index.rst | 8 * Two independent R5 cores with their own TCMs (tightly coupled memories)
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| /Zephyr-latest/boards/toradex/verdin_imx8mp/doc/ |
| D | index.rst | 35 energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1
38 cores support both real-time trace through the ETM system and static debugging via JTAG.
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt11xx_cm4.dtsi | 17 * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
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| D | nxp_rt11xx_cm7.dtsi | 17 * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
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| /Zephyr-latest/boards/renesas/rcar_spider_s4/doc/ |
| D | rcar_spider_r52.rst | 15 | The software package supports the real-time cores with various drivers and basic software
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| /Zephyr-latest/samples/boards/renesas/openamp_linux_zephyr/ |
| D | README.rst | 5 Enable message exchange between two cores, with the application core running Linux
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| /Zephyr-latest/boards/nxp/lpcxpresso54114/doc/ |
| D | index.rst | 199 …ies-cortex-m4-mcus/low-power-microcontrollers-mcus-based-on-arm-cortex-m4-cores-with-optional-cort…
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| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/doc/ |
| D | index.rst | 34 - Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary
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| /Zephyr-latest/boards/nxp/rd_rw612_bga/doc/ |
| D | index.rst | 20 - 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4
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| /Zephyr-latest/boards/mediatek/ |
| D | index.rst | 25 These devices are Xtensa DSP cores, very similar to the Intel ADSP
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-1.8.rst | 294 * ``ZEP-2012`` - Fault in networking stack for cores that can't access unaligned memory
323 * ``ZEP-2152`` - Xtensa crashes on startup for cores with coprocessors
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| /Zephyr-latest/boards/nxp/imx93_evk/doc/ |
| D | index.rst | 12 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
366 They will only be aware of the cores they have been assigned through the config
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| /Zephyr-latest/boards/gaisler/gr716a_mini/doc/ |
| D | index.rst | 144 Use command 'info sys' to print a detailed report of attached cores
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| /Zephyr-latest/doc/services/ipc/ipc_service/backends/ |
| D | ipc_service_icmsg.rst | 27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
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| /Zephyr-latest/boards/st/stm32wb5mm_dk/doc/ |
| D | stm32wb5mm_dk.rst | 8 on the Arm |reg| Cortex |reg|-M4 and Arm |reg| Cortex |reg|-M0+ cores.
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| /Zephyr-latest/boards/phytec/phyboard_pollux/doc/ |
| D | index.rst | 10 the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one
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| /Zephyr-latest/dts/arm/raspberrypi/rpi_pico/ |
| D | rp2350.dtsi | 31 * define what kind of CPU cores they are.
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| /Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/doc/ |
| D | index.rst | 138 CM4 core working FW for both cores should be written into Flash. CM0+ FW
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| /Zephyr-latest/boards/arm/mps2/doc/ |
| D | mps2_an521.rst | 37 The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores
58 regions are shared across both cores, and are aliased in both secure and
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| /Zephyr-latest/boards/nxp/s32z2xxdc2/support/ |
| D | startup.cmm | 242 ; EnableR52_<core>_<rtu> - routines for waking up the RTU cores:
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| /Zephyr-latest/doc/connectivity/bluetooth/ |
| D | bluetooth-dev.rst | 55 configuration or if you have multiple cores in your SoC each running a different
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| /Zephyr-latest/boards/renesas/rzg3s_smarc/doc/ |
| D | index.rst | 99 RZ/G3S-EVKIT is designed to start different systems on different cores.
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