Searched refs:channel (Results 1126 – 1150 of 1368) sorted by relevance
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| /Zephyr-latest/boards/st/nucleo_g431rb/doc/ |
| D | index.rst | 43 …- 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generat…
77 - 12-channel DMA controller
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| /Zephyr-latest/boards/st/nucleo_g474re/doc/ |
| D | index.rst | 43 …- 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generat…
77 - 12-channel DMA controller
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| /Zephyr-latest/boards/microchip/mec1501modular_assy6885/doc/ |
| D | index.rst | 171 | 1 | 0 | Use eSPI Flash channel |
173 | | 1 | Use 3.3V Shared channel(R)|
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| /Zephyr-latest/dts/arm/st/f7/ |
| D | stm32f7.dtsi | 758 #io-channel-cells = <1>;
775 #io-channel-cells = <1>;
792 #io-channel-cells = <1>;
808 #io-channel-cells = <1>;
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| /Zephyr-latest/drivers/spi/ |
| D | spi_mcux_dspi.c | 477 uint32_t channel, int error_code) in dma_callback() argument
484 LOG_DBG("=dma call back @channel %d=", channel); in dma_callback()
491 if (channel == data->tx_dma_config.dma_channel) { in dma_callback()
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| /Zephyr-latest/boards/native/native_sim/ |
| D | native_sim.dts | 224 #io-channel-cells = <1>;
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| /Zephyr-latest/boards/firefly/roc_rk3568_pc/doc/ |
| D | index.rst | 69 This board configuration uses a single serial communication channel with the
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| /Zephyr-latest/dts/arm/st/f3/ |
| D | stm32f373.dtsi | 193 #io-channel-cells = <1>;
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| /Zephyr-latest/drivers/sensor/tdk/icm42688/ |
| D | icm42688_decoder.c | 17 static int icm42688_get_shift(enum sensor_channel channel, int accel_fs, int gyro_fs, int8_t *shift) in icm42688_get_shift() argument
19 switch (channel) { in icm42688_get_shift()
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_imx6sx_m4.dtsi | 446 #io-channel-cells = <1>;
460 #io-channel-cells = <1>;
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| /Zephyr-latest/boards/renesas/rcar_h3ulcb/doc/ |
| D | rcar_h3ulcb_r7.rst | 10 - The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit w…
172 When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector.
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| /Zephyr-latest/dts/arm/st/l1/ |
| D | stm32l1.dtsi | 223 #io-channel-cells = <1>;
239 #io-channel-cells = <1>;
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| /Zephyr-latest/doc/services/tracing/ |
| D | index.rst | 293 The main setting for the ITM stream port is the ITM port (0-31). A dedicated channel is needed
294 for Tracealyzer. Port 0 is usually reserved for printf logging, so channel 1 is used by default.
593 - The system has non-atomic write and one shared channel
600 thread+ISR to its own channel, thus alleviating races as each
605 - The system has atomic write but one shared channel
613 E.g. native_sim or board with multi-channel DMA. Lock-free.
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| /Zephyr-latest/doc/connectivity/bluetooth/api/ |
| D | hci.txt | 466 diagnostic channel type shall only supported when the feature bit is also set.
1379 | 0x00 to 0x27 | The index of the channel on which the|
1569 | 0x00 to 0x24 | The index of the data channel on |
1696 The vendor diagnostic channel allows for an independent side channel to provide
1705 The diagnostic channel provides multiplexing of diagnostic information based on
1706 a channel code. The channel parameters content depends on the channel code.
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| /Zephyr-latest/dts/arm/atmel/ |
| D | sam4s.dtsi | 231 #io-channel-cells = <1>;
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| /Zephyr-latest/doc/contribute/ |
| D | index.rst | 105 You may join our Discord_ channel or use the `Developer Mailing List`_.
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| /Zephyr-latest/boards/vngiotlab/nrf51_vbluno51/doc/ |
| D | index.rst | 38 + USB HID (DAP): CMSIS-DAP compliant debug channel.
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| /Zephyr-latest/drivers/espi/ |
| D | Kconfig.npcx | 42 Enabling an eSPI channel during an eSPI transaction might
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| /Zephyr-latest/boards/qemu/nios2/doc/ |
| D | index.rst | 49 This board configuration uses a single serial communication channel with the
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| /Zephyr-latest/subsys/net/l2/ieee802154/ |
| D | ieee802154_frame.h | 383 uint8_t channel; member
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| /Zephyr-latest/dts/arm/ti/ |
| D | cc13xx_cc26xx.dtsi | 240 #io-channel-cells = <1>;
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| /Zephyr-latest/boards/nordic/nrf9280pdk/ |
| D | nrf9280pdk_nrf9280_cpuapp.dts | 105 * Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2.
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| /Zephyr-latest/boards/nxp/imx8mn_evk/doc/ |
| D | index.rst | 78 This board configuration uses a single serial communication channel with the
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| /Zephyr-latest/dts/arm/st/l5/ |
| D | stm32l5.dtsi | 412 #io-channel-cells = <1>;
663 #io-channel-cells = <1>;
679 #io-channel-cells = <1>;
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| /Zephyr-latest/subsys/mgmt/osdp/src/ |
| D | osdp_common.h | 473 struct osdp_channel channel; member
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