1.. zephyr:board:: qemu_nios2
2
3Overview
4********
5
6This board configuration will use QEMU to emulate the Altera MAX 10 platform.
7
8This configuration provides support for an Altera Nios-II CPU and these devices:
9
10* Internal Interrupt Controller
11* Altera Avalon Timer
12* NS16550 UART
13
14.. note::
15   This board configuration makes no claims about its suitability for use
16   with an actual ti_lm3s6965 hardware system, or any other hardware system.
17
18Hardware
19********
20Supported Features
21==================
22
23The following hardware features are supported:
24
25+--------------+------------+----------------------+
26| Interface    | Controller | Driver/Component     |
27+==============+============+======================+
28| IIC          | on-chip    | Internal interrupt   |
29|              |            | controller           |
30+--------------+------------+----------------------+
31| NS16550      | on-chip    | serial port          |
32| UART         |            |                      |
33+--------------+------------+----------------------+
34| TIMER        | on-chip    | system clock         |
35+--------------+------------+----------------------+
36
37The kernel currently does not support other hardware features on this platform.
38
39Devices
40========
41System Clock
42------------
43
44This board configuration uses a system clock frequency of 50 MHz.
45
46Serial Port
47-----------
48
49This board configuration uses a single serial communication channel with the
50CPU's UART0.
51
52If SLIP networking is enabled (see below), an additional serial port will be
53used for it.
54
55Known Problems or Limitations
56==============================
57
58The following platform features are unsupported:
59
60* Memory protection through optional MPU.  However, using a XIP kernel
61  effectively provides TEXT/RODATA write protection in ROM.
62* Writing to the hardware's flash memory
63* Serial port in Direct Memory Access (DMA) mode
64* Serial Peripheral Interface (SPI) flash
65* General-Purpose Input/Output (GPIO)
66* Inter-Integrated Circuit (I2C)
67* Ethernet
68
69
70Programming and Debugging
71*************************
72
73Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
74emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
75
76.. zephyr-app-commands::
77   :zephyr-app: samples/synchronization
78   :host-os: unix
79   :board: qemu_nios2
80   :goals: run
81
82This will build an image with the synchronization sample app, boot it using
83QEMU, and display the following console output:
84
85.. code-block:: console
86
87        ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
88        threadA: Hello World from arm!
89        threadB: Hello World from arm!
90        threadA: Hello World from arm!
91        threadB: Hello World from arm!
92        threadA: Hello World from arm!
93        threadB: Hello World from arm!
94        threadA: Hello World from arm!
95        threadB: Hello World from arm!
96        threadA: Hello World from arm!
97        threadB: Hello World from arm!
98
99Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
100
101Debugging
102=========
103
104Refer to the detailed overview about :ref:`application_debugging`.
105
106Networking
107==========
108
109The board supports SLIP networking over an emulated serial port
110(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
111:ref:`networking_with_qemu`.
112
113References
114**********
115
116* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_
117* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_
118* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_
119* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_
120* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_
121* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_
122* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
123
124
125.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite
126