1/* 2 * Copyright (c) 2018, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv7-m.dtsi> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/rdc/imx_rdc.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-a9"; 21 reg = <0>; 22 status = "disabled"; 23 }; 24 25 cpu@1 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4f"; 28 reg = <1>; 29 }; 30 }; 31 32 /* TCML 0x1fff8000 is aliased at 0 */ 33 tcml:memory@0 { 34 compatible = "nxp,imx-itcm"; 35 reg = <0x00000000 DT_SIZE_K(32)>; 36 }; 37 38 tcmu:memory@20000000 { 39 compatible = "nxp,imx-dtcm"; 40 reg = <0x20000000 DT_SIZE_K(32)>; 41 }; 42 43 ocram_s:memory@208f8000 { 44 device_type = "memory"; 45 compatible = "nxp,imx-sys-bus"; 46 reg = <0x208f8000 DT_SIZE_K(16)>; 47 }; 48 49 ocram:memory@20900000 { 50 device_type = "memory"; 51 compatible = "nxp,imx-sys-bus"; 52 reg = <0x20900000 DT_SIZE_K(128)>; 53 }; 54 55 ddr:memory@80000000 { 56 device_type = "memory"; 57 compatible = "nxp,imx-sys-bus"; 58 reg = <0x80000000 0x60000000>; 59 }; 60 61 flash:memory@DT_FLASH_ADDR { 62 compatible = "soc-nv-flash"; 63 reg = <DT_ADDR(DT_FLASH_ADDR) DT_FLASH_SIZE>; 64 }; 65 66 sram:memory@DT_SRAM_ADDR { 67 reg = <DT_ADDR(DT_SRAM_ADDR) DT_SRAM_SIZE>; 68 }; 69 70 soc { 71 uart1:uart@42020000 { 72 compatible = "nxp,imx-uart"; 73 reg = <0x42020000 0x00004000>; 74 interrupts = <26 0>; 75 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 76 RDC_DOMAIN_PERM_RW)|\ 77 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 78 RDC_DOMAIN_PERM_RW))>; 79 status = "disabled"; 80 }; 81 82 uart2:uart@421e8000 { 83 compatible = "nxp,imx-uart"; 84 reg = <0x421e8000 0x00004000>; 85 interrupts = <27 0>; 86 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 87 RDC_DOMAIN_PERM_RW)|\ 88 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 89 RDC_DOMAIN_PERM_RW))>; 90 status = "disabled"; 91 }; 92 93 uart3:uart@421ec000 { 94 compatible = "nxp,imx-uart"; 95 reg = <0x421ec000 0x00004000>; 96 interrupts = <28 0>; 97 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 98 RDC_DOMAIN_PERM_RW)|\ 99 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 100 RDC_DOMAIN_PERM_RW))>; 101 status = "disabled"; 102 }; 103 104 uart4:uart@421f0000 { 105 compatible = "nxp,imx-uart"; 106 reg = <0x421f0000 0x00004000>; 107 interrupts = <29 0>; 108 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 109 RDC_DOMAIN_PERM_RW)|\ 110 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 111 RDC_DOMAIN_PERM_RW))>; 112 status = "disabled"; 113 }; 114 115 uart5:uart@421f4000 { 116 compatible = "nxp,imx-uart"; 117 reg = <0x421f4000 0x00004000>; 118 interrupts = <30 0>; 119 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 120 RDC_DOMAIN_PERM_RW)|\ 121 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 122 RDC_DOMAIN_PERM_RW))>; 123 status = "disabled"; 124 }; 125 126 uart6:uart@422a0000 { 127 compatible = "nxp,imx-uart"; 128 reg = <0x422a0000 0x00004000>; 129 interrupts = <17 0>; 130 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 131 RDC_DOMAIN_PERM_RW)|\ 132 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 133 RDC_DOMAIN_PERM_RW))>; 134 status = "disabled"; 135 }; 136 137 gpio1:gpio@4209c000 { 138 compatible = "nxp,imx-gpio"; 139 reg = <0x4209c000 0x4000>; 140 interrupts = <66 0>, <67 0>; 141 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 142 RDC_DOMAIN_PERM_RW)|\ 143 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 144 RDC_DOMAIN_PERM_RW))>; 145 gpio-controller; 146 #gpio-cells = <2>; 147 status = "disabled"; 148 }; 149 150 gpio2:gpio@420a0000 { 151 compatible = "nxp,imx-gpio"; 152 reg = <0x420a0000 0x4000>; 153 interrupts = <68 0>, <69 0>; 154 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 155 RDC_DOMAIN_PERM_RW)|\ 156 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 157 RDC_DOMAIN_PERM_RW))>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 status = "disabled"; 161 }; 162 163 gpio3:gpio@420a4000 { 164 compatible = "nxp,imx-gpio"; 165 reg = <0x420a4000 0x4000>; 166 interrupts = <70 0>, <71 0>; 167 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 168 RDC_DOMAIN_PERM_RW)|\ 169 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 170 RDC_DOMAIN_PERM_RW))>; 171 gpio-controller; 172 #gpio-cells = <2>; 173 status = "disabled"; 174 }; 175 176 gpio4:gpio@420a8000 { 177 compatible = "nxp,imx-gpio"; 178 reg = <0x420a8000 0x4000>; 179 interrupts = <72 0>, <73 0>; 180 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 181 RDC_DOMAIN_PERM_RW)|\ 182 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 183 RDC_DOMAIN_PERM_RW))>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 status = "disabled"; 187 }; 188 189 gpio5:gpio@420ac000 { 190 compatible = "nxp,imx-gpio"; 191 reg = <0x420ac000 0x4000>; 192 interrupts = <74 0>, <75 0>; 193 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 194 RDC_DOMAIN_PERM_RW)|\ 195 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 196 RDC_DOMAIN_PERM_RW))>; 197 gpio-controller; 198 #gpio-cells = <2>; 199 status = "disabled"; 200 }; 201 202 gpio6:gpio@420b0000 { 203 compatible = "nxp,imx-gpio"; 204 reg = <0x420b0000 0x4000>; 205 interrupts = <76 0>, <77 0>; 206 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 207 RDC_DOMAIN_PERM_RW)|\ 208 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 209 RDC_DOMAIN_PERM_RW))>; 210 gpio-controller; 211 #gpio-cells = <2>; 212 status = "disabled"; 213 }; 214 215 gpio7:gpio@420b4000 { 216 compatible = "nxp,imx-gpio"; 217 reg = <0x420b4000 0x4000>; 218 interrupts = <78 0>, <79 0>; 219 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 220 RDC_DOMAIN_PERM_RW)|\ 221 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 222 RDC_DOMAIN_PERM_RW))>; 223 gpio-controller; 224 #gpio-cells = <2>; 225 status = "disabled"; 226 }; 227 228 mub:mu@4229c000 { 229 compatible = "nxp,imx-mu"; 230 reg = <0x4229c000 0x4000>; 231 interrupts = <99 0>; 232 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 233 RDC_DOMAIN_PERM_RW)|\ 234 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 235 RDC_DOMAIN_PERM_RW))>; 236 status = "disabled"; 237 }; 238 239 epit1:epit@420d0000 { 240 compatible = "nxp,imx-epit"; 241 reg = <0x420d0000 0x4000>; 242 interrupts = <56 0>; 243 prescaler = <0>; 244 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 245 RDC_DOMAIN_PERM_RW)|\ 246 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 247 RDC_DOMAIN_PERM_RW))>; 248 status = "disabled"; 249 }; 250 251 iomuxc: iomuxc@420e0000 { 252 compatible = "nxp,imx-iomuxc"; 253 reg = <0x420e0000 0x4000>; 254 status = "okay"; 255 pinctrl: pinctrl { 256 status = "okay"; 257 /* iMX6 has same IOMUXC IP block as RT10xx series */ 258 compatible = "nxp,mcux-rt-pinctrl"; 259 }; 260 }; 261 262 epit2:epit@420d4000 { 263 compatible = "nxp,imx-epit"; 264 reg = <0x420d4000 0x4000>; 265 interrupts = <57 0>; 266 prescaler = <0>; 267 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 268 RDC_DOMAIN_PERM_RW)|\ 269 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 270 RDC_DOMAIN_PERM_RW))>; 271 status = "disabled"; 272 }; 273 274 i2c1: i2c@421a0000 { 275 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 276 clock-frequency = <I2C_BITRATE_STANDARD>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 reg = <0x421a0000 0x4000>; 280 interrupts = <36 0>; 281 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 282 RDC_DOMAIN_PERM_RW)|\ 283 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 284 RDC_DOMAIN_PERM_RW))>; 285 status = "disabled"; 286 }; 287 288 i2c2: i2c@421a4000 { 289 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 290 clock-frequency = <I2C_BITRATE_STANDARD>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 reg = <0x421a4000 0x4000>; 294 interrupts = <37 0>; 295 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 296 RDC_DOMAIN_PERM_RW)|\ 297 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 298 RDC_DOMAIN_PERM_RW))>; 299 status = "disabled"; 300 }; 301 302 i2c3: i2c@421a8000 { 303 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 304 clock-frequency = <I2C_BITRATE_STANDARD>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 reg = <0x421a8000 0x4000>; 308 interrupts = <38 0>; 309 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 310 RDC_DOMAIN_PERM_RW)|\ 311 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 312 RDC_DOMAIN_PERM_RW))>; 313 status = "disabled"; 314 }; 315 316 i2c4: i2c@421f8000 { 317 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 318 clock-frequency = <I2C_BITRATE_STANDARD>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 reg = <0x421f8000 0x4000>; 322 interrupts = <35 0>; 323 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 324 RDC_DOMAIN_PERM_RW)|\ 325 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 326 RDC_DOMAIN_PERM_RW))>; 327 status = "disabled"; 328 }; 329 330 pwm1: pwm@42080000 { 331 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 332 reg = <0x42080000 0x4000>; 333 interrupts = <83 0>; 334 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 335 RDC_DOMAIN_PERM_RW)|\ 336 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 337 RDC_DOMAIN_PERM_RW))>; 338 prescaler = <0>; 339 #pwm-cells = <2>; 340 status = "disabled"; 341 }; 342 343 pwm2: pwm@42084000 { 344 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 345 reg = <0x42084000 0x4000>; 346 interrupts = <84 0>; 347 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 348 RDC_DOMAIN_PERM_RW)|\ 349 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 350 RDC_DOMAIN_PERM_RW))>; 351 prescaler = <0>; 352 #pwm-cells = <2>; 353 status = "disabled"; 354 }; 355 356 pwm3: pwm@42088000 { 357 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 358 reg = <0x42088000 0x4000>; 359 interrupts = <85 0>; 360 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 361 RDC_DOMAIN_PERM_RW)|\ 362 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 363 RDC_DOMAIN_PERM_RW))>; 364 prescaler = <0>; 365 #pwm-cells = <2>; 366 status = "disabled"; 367 }; 368 369 pwm4: pwm@4208c000 { 370 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 371 reg = <0x4208c000 0x4000>; 372 interrupts = <86 0>; 373 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 374 RDC_DOMAIN_PERM_RW)|\ 375 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 376 RDC_DOMAIN_PERM_RW))>; 377 prescaler = <0>; 378 #pwm-cells = <2>; 379 status = "disabled"; 380 }; 381 382 383 pwm5: pwm@422a4000 { 384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 385 reg = <0x422a4000 0x4000>; 386 interrupts = <83 0>; 387 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 388 RDC_DOMAIN_PERM_RW)|\ 389 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 390 RDC_DOMAIN_PERM_RW))>; 391 prescaler = <0>; 392 #pwm-cells = <2>; 393 status = "disabled"; 394 }; 395 396 pwm6: pwm@422a8000 { 397 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 398 reg = <0x422a8000 0x4000>; 399 interrupts = <84 0>; 400 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 401 RDC_DOMAIN_PERM_RW)|\ 402 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 403 RDC_DOMAIN_PERM_RW))>; 404 prescaler = <0>; 405 #pwm-cells = <2>; 406 status = "disabled"; 407 }; 408 409 pwm7: pwm@422ac000 { 410 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 411 reg = <0x422ac000 0x4000>; 412 interrupts = <85 0>; 413 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 414 RDC_DOMAIN_PERM_RW)|\ 415 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 416 RDC_DOMAIN_PERM_RW))>; 417 prescaler = <0>; 418 #pwm-cells = <2>; 419 status = "disabled"; 420 }; 421 422 pwm8: pwm@422ab000 { 423 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 424 reg = <0x422ab000 0x4000>; 425 interrupts = <86 0>; 426 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 427 RDC_DOMAIN_PERM_RW)|\ 428 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 429 RDC_DOMAIN_PERM_RW))>; 430 prescaler = <0>; 431 #pwm-cells = <2>; 432 status = "disabled"; 433 }; 434 435 adc1: adc@42280000 { 436 compatible = "nxp,vf610-adc"; 437 reg = <0x42280000 0x4000>; 438 clk-source = <1>; 439 clk-divider = <2>; 440 interrupts = <100 0>; 441 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 442 RDC_DOMAIN_PERM_RW)|\ 443 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 444 RDC_DOMAIN_PERM_RW))>; 445 status = "disabled"; 446 #io-channel-cells = <1>; 447 }; 448 449 adc2: adc@42284000 { 450 compatible = "nxp,vf610-adc"; 451 reg = <0x42284000 0x4000>; 452 clk-source = <1>; 453 clk-divider = <2>; 454 interrupts = <101 0>; 455 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 456 RDC_DOMAIN_PERM_RW)|\ 457 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 458 RDC_DOMAIN_PERM_RW))>; 459 status = "disabled"; 460 #io-channel-cells = <1>; 461 }; 462 }; 463}; 464 465&nvic { 466 arm,num-irq-priority-bits = <4>; 467}; 468 469/* 470 * GPIO pinmux options. These options define the pinmux settings 471 * for GPIO ports on the package, so that the GPIO driver can 472 * select GPIO mux options during GPIO configuration. 473 */ 474 475&gpio1 { 476 pinmux = <&mx6sx_pad_gpio1_io00__gpio1_io_0>, 477 <&mx6sx_pad_gpio1_io01__gpio1_io_1>, 478 <&mx6sx_pad_gpio1_io02__gpio1_io_2>, 479 <&mx6sx_pad_gpio1_io03__gpio1_io_3>, 480 <&mx6sx_pad_gpio1_io04__gpio1_io_4>, 481 <&mx6sx_pad_gpio1_io05__gpio1_io_5>, 482 <&mx6sx_pad_gpio1_io06__gpio1_io_6>, 483 <&mx6sx_pad_gpio1_io07__gpio1_io_7>, 484 <&mx6sx_pad_gpio1_io08__gpio1_io_8>, 485 <&mx6sx_pad_gpio1_io09__gpio1_io_9>, 486 <&mx6sx_pad_gpio1_io10__gpio1_io_10>, 487 <&mx6sx_pad_gpio1_io11__gpio1_io_11>, 488 <&mx6sx_pad_gpio1_io12__gpio1_io_12>, 489 <&mx6sx_pad_gpio1_io13__gpio1_io_13>, 490 <&mx6sx_pad_csi_data00__gpio1_io_14>, 491 <&mx6sx_pad_csi_data01__gpio1_io_15>, 492 <&mx6sx_pad_csi_data02__gpio1_io_16>, 493 <&mx6sx_pad_csi_data03__gpio1_io_17>, 494 <&mx6sx_pad_csi_data04__gpio1_io_18>, 495 <&mx6sx_pad_csi_data05__gpio1_io_19>, 496 <&mx6sx_pad_csi_data06__gpio1_io_20>, 497 <&mx6sx_pad_csi_data07__gpio1_io_21>, 498 <&mx6sx_pad_csi_hsync__gpio1_io_22>, 499 <&mx6sx_pad_csi_mclk__gpio1_io_23>, 500 <&mx6sx_pad_csi_pixclk__gpio1_io_24>, 501 <&mx6sx_pad_csi_vsync__gpio1_io_25>; 502}; 503 504&gpio2 { 505 pinmux = <&mx6sx_pad_enet1_col__gpio2_io_0>, 506 <&mx6sx_pad_enet1_crs__gpio2_io_1>, 507 <&mx6sx_pad_enet1_mdc__gpio2_io_2>, 508 <&mx6sx_pad_enet1_mdio__gpio2_io_3>, 509 <&mx6sx_pad_enet1_rx_clk__gpio2_io_4>, 510 <&mx6sx_pad_enet1_tx_clk__gpio2_io_5>, 511 <&mx6sx_pad_enet2_col__gpio2_io_6>, 512 <&mx6sx_pad_enet2_crs__gpio2_io_7>, 513 <&mx6sx_pad_enet2_rx_clk__gpio2_io_8>, 514 <&mx6sx_pad_enet2_tx_clk__gpio2_io_9>, 515 <&mx6sx_pad_key_col0__gpio2_io_10>, 516 <&mx6sx_pad_key_col1__gpio2_io_11>, 517 <&mx6sx_pad_key_col2__gpio2_io_12>, 518 <&mx6sx_pad_key_col3__gpio2_io_13>, 519 <&mx6sx_pad_key_col4__gpio2_io_14>, 520 <&mx6sx_pad_key_row0__gpio2_io_15>, 521 <&mx6sx_pad_key_row1__gpio2_io_16>, 522 <&mx6sx_pad_key_row2__gpio2_io_17>, 523 <&mx6sx_pad_key_row3__gpio2_io_18>, 524 <&mx6sx_pad_key_row4__gpio2_io_19>; 525}; 526 527&gpio3 { 528 pinmux = <&mx6sx_pad_lcd1_clk__gpio3_io_0>, 529 <&mx6sx_pad_lcd1_data00__gpio3_io_1>, 530 <&mx6sx_pad_lcd1_data01__gpio3_io_2>, 531 <&mx6sx_pad_lcd1_data02__gpio3_io_3>, 532 <&mx6sx_pad_lcd1_data03__gpio3_io_4>, 533 <&mx6sx_pad_lcd1_data04__gpio3_io_5>, 534 <&mx6sx_pad_lcd1_data05__gpio3_io_6>, 535 <&mx6sx_pad_lcd1_data06__gpio3_io_7>, 536 <&mx6sx_pad_lcd1_data07__gpio3_io_8>, 537 <&mx6sx_pad_lcd1_data08__gpio3_io_9>, 538 <&mx6sx_pad_lcd1_data09__gpio3_io_10>, 539 <&mx6sx_pad_lcd1_data10__gpio3_io_11>, 540 <&mx6sx_pad_lcd1_data11__gpio3_io_12>, 541 <&mx6sx_pad_lcd1_data12__gpio3_io_13>, 542 <&mx6sx_pad_lcd1_data13__gpio3_io_14>, 543 <&mx6sx_pad_lcd1_data14__gpio3_io_15>, 544 <&mx6sx_pad_lcd1_data15__gpio3_io_16>, 545 <&mx6sx_pad_lcd1_data16__gpio3_io_17>, 546 <&mx6sx_pad_lcd1_data17__gpio3_io_18>, 547 <&mx6sx_pad_lcd1_data18__gpio3_io_19>, 548 <&mx6sx_pad_lcd1_data19__gpio3_io_20>, 549 <&mx6sx_pad_lcd1_data20__gpio3_io_21>, 550 <&mx6sx_pad_lcd1_data21__gpio3_io_22>, 551 <&mx6sx_pad_lcd1_data22__gpio3_io_23>, 552 <&mx6sx_pad_lcd1_data23__gpio3_io_24>, 553 <&mx6sx_pad_lcd1_enable__gpio3_io_25>, 554 <&mx6sx_pad_lcd1_hsync__gpio3_io_26>, 555 <&mx6sx_pad_lcd1_reset__gpio3_io_27>, 556 <&mx6sx_pad_lcd1_vsync__gpio3_io_28>; 557}; 558 559&gpio4 { 560 pinmux = <&mx6sx_pad_nand_ale__gpio4_io_0>, 561 <&mx6sx_pad_nand_ce0_b__gpio4_io_1>, 562 <&mx6sx_pad_nand_ce1_b__gpio4_io_2>, 563 <&mx6sx_pad_nand_cle__gpio4_io_3>, 564 <&mx6sx_pad_nand_data00__gpio4_io_4>, 565 <&mx6sx_pad_nand_data01__gpio4_io_5>, 566 <&mx6sx_pad_nand_data02__gpio4_io_6>, 567 <&mx6sx_pad_nand_data03__gpio4_io_7>, 568 <&mx6sx_pad_nand_data04__gpio4_io_8>, 569 <&mx6sx_pad_nand_data05__gpio4_io_9>, 570 <&mx6sx_pad_nand_data06__gpio4_io_10>, 571 <&mx6sx_pad_nand_data07__gpio4_io_11>, 572 <&mx6sx_pad_nand_re_b__gpio4_io_12>, 573 <&mx6sx_pad_nand_ready_b__gpio4_io_13>, 574 <&mx6sx_pad_nand_we_b__gpio4_io_14>, 575 <&mx6sx_pad_nand_wp_b__gpio4_io_15>, 576 <&mx6sx_pad_qspi1a_data0__gpio4_io_16>, 577 <&mx6sx_pad_qspi1a_data1__gpio4_io_17>, 578 <&mx6sx_pad_qspi1a_data2__gpio4_io_18>, 579 <&mx6sx_pad_qspi1a_data3__gpio4_io_19>, 580 <&mx6sx_pad_qspi1a_dqs__gpio4_io_20>, 581 <&mx6sx_pad_qspi1a_sclk__gpio4_io_21>, 582 <&mx6sx_pad_qspi1a_ss0_b__gpio4_io_22>, 583 <&mx6sx_pad_qspi1a_ss1_b__gpio4_io_23>, 584 <&mx6sx_pad_qspi1b_data0__gpio4_io_24>, 585 <&mx6sx_pad_qspi1b_data1__gpio4_io_25>, 586 <&mx6sx_pad_qspi1b_data2__gpio4_io_26>, 587 <&mx6sx_pad_qspi1b_data3__gpio4_io_27>, 588 <&mx6sx_pad_qspi1b_dqs__gpio4_io_28>, 589 <&mx6sx_pad_qspi1b_sclk__gpio4_io_29>, 590 <&mx6sx_pad_qspi1b_ss0_b__gpio4_io_30>, 591 <&mx6sx_pad_qspi1b_ss1_b__gpio4_io_31>; 592}; 593 594&gpio5 { 595 pinmux = <&mx6sx_pad_rgmii1_rd0__gpio5_io_0>, 596 <&mx6sx_pad_rgmii1_rd1__gpio5_io_1>, 597 <&mx6sx_pad_rgmii1_rd2__gpio5_io_2>, 598 <&mx6sx_pad_rgmii1_rd3__gpio5_io_3>, 599 <&mx6sx_pad_rgmii1_rx_ctl__gpio5_io_4>, 600 <&mx6sx_pad_rgmii1_rxc__gpio5_io_5>, 601 <&mx6sx_pad_rgmii1_td0__gpio5_io_6>, 602 <&mx6sx_pad_rgmii1_td1__gpio5_io_7>, 603 <&mx6sx_pad_rgmii1_td2__gpio5_io_8>, 604 <&mx6sx_pad_rgmii1_td3__gpio5_io_9>, 605 <&mx6sx_pad_rgmii1_tx_ctl__gpio5_io_10>, 606 <&mx6sx_pad_rgmii1_txc__gpio5_io_11>, 607 <&mx6sx_pad_rgmii2_rd0__gpio5_io_12>, 608 <&mx6sx_pad_rgmii2_rd1__gpio5_io_13>, 609 <&mx6sx_pad_rgmii2_rd2__gpio5_io_14>, 610 <&mx6sx_pad_rgmii2_rd3__gpio5_io_15>, 611 <&mx6sx_pad_rgmii2_rx_ctl__gpio5_io_16>, 612 <&mx6sx_pad_rgmii2_rxc__gpio5_io_17>, 613 <&mx6sx_pad_rgmii2_td0__gpio5_io_18>, 614 <&mx6sx_pad_rgmii2_td1__gpio5_io_19>, 615 <&mx6sx_pad_rgmii2_td2__gpio5_io_20>, 616 <&mx6sx_pad_rgmii2_td3__gpio5_io_21>, 617 <&mx6sx_pad_rgmii2_tx_ctl__gpio5_io_22>, 618 <&mx6sx_pad_rgmii2_txc__gpio5_io_23>; 619}; 620 621&gpio6 { 622 pinmux = <&mx6sx_pad_sd1_clk__gpio6_io_0>, 623 <&mx6sx_pad_sd1_cmd__gpio6_io_1>, 624 <&mx6sx_pad_sd1_data0__gpio6_io_2>, 625 <&mx6sx_pad_sd1_data1__gpio6_io_3>, 626 <&mx6sx_pad_sd1_data2__gpio6_io_4>, 627 <&mx6sx_pad_sd1_data3__gpio6_io_5>, 628 <&mx6sx_pad_sd2_clk__gpio6_io_6>, 629 <&mx6sx_pad_sd2_cmd__gpio6_io_7>, 630 <&mx6sx_pad_sd2_data0__gpio6_io_8>, 631 <&mx6sx_pad_sd2_data1__gpio6_io_9>, 632 <&mx6sx_pad_sd2_data2__gpio6_io_10>, 633 <&mx6sx_pad_sd2_data3__gpio6_io_11>, 634 <&mx6sx_pad_sd4_clk__gpio6_io_12>, 635 <&mx6sx_pad_sd4_cmd__gpio6_io_13>, 636 <&mx6sx_pad_sd4_data0__gpio6_io_14>, 637 <&mx6sx_pad_sd4_data1__gpio6_io_15>, 638 <&mx6sx_pad_sd4_data2__gpio6_io_16>, 639 <&mx6sx_pad_sd4_data3__gpio6_io_17>, 640 <&mx6sx_pad_sd4_data4__gpio6_io_18>, 641 <&mx6sx_pad_sd4_data5__gpio6_io_19>, 642 <&mx6sx_pad_sd4_data6__gpio6_io_20>, 643 <&mx6sx_pad_sd4_data7__gpio6_io_21>, 644 <&mx6sx_pad_sd4_reset_b__gpio6_io_22>; 645}; 646 647&gpio7 { 648 pinmux = <&mx6sx_pad_sd3_clk__gpio7_io_0>, 649 <&mx6sx_pad_sd3_cmd__gpio7_io_1>, 650 <&mx6sx_pad_sd3_data0__gpio7_io_2>, 651 <&mx6sx_pad_sd3_data1__gpio7_io_3>, 652 <&mx6sx_pad_sd3_data2__gpio7_io_4>, 653 <&mx6sx_pad_sd3_data3__gpio7_io_5>, 654 <&mx6sx_pad_sd3_data4__gpio7_io_6>, 655 <&mx6sx_pad_sd3_data5__gpio7_io_7>, 656 <&mx6sx_pad_sd3_data6__gpio7_io_8>, 657 <&mx6sx_pad_sd3_data7__gpio7_io_9>, 658 <&mx6sx_pad_usb_h_data__gpio7_io_10>, 659 <&mx6sx_pad_usb_h_strobe__gpio7_io_11>; 660}; 661
