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45 /* Flash segments (rodata and text) should be mapped in the virtual address spaces.50 /* Make sure new sections have consistent alignment between input and output sections */421 * iram0_0_seg and dram0_0_seg reflect the same address space on different buses.626 /* Provide total SRAM usage, including IRAM and DRAM */704 * because DROM and IROM regions share the same address space */
144 * The minimum residency and exit latency is172 * as BURTC clock for the system to not lose track of time and
154 * The minimum residency and exit latency is182 * as BURTC clock for the system to not lose track of time and
244 * control in a distributed way (GPIO registers and PSEL
246 * control in a distributed way (GPIO registers and PSEL
36 Enable STM32Cube Boot and Security Control (BSEC) HAL module driver173 Enable STM32Cube Extended interrupt and event controller (EXTI) HAL711 Enable STM32Cube Extended interrupt and event controller (EXTI) LL804 Enable STM32Cube Reset and Clock Control (RCC) LL module driver
260 #error RDP1 byte has to be different than RDP0 and RDP2 byte
1 /* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> */
215 * The flash starting at 0x000f8000 and ending at
19 # for Makefile generators and will be ignored by other generators.
49 * on nRF9160 DK. Instead, we have 2 buttons and 2 switches.
215 * The flash starting at 0x0007a000 and ending at
159 # configdefault with "prompt if <conditional==true>" and surrounding 'if'
41 /* As Apollo3blueplus datasheet, run_to_sleep and sleep_to_run53 * is the software overhead 1us and deepsleep_to_run transition
54 If enabled, OpenThread stack will have to be configured and56 Otherwise, OpenThread will configure the network parameters and try to
2 # removed, and various additions have been made as they've been discovered137 and and||and138 ang||and785 iff||if and only if
89 /* pwm pins for vmu and io ports */
101 The value is incremented every bit time and starts when the controller
199 /* The RTC peripheral backs the kernel system clock and tick timer. */
306 /* BKPSRAMEN and RAMCFGEN clock enable */745 * The SDMMC domain clock can be chosen between ICLK and PLL1P.747 * PLL1Q and MSIK.750 * ICLK comes in the future, the clock source for sdmmc1 and
92 * SAM3X doesn't support erase pages command and must
226 /* MX25R64 supports only pp and pp4io */
102 * configuration to pass PWM signal on pis 0 and 1. First valid config is P9.2.
238 * and pwm0 so disabled by default.
