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/Zephyr-latest/lib/hash/
DKconfig.hash_func3 # SPDX-License-Identifier: Apache-2.0
21 prompt "Default system-wide 32-bit hash function"
24 The default system-wide 32-bit hash function is sys_hash32().
27 bool "Default 32-bit hash is djb2"
31 bool "Default 32-bit hash is Murmur3"
35 bool "Default 32-bit hash is the identity"
37 This is the naive identity hash function. It only works for strings
38 either 1, 2, 4, or 8 bytes in length and so is suitable for scalar
39 values such as keys in a Hashmap. It is implemented as a static
/Zephyr-latest/include/zephyr/bluetooth/
Dbyteorder.h8 * SPDX-License-Identifier: Apache-2.0
26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
30 * @note @p _v is evaluated 2 times.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
44 * @note @p _v is evaluated 3 times.
46 * @param _v 24-bit integer in host endianness.
[all …]
/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
11 config: A 32bit mask specifying the DMA channel configuration
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
[all …]
Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
7 It is present on stm32 devices like stm32F4 or stm32F2.
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
18 which is device dependent. See stm32_dma.h:
[all …]
Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 config: A 32bit mask specifying the DMA channel configuration
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
[all …]
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
16 which is device dependent:
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
[all …]
Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 DMAMUX is a direct memory access multiplexer
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
14 which is device dependent:
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
[all …]
Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 It is present on stm32U5 devices as a GP DMA
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
24 which is device dependent:
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/Zephyr-latest/dts/bindings/sensor/
Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
29 1 = 32 V FSR
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
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/Zephyr-latest/include/zephyr/arch/common/
Dffs.h5 * SPDX-License-Identifier: Apache-2.0
21 * @brief find most significant bit set in a 32-bit word
23 * This routine finds the first bit set starting from the most significant bit
24 * in the argument passed in and returns the index of that bit. Bits are
25 * numbered starting at 1 from the least significant bit. A return value of
26 * zero indicates that the value passed is zero.
28 * @return most significant bit set, 0 if @a op is 0
37 return 32 - __builtin_clz(op); in find_msb_set()
43 * @brief find least significant bit set in a 32-bit word
45 * This routine finds the first bit set starting from the least significant bit
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
35 * 32768 Hz period is 30.518 us
36 * HW count resolution is 48 MHz.
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
47 #define CLK32K_FLAG_CRYSTAL_SE BIT(0)
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/Zephyr-latest/include/zephyr/sys/
Dsys_io.h6 * SPDX-License-Identifier: Apache-2.0
69 * @brief Output 32 bits to an I/O port
71 * This function writes 32 bits to the given port.
73 * @param data the 32 bits to write
74 * @param port the port address where to write the 32 bits
79 * @brief Input 32 bits from an I/O port
81 * This function reads 32 bits from the port.
83 * @param port the port address from where to read the 32 bits
85 * @return the 32 bits read
89 * @fn static inline void sys_io_set_bit(io_port_t port, unsigned int bit)
[all …]
/Zephyr-latest/include/zephyr/arch/arc/asm-compat/
Dassembler.h1 /* SPDX-License-Identifier: Apache-2.0 */
7 * Top level include file providing ISA pseudo-mnemonics for use in assembler
10 * - Helps code reuse across ARC64/ARC32/ARCv2
11 * e.g. "LDR" maps to 'LD' on 32-bit ISA, 'LDL' on 64-bit ARCv2/ARC64
13 * - Provides emulation with multiple instructions if the case be
16 * - Looks more complex than it really is: mainly because Kconfig defines
17 * are not "honored" in inline assembly. So each variant is unconditional
34 #include "asm-macro-64-bit-mwdt.h"
36 #include "asm-macro-64-bit-gnu.h"
45 #include "asm-macro-32-bit-mwdt.h"
[all …]
/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2015-2021, Linaro Limited
11 * This file is exported by OP-TEE and is in kept in sync between secure
70 * Normal cached memory (write-back), shareable for SMP systems and not
76 * a0..a7 is used as register names in the descriptions below, on arm32
78 * 32-bit registers.
86 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
110 * Used by non-secure world to figure out which Trusted OS is installed.
111 * Note that returned UUID is the UUID of the Trusted OS, not of the API.
113 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
[all …]
/Zephyr-latest/doc/kernel/services/other/
Datomic.rst6 An :dfn:`atomic variable` is one that can be read and modified
7 by threads and ISRs in an uninterruptible manner. It is a 32-bit variable on
8 32-bit machines and a 64-bit variable on 64-bit machines.
23 The kernel also supports the atomic manipulation of a single bit
32 An atomic variable is defined using a variable of type :c:type:`atomic_t`.
34 By default an atomic variable is initialized to zero. However, it can be given
37 .. code-block:: c
44 An atomic variable is manipulated using the APIs listed at the end of
48 of the number of times a function has been invoked. Since the count is
49 incremented atomically, there is no risk that it will become corrupted
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/Zephyr-latest/arch/posix/
DLinux.aarch64.cmake1 # SPDX-License-Identifier: Apache-2.0
3 # For Aarch64, multilib is not an actively pursued solution for most Linux
4 # distributions. Userspace is (generally) either 32-bit or 64-bit but not
18 if (${WORDSIZE} STREQUAL "32")
20 "CONFIG_64BIT=y but this Aarch64 machine has a 32-bit userspace.\n"
25 zephyr_compile_options(-fPIC)
29 "CONFIG_64BIT=n but this Aarch64 machine has a 64-bit userspace.\n"
/Zephyr-latest/boards/native/native_posix/doc/
Dindex.rst15 ``native_posix`` is deprecated in favour of :ref:`native_sim<native_sim>`, and will be removed
21 which will set its configuration to mimic a native_posix-like configuration.
23 ``native_posix`` is the predecessor of :ref:`native_sim<native_sim>`.
53 Moreover, being limited to build only with the host C library, it is not possible to build
64 .. zephyr-app-commands::
65 :zephyr-app: samples/hello_world
66 :host-os: unix
80 32 and 64bit versions
84 A 32 bit and 64 bit version.
85 The 32 bit version, ``native_posix``, is the default target, which will compile
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
D__arithmetic.S3 * SPDX-License-Identifier: Apache-2.0
5 * When the 'M' extension is disabled, compiler can not recognize div/mul
28 .size \func, .-\func
31 /* signed 32 bit multiplication. opcode of mul a0,a0,a1 is 0x02b50533 */
34 /* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */
37 /* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */
42 * opcode of rem a0,a0,a1 is 0x02b56533
48 * opcode of remu a0,a0,a1 is 0x02b57533
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dtimer.h4 * SPDX-License-Identifier: Apache-2.0
34 #define TIMER_IRQ_ENABLE BIT(2)
35 #define TIMER_COMP_ENABLE BIT(1)
36 #define TIMER_ENABLE BIT(0)
38 #define TIMER_ISR_EVENT_FLAG BIT(0)
52 uint32_t upper = (uint32_t)(val >> 32); in arm_arch_timer_set_compare()
71 * R/W access to the event flag register is required for the timer errata
72 * 740657 workaround -> comp. ISR implementation in arm_arch_timer.c.
73 * This functionality is not present in the aarch64 implementation of the
76 * comp. ARM Cortex-A9 processors Software Developers Errata Notice,
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/Zephyr-latest/drivers/timer/
DKconfig.mec52 # SPDX-License-Identifier: Apache-2.0
14 The 32-bit 32 KHz based RTOS timer which is operational in
15 full power and deep sleep. Basic timer 5 is a 48 MHz based
16 32-bit down counter with frequency divider used for the
/Zephyr-latest/arch/arm64/core/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
18 This option signifies the use of a CPU of the Cortex-A family.
31 This option signifies the use of a CPU of the Cortex-R 64-bit family.
38 This option signifies the use of a Cortex-A53 CPU
45 This option signifies the use of a Cortex-A55 CPU
52 This option signifies the use of a Cortex-A57 CPU
59 This option signifies the use of a Cortex-A72 CPU
66 This option signifies the use of a Cortex-A76 CPU
73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
80 This option signifies the use of a Cortex-R82 CPU
[all …]
/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
24 uint32_t r = pcr->PWR_RST_STS; in pcr_clock_regs()
28 LOG_INF("PCR Power Reset Status register(bit[10] is 32K_ACTIVE) = 0x%x", r); in pcr_clock_regs()
30 r = pcr->OSC_ID; in pcr_clock_regs()
31 LOG_INF("PCR Oscillator ID register(bit[8]=PLL Lock) = 0x%x", r); in pcr_clock_regs()
33 r = pcr->PROC_CLK_CTRL; in pcr_clock_regs()
36 r = pcr->SLOW_CLK_CTRL; in pcr_clock_regs()
43 uint32_t cken = vbr->CLK32_EN; in vbat_clock_regs()
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwmbbled.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
20 description: Array of pairs of GIRQ number and bit position
25 description: BBLED PCR register index and bit position
27 clock-select:
31 Clock source selection: 32 KHz is available in deep sleep.
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
35 - "PWM_BBLED_CLK_32K"
[all …]
/Zephyr-latest/include/zephyr/arch/x86/
Dmsr.h3 * SPDX-License-Identifier: Apache-2.0
16 #define X86_SPEC_CTRL_MSR_IBRS BIT(0)
17 #define X86_SPEC_CTRL_MSR_SSBD BIT(2)
20 #define X86_APIC_BASE_MSR_X2APIC BIT(10)
23 #define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)
28 #define X86_EFER_MSR_SCE BIT(0)
29 #define X86_EFER_MSR_LME BIT(8)
30 #define X86_EFER_MSR_NXE BIT(11)
33 * 47:32 Kernel CS (SS = CS+8)
41 /* Low 32 bits in this MSR are the SYSCALL mask applied to EFLAGS */
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_vbat.h4 * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
26 #define MCHP_VBATR_PFRS_SYS_RST BIT(2)
27 #define MCHP_VBATR_PFRS_JTAG BIT(3)
28 #define MCHP_VBATR_PFRS_RESETI BIT(4)
29 #define MCHP_VBATR_PFRS_WDT BIT(5)
30 #define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6)
31 #define MCHP_VBATR_PFRS_VBAT_RST BIT(7)
33 /* Offset 0x08 32K Clock Source register */
44 /* Enable and start internal 32KHz Silicon Oscillator */
[all …]

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