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Searched +full:clock +full:- +full:mult (Results 1 – 17 of 17) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
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Dfixed-factor-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Generic fixed factor clock provider
6 compatible: "fixed-factor-clock"
8 include: clock-controller.yaml
11 clock-div:
13 description: fixed clock divider
15 clock-mult:
17 description: fixed clock multiplier
20 type: phandle-array
21 description: input clock source
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/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1160.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 clock-mult = <100>;
10 clock-div = <4>;
Dnxp_rt1170.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 clock-mult = <83>;
10 clock-div = <2>;
Dnxp_ke1xf.dtsi2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
20 zephyr,flash-controller = &ftfe;
24 #address-cells = <1>;
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Dnxp_rt11xx.dtsi2 * Copyright 2021,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/power/imx_spc.h>
15 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
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/Zephyr-latest/boards/google/twinkie_v2/
Dgoogle_twinkie_v2.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g0b1r(b-c-e)ixn-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "google,twinkie-v2";
22 compatible = "gpio-leds";
35 compatible = "gpio-keys";
47 compatible = "voltage-divider";
48 io-channels = <&adc1 1>;
49 output-ohms = <2000000000>;
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/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "litex,vexriscv", "litex-dev";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clock-frequency = <100000000>;
25 compatible = "litex,vexriscv-standard", "riscv";
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/Zephyr-latest/boards/microchip/ev11l78a/
Dev11l78a.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
12 #include "ev11l78a-pinctrl.dtsi"
26 zephyr,shell-uart = &sercom1;
32 compatible = "gpio-leds";
40 compatible = "current-sense-amplifier";
41 io-channels = <&adc 5>;
42 sense-resistor-milli-ohms = <4>;
43 sense-gain-mult = <100>;
49 clock-frequency = <DT_FREQ_M(48)>;
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
39 /* Core clock frequency: 198000000Hz */
49 /* OSC clock */
59 /* OSC clock */
69 .num = 0, .sfg_clock_src = kCLOCK_FrgPllDiv, .divider = 255U, .mult = 0};
72 .num = 12, .sfg_clock_src = kCLOCK_FrgMainClk, .divider = 255U, .mult = 167};
81 /* System clock frequency. */
152 /* enable usb ip clock */ in usb_device_clock_init()
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/Zephyr-latest/boards/nxp/twr_ke18f/
Dtwr_ke18f.dts2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include "twr_ke18f-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
27 pwm-led0 = &orange_pwm_led;
28 pwm-led1 = &yellow_pwm_led;
29 pwm-led2 = &green_pwm_led;
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/Zephyr-latest/drivers/sdhc/
Dsdhc_renesas_ra.c4 * SPDX-License-Identifier: Apache-2.0
97 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_get_card_present()
103 fsp_err = R_SDHI_StatusGet(&priv->sdmmc_ctrl, &status); in sdhc_ra_get_card_present()
114 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_card_busy()
119 fsp_err = R_SDHI_StatusGet(&priv->sdmmc_ctrl, &status); in sdhc_ra_card_busy()
146 fsp_err = sdhi_command_send_wait(&priv->sdmmc_ctrl, ra_cmd->opcode, ra_cmd->arg, in sdhc_ra_send_cmd()
147 ra_cmd->timeout_ms); in sdhc_ra_send_cmd()
149 retries--; /* error, retry */ in sdhc_ra_send_cmd()
163 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_request()
164 int retries = (int)(cmd->retries + 1); /* first try plus retries */ in sdhc_ra_request()
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/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
34 /* System Clock configuration */
36 "Invalid SCG slow clock divider value");
38 "Invalid SCG bus clock divider value");
40 /* Core divider range is 1 to 4 with SPLL as clock source */
42 "Invalid SCG core clock divider value");
45 "Invalid SCG core clock divider value");
60 #error Invalid SCG core clock source
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/Zephyr-latest/drivers/clock_control/
Dclock_control_lpc11u6x.c4 * SPDX-License-Identifier: Apache-2.0
21 syscon->pd_run_cfg = (syscon->pd_run_cfg & ~bit) in syscon_power_up()
24 syscon->pd_run_cfg = syscon->pd_run_cfg | bit in syscon_power_up()
32 syscon->sys_pll_clk_sel = src; in syscon_set_pll_src()
33 syscon->sys_pll_clk_uen = 0; in syscon_set_pll_src()
34 syscon->sys_pll_clk_uen = 1; in syscon_set_pll_src()
51 syscon->sys_pll_ctrl = val; in syscon_setup_pll()
56 return (syscon->sys_pll_stat & 0x1) != 0; in syscon_pll_locked()
62 syscon->main_clk_sel = src; in syscon_set_main_clock_source()
63 syscon->main_clk_uen = 0; in syscon_set_main_clock_source()
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/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.c2 * Copyright 2021-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
33 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA), \
72 "ARM PLL must have clock-mult property");
74 "ARM PLL must have clock-div property");
161 * @brief Initialize the system clock
174 if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { in clock_init()
190 if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & in clock_init()
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/Zephyr-latest/doc/releases/
Dmigration-guide-4.0.rst39 to define default flash and ram partitioning based on TF-M.
60 specify it using the west ``--runner`` or ``-r`` option. (:github:`75284`)
61 * ADC: Domain clock needs to be explicitly defined if property st,adc-clock-source = <ASYNC> is use…
85 Trusted Firmware-M
130 Chip variants with open-drain outputs (``mcp23x09``, ``mcp23x18``) now correctly reflect this in
134 * The ``power-domain`` property has been removed in favor of ``power-domains``.
136 ``power-domain-names`` is also available to optionally name each entry in
137 ``power-domains``. The number of cells in the ``power-domains`` property need
138 to be defined using ``#power-domain-cells``.
143 * For all STM32 ADC that selects an asynchronous clock through ``st,adc-clock-source`` property,
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/Zephyr-latest/soc/altr/zephyr_nios2f/cpu/
Dghrd_10m50da.sopcinfo1 <?xml version="1.0" encoding="UTF-8"?>
3 <!-- Format version 17.0 595 (Future versions may contain additional information.) -->
4 <!-- 2017.12.05.14:35:53 -->
5 <!-- A collection of modules and connections -->
53 <value>-1</value>
63 <value>-1</value>
73 <value>-1</value>
103 <!-- Describes a single module. Module parameters are
104 the requested settings for a module instance. -->
127 <value>altr,16550-FIFO64 ns16550a</value>
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