2  * Copyright 2021-2024 NXP
4  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
33 	memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA),                             \
72 	     "ARM PLL must have clock-mult property");
74 	     "ARM PLL must have clock-div property");
161  * @brief Initialize the system clock
174 	if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) {  in clock_init()
190 	if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &  in clock_init()
196 	if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &  in clock_init()
210 	ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;  in clock_init()
221 	ANADIG_OSC->OSC_24M_CTRL |=  in clock_init()
228 	       (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {  in clock_init()
255 	 * If DCD is used, please make sure the clock source of SEMC is not  in clock_init()
311 	/* Module clock root configurations. */  in clock_init()
332 	/* Keep root bus clock at default 240M */  in clock_init()
337 	/* Configure root bus clock at 198M */  in clock_init()
413 	/* 50 MHz ENET clock */  in clock_init()
419 	IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U);  in clock_init()
420 	IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U);  in clock_init()
423 	IOMUXC_GPR->GPR4 |=  in clock_init()
430 	/* 125 MHz ENET1G clock */  in clock_init()
434 	IOMUXC_GPR->GPR5 = (IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(0x01U) |  in clock_init()
435 			    (IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x01U)));  in clock_init()
437 	IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);  in clock_init()
440 	 * 50 MHz clock for 10/100Mbit RMII PHY -  in clock_init()
447 	IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);  in clock_init()
448 	IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U);  in clock_init()
451 	IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) |  in clock_init()
459 	/* 24MHz PTP clock */  in clock_init()
473 	/* MIPI CSI-2 Rx connects to CSI via Video Mux */  in clock_init()
475 	VIDEO_MUX->VID_MUX_CTRL.SET = VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK;  in clock_init()
477 	/* Enable power domain for MIPI CSI-2 */  in clock_init()
478 	PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK |  in clock_init()
509 	 * PLL2 is fixed at 528MHz. Use desired panel clock clock to  in clock_init()
510 	 * calculate LCDIF clock.  in clock_init()
570 	/* Keep core clock ungated during WFI */  in clock_init()
571 	CCM->GPR_PRIVATE1_SET = 0x1;  in clock_init()
572 	/* Keep the system clock running so SYSTICK can wake up the system from  in clock_init()
581 	/* Enable the AHB clock while the CM7 is sleeping to allow debug access  in clock_init()
584 	IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK;  in clock_init()
622 	VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK;  in imxrt_pre_init_display_interface()
625 	PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK |  in imxrt_pre_init_display_interface()
629 	IOMUXC_GPR->GPR62 &= ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK |  in imxrt_pre_init_display_interface()
634 	/* setup clock */  in imxrt_pre_init_display_interface()
643 	/* TX esc clock */  in imxrt_pre_init_display_interface()
661 	IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK |  in imxrt_pre_init_display_interface()
668 	IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK |  in imxrt_post_init_display_interface()
692 		return -EINVAL;  in mipi_csi2rx_clock_set_freq()
698 		LOG_ERR("Requested rate is higher than the maximum clock frequency");  in mipi_csi2rx_clock_set_freq()
699 		return -EINVAL;  in mipi_csi2rx_clock_set_freq()
736 	IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(boot_address >> 3u);  in imxrt_init()
737 	IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(boot_address >> 16u);  in imxrt_init()
750 	/* Initialize system clock */  in imxrt_init()
797 	SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK;  in second_core_boot()
798 	SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK;  in second_core_boot()