4  * SPDX-License-Identifier: Apache-2.0
21 		syscon->pd_run_cfg = (syscon->pd_run_cfg & ~bit)  in syscon_power_up()
24 		syscon->pd_run_cfg = syscon->pd_run_cfg | bit  in syscon_power_up()
32 	syscon->sys_pll_clk_sel = src;  in syscon_set_pll_src()
33 	syscon->sys_pll_clk_uen = 0;  in syscon_set_pll_src()
34 	syscon->sys_pll_clk_uen = 1;  in syscon_set_pll_src()
51 	syscon->sys_pll_ctrl = val;  in syscon_setup_pll()
56 	return (syscon->sys_pll_stat & 0x1) != 0;  in syscon_pll_locked()
62 	syscon->main_clk_sel = src;  in syscon_set_main_clock_source()
63 	syscon->main_clk_uen = 0;  in syscon_set_main_clock_source()
64 	syscon->main_clk_uen = 1;  in syscon_set_main_clock_source()
71 		syscon->sys_ahb_clk_ctrl |= mask;  in syscon_ahb_clock_enable()
73 		syscon->sys_ahb_clk_ctrl &= ~mask;  in syscon_ahb_clock_enable()
81 		syscon->p_reset_ctrl &= ~mask;  in syscon_peripheral_reset()
83 		syscon->p_reset_ctrl |= mask;  in syscon_peripheral_reset()
94 	syscon->frg_clk_div = div;  in syscon_frg_init()
97 	syscon->uart_frg_div = 0xFF;  in syscon_frg_init()
98 	syscon->uart_frg_mult = ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / div)  in syscon_frg_init()
104 	syscon->uart_frg_div = 0x0;  in syscon_frg_deinit()
111 	const struct lpc11u6x_syscon_config *cfg = dev->config;  in lpc11u6x_clock_control_on()
112 	struct lpc11u6x_syscon_data *data = dev->data;  in lpc11u6x_clock_control_on()
116 	k_mutex_lock(&data->mutex, K_FOREVER);  in lpc11u6x_clock_control_on()
132 		cfg->syscon->usart0_clk_div = 1;  in lpc11u6x_clock_control_on()
136 		if (!data->frg_in_use++) {  in lpc11u6x_clock_control_on()
143 		if (!data->frg_in_use++) {  in lpc11u6x_clock_control_on()
150 		if (!data->frg_in_use++) {  in lpc11u6x_clock_control_on()
153 		data->usart34_in_use++;  in lpc11u6x_clock_control_on()
158 		if (!data->frg_in_use++) {  in lpc11u6x_clock_control_on()
161 		data->usart34_in_use++;  in lpc11u6x_clock_control_on()
166 		k_mutex_unlock(&data->mutex);  in lpc11u6x_clock_control_on()
167 		return -EINVAL;  in lpc11u6x_clock_control_on()
170 	syscon_ahb_clock_enable(cfg->syscon, clk_mask, true);  in lpc11u6x_clock_control_on()
172 		syscon_frg_init(cfg->syscon);  in lpc11u6x_clock_control_on()
174 	syscon_peripheral_reset(cfg->syscon, reset_mask, false);  in lpc11u6x_clock_control_on()
175 	k_mutex_unlock(&data->mutex);  in lpc11u6x_clock_control_on()
183 	const struct lpc11u6x_syscon_config *cfg = dev->config;  in lpc11u6x_clock_control_off()
184 	struct lpc11u6x_syscon_data *data = dev->data;  in lpc11u6x_clock_control_off()
188 	k_mutex_lock(&data->mutex, K_FOREVER);  in lpc11u6x_clock_control_off()
204 		cfg->syscon->usart0_clk_div = 0;  in lpc11u6x_clock_control_off()
208 		if (!(--data->frg_in_use)) {  in lpc11u6x_clock_control_off()
215 		if (!(--data->frg_in_use)) {  in lpc11u6x_clock_control_off()
222 		if (!(--data->frg_in_use)) {  in lpc11u6x_clock_control_off()
225 		if (!(--data->usart34_in_use)) {  in lpc11u6x_clock_control_off()
231 		if (!(--data->frg_in_use)) {  in lpc11u6x_clock_control_off()
234 		if (!(--data->usart34_in_use)) {  in lpc11u6x_clock_control_off()
240 		k_mutex_unlock(&data->mutex);  in lpc11u6x_clock_control_off()
241 		return -EINVAL;  in lpc11u6x_clock_control_off()
244 	syscon_ahb_clock_enable(cfg->syscon, clk_mask, false);  in lpc11u6x_clock_control_off()
246 		syscon_frg_deinit(cfg->syscon);  in lpc11u6x_clock_control_off()
248 	syscon_peripheral_reset(cfg->syscon, reset_mask, true);  in lpc11u6x_clock_control_off()
249 	k_mutex_unlock(&data->mutex);  in lpc11u6x_clock_control_off()
272 		return -EINVAL;  in lpc11u6x_clock_control_get_rate()
279 	const struct lpc11u6x_syscon_config *cfg = dev->config;  in lpc11u6x_syscon_init()
280 	struct lpc11u6x_syscon_data *data = dev->data;  in lpc11u6x_syscon_init()
283 	k_mutex_init(&data->mutex);  in lpc11u6x_syscon_init()
284 	data->frg_in_use = 0;  in lpc11u6x_syscon_init()
285 	data->usart34_in_use = 0;  in lpc11u6x_syscon_init()
295 	/* Enable IOCON (I/O Control) clock. */  in lpc11u6x_syscon_init()
298 	syscon_ahb_clock_enable(cfg->syscon, val, true);  in lpc11u6x_syscon_init()
300 	/* Configure PLL output as the main clock source, with a frequency of  in lpc11u6x_syscon_init()
304 	syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_SYSOSC_PD, true);  in lpc11u6x_syscon_init()
311 	syscon_set_pll_src(cfg->syscon, LPC11U6X_SYS_PLL_CLK_SEL_SYSOSC);  in lpc11u6x_syscon_init()
313 	pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);  in lpc11u6x_syscon_init()
316 	syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_IRC_PD, true);  in lpc11u6x_syscon_init()
317 	syscon_set_pll_src(cfg->syscon, LPC11U6X_SYS_PLL_CLK_SEL_IRC);  in lpc11u6x_syscon_init()
319 	/* Flash access takes 3 clock cycles for main clock frequencies  in lpc11u6x_syscon_init()
324 	/* Shutdown PLL to change divider/mult ratios */  in lpc11u6x_syscon_init()
325 	syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_PLL_PD, false);  in lpc11u6x_syscon_init()
328 	syscon_setup_pll(cfg->syscon, 3, 1);  in lpc11u6x_syscon_init()
331 	syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_PLL_PD, true);  in lpc11u6x_syscon_init()
333 	while (!syscon_pll_locked(cfg->syscon)) {  in lpc11u6x_syscon_init()
336 	cfg->syscon->sys_ahb_clk_div = 1;  in lpc11u6x_syscon_init()
337 	syscon_set_main_clock_source(cfg->syscon, LPC11U6X_MAIN_CLK_SRC_PLLOUT);  in lpc11u6x_syscon_init()