Lines Matching +full:clock +full:- +full:mult
4 * SPDX-License-Identifier: Apache-2.0
97 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_get_card_present()
103 fsp_err = R_SDHI_StatusGet(&priv->sdmmc_ctrl, &status); in sdhc_ra_get_card_present()
114 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_card_busy()
119 fsp_err = R_SDHI_StatusGet(&priv->sdmmc_ctrl, &status); in sdhc_ra_card_busy()
146 fsp_err = sdhi_command_send_wait(&priv->sdmmc_ctrl, ra_cmd->opcode, ra_cmd->arg, in sdhc_ra_send_cmd()
147 ra_cmd->timeout_ms); in sdhc_ra_send_cmd()
149 retries--; /* error, retry */ in sdhc_ra_send_cmd()
163 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_request()
164 int retries = (int)(cmd->retries + 1); /* first try plus retries */ in sdhc_ra_request()
171 .opcode = cmd->opcode, in sdhc_ra_request()
172 .arg = cmd->arg, in sdhc_ra_request()
176 ra_cmd.data = (uint8_t *)data->data; in sdhc_ra_request()
177 ra_cmd.sector_count = data->blocks; in sdhc_ra_request()
178 ra_cmd.sector_size = data->block_size; in sdhc_ra_request()
179 timeout_cfg = data->timeout_ms; in sdhc_ra_request()
181 timeout_cfg = cmd->timeout_ms; in sdhc_ra_request()
184 if (cmd->timeout_ms == SDHC_TIMEOUT_FOREVER) { in sdhc_ra_request()
191 k_sem_reset(&priv->sdmmc_event.transfer_sem); in sdhc_ra_request()
192 k_sem_take(&priv->thread_lock, K_FOREVER); in sdhc_ra_request()
201 switch (cmd->opcode) { in sdhc_ra_request()
225 /* SDResponseR2 are bits from 8-127, first 8 MSBs are reserved */ in sdhc_ra_request()
226 p_csd_reg.reg.sdrsp10 = priv->sdmmc_ctrl.p_reg->SD_RSP10; in sdhc_ra_request()
227 p_csd_reg.reg.sdrsp32 = priv->sdmmc_ctrl.p_reg->SD_RSP32; in sdhc_ra_request()
228 p_csd_reg.reg.sdrsp54 = priv->sdmmc_ctrl.p_reg->SD_RSP54; in sdhc_ra_request()
229 p_csd_reg.reg.sdrsp76 = priv->sdmmc_ctrl.p_reg->SD_RSP76; in sdhc_ra_request()
233 uint32_t mult; in sdhc_ra_request() local
236 (SDMMC_CARD_TYPE_MMC == priv->sdmmc_ctrl.device.card_type)) { in sdhc_ra_request()
237 mult = (1U << (p_csd_reg.csd_v1_b.c_size_mult + 2)); in sdhc_ra_request()
238 priv->sdmmc_ctrl.device.sector_count = in sdhc_ra_request()
239 ((p_csd_reg.csd_v1_b.c_size + 1U) * mult); in sdhc_ra_request()
244 priv->sdmmc_ctrl.device.sector_count = in sdhc_ra_request()
245 priv->sdmmc_ctrl.device.sector_count * in sdhc_ra_request()
248 if (SDMMC_CARD_TYPE_MMC == priv->sdmmc_ctrl.device.card_type) { in sdhc_ra_request()
255 priv->sdmmc_ctrl.device.sector_count = 0U; in sdhc_ra_request()
262 priv->sdmmc_ctrl.device.sector_count = in sdhc_ra_request()
270 priv->sdmmc_ctrl.device.erase_sector_count = in sdhc_ra_request()
279 priv->sdmmc_ctrl.device.erase_sector_count = 1U; in sdhc_ra_request()
290 response.status = priv->sdmmc_ctrl.p_reg->SD_RSP10; in sdhc_ra_request()
295 priv->sdmmc_ctrl.sector_addressing = in sdhc_ra_request()
297 priv->sdmmc_ctrl.device.card_type = SDMMC_CARD_TYPE_SD; in sdhc_ra_request()
299 priv->sdmmc_ctrl.initialized = true; in sdhc_ra_request()
303 if (priv->app_cmd && cmd->opcode == SD_APP_SET_BUS_WIDTH) { in sdhc_ra_request()
312 fsp_err = r_sdhi_read_and_block(&priv->sdmmc_ctrl, ra_cmd.opcode, in sdhc_ra_request()
318 memcpy(ra_cmd.data, priv->sdmmc_ctrl.aligned_buff, 8); in sdhc_ra_request()
319 priv->sdmmc_event.transfer_completed = false; in sdhc_ra_request()
326 ra_cmd.opcode = cmd->opcode | SDHI_PRV_CMD_C_ACMD; in sdhc_ra_request()
327 fsp_err = r_sdhi_read_and_block(&priv->sdmmc_ctrl, ra_cmd.opcode, ra_cmd.arg, in sdhc_ra_request()
331 ret = -ETIMEDOUT; in sdhc_ra_request()
334 memcpy(ra_cmd.data, priv->sdmmc_ctrl.aligned_buff, 8); in sdhc_ra_request()
335 priv->sdmmc_event.transfer_completed = false; in sdhc_ra_request()
340 fsp_err = r_sdhi_transfer_read(&priv->sdmmc_ctrl, ra_cmd.sector_count, in sdhc_ra_request()
347 r_sdhi_read_write_common(&priv->sdmmc_ctrl, ra_cmd.sector_count, ra_cmd.sector_size, in sdhc_ra_request()
351 ret = k_sem_take(&priv->sdmmc_event.transfer_sem, K_MSEC(ra_cmd.timeout_ms)); in sdhc_ra_request()
357 if (!priv->sdmmc_event.transfer_completed) { in sdhc_ra_request()
358 ret = -EIO; in sdhc_ra_request()
362 priv->sdmmc_event.transfer_completed = false; in sdhc_ra_request()
368 fsp_err = r_sdhi_transfer_write(&priv->sdmmc_ctrl, ra_cmd.sector_count, in sdhc_ra_request()
375 r_sdhi_read_write_common(&priv->sdmmc_ctrl, ra_cmd.sector_count, ra_cmd.sector_size, in sdhc_ra_request()
379 ret = k_sem_take(&priv->sdmmc_event.transfer_sem, K_MSEC(ra_cmd.timeout_ms)); in sdhc_ra_request()
385 if (!priv->sdmmc_event.transfer_completed) { in sdhc_ra_request()
386 ret = -EIO; in sdhc_ra_request()
390 priv->sdmmc_event.transfer_completed = false; in sdhc_ra_request()
394 LOG_INF("SDHC driver: command %u not supported", cmd->opcode); in sdhc_ra_request()
395 ret = -ENOTSUP; in sdhc_ra_request()
399 /* SDResponseR2 are bits from 8-127, first 8 MSBs are reserved */ in sdhc_ra_request()
400 p_csd_reg.reg.sdrsp10 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP10 << 8; in sdhc_ra_request()
401 p_csd_reg.reg.sdrsp32 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP32 << 8; in sdhc_ra_request()
402 p_csd_reg.reg.sdrsp54 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP54 << 8; in sdhc_ra_request()
403 p_csd_reg.reg.sdrsp76 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP76 << 8; in sdhc_ra_request()
405 memcpy(cmd->response, &p_csd_reg.reg, sizeof(cmd->response)); in sdhc_ra_request()
408 p_csd_reg.reg.sdrsp10 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP10; in sdhc_ra_request()
409 p_csd_reg.reg.sdrsp32 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP32; in sdhc_ra_request()
410 p_csd_reg.reg.sdrsp54 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP54; in sdhc_ra_request()
411 p_csd_reg.reg.sdrsp76 = (uint32_t)priv->sdmmc_ctrl.p_reg->SD_RSP76; in sdhc_ra_request()
413 memcpy(cmd->response, &p_csd_reg.reg, sizeof(cmd->response)); in sdhc_ra_request()
416 if (cmd->opcode == SD_APP_CMD) { in sdhc_ra_request()
417 priv->app_cmd = true; in sdhc_ra_request()
419 priv->app_cmd = false; in sdhc_ra_request()
422 k_sem_give(&priv->thread_lock); in sdhc_ra_request()
429 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_reset()
430 const struct sdhc_ra_config *cfg = dev->config; in sdhc_ra_reset()
432 k_sem_take(&priv->thread_lock, K_USEC(50)); in sdhc_ra_reset()
435 ((R_SDHI0_Type *)cfg->regs)->SOFT_RST = 0x0U; in sdhc_ra_reset()
436 ((R_SDHI0_Type *)cfg->regs)->SOFT_RST = 0x1U; in sdhc_ra_reset()
438 k_sem_give(&priv->thread_lock); in sdhc_ra_reset()
448 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_set_io()
449 const struct sdhc_ra_config *cfg = dev->config; in sdhc_ra_set_io()
450 struct st_sdmmc_instance_ctrl *p_ctrl = &priv->sdmmc_ctrl; in sdhc_ra_set_io()
457 if (ios->bus_width > 0) { in sdhc_ra_set_io()
460 switch (ios->bus_width) { in sdhc_ra_set_io()
469 ret = -ENOTSUP; in sdhc_ra_set_io()
473 if (priv->bus_width != bus_width) { in sdhc_ra_set_io()
475 ((R_SDHI0_Type *)cfg->regs)->SD_OPTION = in sdhc_ra_set_io()
478 priv->bus_width = bus_width; in sdhc_ra_set_io()
482 if (ios->clock) { in sdhc_ra_set_io()
483 if (ios->clock > priv->props.f_max || ios->clock < priv->props.f_min) { in sdhc_ra_set_io()
484 LOG_ERR("Proposed clock outside supported host range"); in sdhc_ra_set_io()
485 return -EINVAL; in sdhc_ra_set_io()
488 if (priv->bus_clock != (uint32_t)ios->clock) { in sdhc_ra_set_io()
489 fsp_err = r_sdhi_max_clock_rate_set(p_ctrl, ios->clock); in sdhc_ra_set_io()
494 priv->bus_clock = ios->clock; in sdhc_ra_set_io()
498 if (ios->timing > 0) { in sdhc_ra_set_io()
500 if (priv->timing != ios->timing) { in sdhc_ra_set_io()
501 switch (ios->timing) { in sdhc_ra_set_io()
509 ret = -ENOTSUP; in sdhc_ra_set_io()
513 priv->timing = ios->timing; in sdhc_ra_set_io()
526 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_get_host_props()
528 memcpy(props, &priv->props, sizeof(struct sdhc_host_props)); in sdhc_ra_get_host_props()
534 const struct sdhc_ra_config *config = dev->config; in sdhc_ra_init()
535 struct sdhc_ra_priv *priv = dev->data; in sdhc_ra_init()
540 priv->sdmmc_event.transfer_completed = false; in sdhc_ra_init()
541 k_sem_init(&priv->sdmmc_event.transfer_sem, 1, 1); in sdhc_ra_init()
544 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in sdhc_ra_init()
548 if (priv->sdhi_en.port != NULL) { in sdhc_ra_init()
549 int err = gpio_pin_configure_dt(&priv->sdhi_en, GPIO_OUTPUT_HIGH); in sdhc_ra_init()
557 k_sem_init(&priv->thread_lock, 1, 1); in sdhc_ra_init()
558 fsp_err = R_SDHI_Open(&priv->sdmmc_ctrl, &priv->fsp_config); in sdhc_ra_init()
568 k_sem_take(&priv->thread_lock, K_USEC(timeout)); in sdhc_ra_init()
570 fsp_err = r_sdhi_hw_cfg(&priv->sdmmc_ctrl); in sdhc_ra_init()
576 priv->bus_width = SDMMC_BUS_WIDTH_1_BIT; in sdhc_ra_init()
577 priv->timing = SDHC_TIMING_LEGACY; in sdhc_ra_init()
578 priv->bus_clock = SDMMC_CLOCK_400KHZ; in sdhc_ra_init()
581 k_sem_give(&priv->thread_lock); in sdhc_ra_init()
606 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, accs, irq)] = \
608 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, card, irq)] = \
610 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, dma_req, irq)] = \
671 struct sdhc_ra_priv *priv = dev->data; \
672 if (p_args->event == SDMMC_EVENT_TRANSFER_COMPLETE) { \
673 priv->sdmmc_event.transfer_completed = true; \
674 k_sem_give(&priv->sdmmc_event.transfer_sem); \
675 } else if (p_args->event == SDMMC_EVENT_TRANSFER_ERROR) { \
676 priv->sdmmc_event.transfer_completed = false; \
677 k_sem_give(&priv->sdmmc_event.transfer_sem); \