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/Zephyr-latest/dts/riscv/openisa/
Drv32m1.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
55 #address-cells = <1>;
56 #size-cells = <1>;
63 #clock-cells = <1>;
69 #clock-cells = <1>;
74 #address-cells = <0>;
75 #interrupt-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6.dtsi15 #address-cells = <1>;
16 #size-cells = <0>;
34 #address-cells = <1>;
35 #size-cells = <1>;
71 #address-cells = <1>;
72 #size-cells = <1>;
89 #gpio-cells = <2>;
90 #cypress,pin-cells = <2>;
99 #gpio-cells = <2>;
100 #cypress,pin-cells = <2>;
[all …]
Dpsoc6_cm0.dtsi26 #address-cells = <1>;
27 #size-cells = <1>;
32 #interrupt-cells = <2>;
40 #interrupt-cells = <2>;
48 #interrupt-cells = <2>;
56 #interrupt-cells = <2>;
64 #interrupt-cells = <2>;
72 #interrupt-cells = <2>;
80 #interrupt-cells = <2>;
88 #interrupt-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/ene/
Dkb1200.dtsi17 #address-cells = <1>;
18 #size-cells = <0>;
37 #address-cells = <1>;
38 #size-cells = <1>;
58 #address-cells = <1>;
59 #size-cells = <1>;
67 #gpio-cells = <2>;
77 #gpio-cells = <2>;
87 #gpio-cells = <2>;
97 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo4p_blue.dtsi14 #clock-cells = <0>;
19 #clock-cells = <1>;
24 #clock-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 #address-cells = <1>;
36 #size-cells = <1>;
66 #address-cells = <1>;
67 #size-cells = <1>;
79 #pwrcfg-cells = <2>;
[all …]
Dambiq_apollo4p.dtsi15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
85 #address-cells = <1>;
86 #size-cells = <1>;
98 #pwrcfg-cells = <2>;
158 #address-cells = <1>;
159 #size-cells = <0>;
[all …]
Dambiq_apollo3p_blue.dtsi15 #clock-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
101 #address-cells = <1>;
102 #size-cells = <1>;
114 #pwrcfg-cells = <2>;
221 #address-cells = <1>;
222 #size-cells = <0>;
[all …]
/Zephyr-latest/tests/drivers/build_all/adc/boards/
Dnative_sim.overlay15 #address-cells = <1>;
16 #size-cells = <1>;
23 #io-channel-cells = <1>;
31 #gpio-cells = <0x2>;
36 #address-cells = <1>;
37 #size-cells = <0>;
46 #io-channel-cells = <1>;
53 #io-channel-cells = <1>;
60 #io-channel-cells = <1>;
66 #io-channel-cells = <1>;
[all …]
/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts19 #interrupt-cells = <3>;
31 #interrupt-cells = <1>;
36 #interrupt-cells = <2>;
41 #interrupt-cells = <3>;
52 #address-cells = <2>;
53 #size-cells = <0>;
57 #address-cells = <1>;
58 #interrupt-cells = <1>;
63 #address-cells = <2>;
64 #interrupt-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_03/
Dpsoc6_03.dtsi12 #address-cells = <1>;
13 #size-cells = <0>;
30 #address-cells = <1>;
31 #size-cells = <1>;
56 #address-cells = <1>;
57 #size-cells = <0>;
73 #gpio-cells = <2>;
82 #gpio-cells = <2>;
91 #gpio-cells = <2>;
100 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/riscv/wch/
Dch32v00x.dtsi14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #clock-cells = <0>;
58 #address-cells = <1>;
59 #size-cells = <1>;
[all …]
/Zephyr-latest/dts/arm64/broadcom/
Dbcm2712.dtsi12 #address-cells = <1>;
13 #size-cells = <0>;
37 #address-cells = <2>;
38 #size-cells = <1>;
51 #interrupt-cells = <4>;
59 #address-cells = <1>;
60 #size-cells = <0>;
65 #gpio-cells = <2>;
87 #clock-cells = <0>;
92 #address-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/
Dpsoc6_04.dtsi12 #address-cells = <1>;
13 #size-cells = <0>;
30 #address-cells = <1>;
31 #size-cells = <1>;
56 #address-cells = <1>;
57 #size-cells = <0>;
73 #gpio-cells = <2>;
81 #gpio-cells = <2>;
90 #gpio-cells = <2>;
99 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/riscv/qemu/
Dvirt-riscv.dtsi16 #address-cells = < 0x01 >;
17 #size-cells = < 0x01 >;
37 #address-cells = < 0x01 >;
38 #size-cells = < 0x00 >;
48 #address-cells = <0>;
49 #interrupt-cells = < 0x01 >;
62 #address-cells = <0>;
63 #interrupt-cells = < 0x01 >;
76 #address-cells = <0>;
77 #interrupt-cells = < 0x01 >;
[all …]
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi11 #address-cells = <2>;
12 #size-cells = <2>;
18 #clock-cells = <0>;
24 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
43 #address-cells = <0>;
44 #interrupt-cells = <1>;
57 #address-cells = <0>;
58 #interrupt-cells = <1>;
[all …]
/Zephyr-latest/dts/riscv/microchip/
Dmpfs.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
25 #address-cells = <0>;
26 #interrupt-cells = <1>;
39 #address-cells = <0>;
40 #interrupt-cells = <1>;
53 #address-cells = <0>;
54 #interrupt-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/intel_socfpga_std/
Dsocfpga.dtsi13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
43 #interrupt-cells = <4>;
50 #address-cells = <1>;
51 #size-cells = <1>;
69 #clock-cells = <0>;
73 #clock-cells = <0>;
78 #clock-cells = <0>;
[all …]
/Zephyr-latest/tests/drivers/build_all/gpio/
Dadc_lmp90xxx_gpio.overlay9 #address-cells = <1>;
10 #size-cells = <1>;
16 #gpio-cells = <0x2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
35 #address-cells = <1>;
36 #size-cells = <0>;
37 #io-channel-cells = <1>;
43 #gpio-cells = <2>;
Dapp.overlay15 #address-cells = <1>;
16 #size-cells = <1>;
22 #gpio-cells = <0x2>;
30 #gpio-cells = <0x2>;
35 #address-cells = <1>;
36 #size-cells = <0>;
45 #gpio-cells = <2>;
54 #gpio-cells = <2>;
64 #gpio-cells = <2>;
74 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32bg2x.dtsi22 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
62 #clock-cells = <0>;
67 #clock-cells = <0>;
72 #clock-cells = <0>;
77 #clock-cells = <0>;
[all …]
Defr32mg21.dtsi22 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
60 #clock-cells = <0>;
65 #clock-cells = <0>;
70 #clock-cells = <0>;
75 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi14 #clock-cells = <0>;
22 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #clock-cells = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
62 #clock-cells = <0>;
70 #clock-cells = <0>;
78 #clock-cells = <0>;
87 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_mcxn94x_common.dtsi16 #address-cells = <1>;
17 #size-cells = <0>;
22 #address-cells = <1>;
23 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <1>;
69 #address-cells = <1>;
70 #size-cells = <1>;
75 #clock-cells = <1>;
78 #reset-cells = <1>;
[all …]
/Zephyr-latest/dts/x86/intel/
Draptor_lake_s.dtsi14 #address-cells = <1>;
15 #size-cells = <0>;
33 #address-cells = <1>;
34 #interrupt-cells = <3>;
43 #interrupt-cells = <3>;
44 #address-cells = <1>;
48 #address-cells = <1>;
49 #size-cells = <1>;
56 #address-cells = <1>;
57 #size-cells = <0>;
[all …]
/Zephyr-latest/boards/arm/mps3/
Dmps3_common_soc_peripheral.dtsi11 #clock-cells = <0>;
19 #gpio-cells = <2>;
27 #gpio-cells = <2>;
35 #gpio-cells = <2>;
43 #gpio-cells = <2>;
57 #address-cells = <1>;
58 #size-cells = <0>;
65 #address-cells = <1>;
66 #size-cells = <0>;
76 #address-cells = <1>;
[all …]

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