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/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483_priv.h3 * SPDX-License-Identifier: Apache-2.0
14 #include<zephyr/dt-bindings/usb-c/nxp_nx20p3483.h>
16 /** Register address - device id */
18 /** Bit mask for vendor id */
20 /** Bit mask for version id */
23 /** Register address - device status */
25 /** Bit mask for device mode */
30 /** Value for high-voltage sink mode */
34 /** Value for high-voltage source mode */
39 /** Register address - switch control */
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpmc_interface.h2 * SPDX-License-Identifier: Apache-2.0
18 * The requesting agent will write the PMC command op-code into this field.
24 * this field.
29 * Some commands require additional information which is passed into this 8 bit field.
34 * Some commands require additional information which is passed into this 8 bit field.
39 * Some commands require additional information which is passed into this 4 bit field.
49 * busy - The run/busy bit can only be set by the requesting agent and can only be cleared by the
50 * responding agent. When this bit is set it will prompt the PMC to execute the command placed in
52 * code has been written back into the COMMAND field and any data requested has been written into
53 * the DATA field.
[all …]
/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 #include <dt-bindings/pinctrl/gd32-af.h>
21 #include <dt-bindings/pinctrl/gd32-afio.h>
33 * - 0-12: GD32_PINMUX_AF bit field.
34 * - 13-25: Reserved.
35 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
38 * - 0-19: GD32_PINMUX_AFIO bit field.
39 * - 20-25: Reserved.
40 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
79 /** No pull-up/down */
[all …]
/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.h4 * SPDX-License-Identifier: Apache-2.0
41 /* Field mask of SPI transfer format register */
44 #define TFMAT_CPHA_MSK BIT(0)
45 #define TFMAT_CPOL_MSK BIT(1)
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_LSB_MSK BIT(3)
48 #define TFMAT_DATA_MERGE_MSK BIT(7)
52 /* Field mask of SPI transfer control register */
65 /* Field mask of SPI interrupt enable register */
66 #define IEN_RX_FIFO_MSK BIT(2)
[all …]
/Zephyr-latest/dts/bindings/ethernet/
Dsnps,dwcxgmac.yaml2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
33 - 2500
[all …]
/Zephyr-latest/include/zephyr/drivers/ethernet/
Deth_nxp_enet_qos.h4 * SPDX-License-Identifier: Apache-2.0
24 #define _ENET_QOS_REG_FIELD(reg, field) MACRO_MAP_CAT(_PREFIX_UNDERLINE, reg, field, MASK) argument
25 #define _ENET_QOS_REG_MASK(reg, field) CONCAT(ENET_QOS_NAME, _ENET_QOS_REG_FIELD(reg, field)) argument
27 /* Deciphers value of a field from a read value of an enet qos register
30 * field: name of the bit field within the register
33 #define ENET_QOS_REG_GET(reg, field, val) FIELD_GET(_ENET_QOS_REG_MASK(reg, field), val) argument
35 /* Prepares value of a field for a write to an enet qos register
38 * field: name of the bit field within the register
39 * val: value to put into the field
41 #define ENET_QOS_REG_PREP(reg, field, val) FIELD_PREP(_ENET_QOS_REG_MASK(reg, field), val) argument
[all …]
/Zephyr-latest/drivers/flash/
Dflash_andes_qspi.h4 * SPDX-License-Identifier: Apache-2.0
26 #define FLASH_ANDES_WIP_BIT BIT(0) /* Write in progress */
27 #define FLASH_ANDES_WEL_BIT BIT(1) /* Write enable latch */
28 #define FLASH_ANDES_QE_BIT BIT(6)
42 /* Field mask of SPI transfer format register */
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_DATA_MERGE_MSK BIT(7)
50 /* Field mask of SPI transfer control register */
58 #define TCTRL_ADDR_FMT_MSK BIT(28)
59 #define TCTRL_ADDR_EN_MSK BIT(29)
[all …]
/Zephyr-latest/drivers/sensor/st/vl53l0x/
Dvl53l0x_platform.h1 /* vl53l0x_platform.h - Zephyr customization of ST vl53l0x library.
8 * SPDX-License-Identifier: Apache-2.0
29 /*!< user specific field */
30 uint8_t I2cDevAddr; /* i2c device address user specific field */
47 * @param field ST structure field name
48 * It maybe used and as real data "ref" not just as "get" for sub-structure item
49 * like PALDevDataGet(FilterData.field)[i]
52 #define PALDevDataGet(Dev, field) (Dev->Data.field) argument
55 * @brief Set ST private structure @a VL53L0X_DevData_t data field
57 * @param field ST structure field name
[all …]
/Zephyr-latest/subsys/bluetooth/services/bas/
Dbas_internal.h4 * SPDX-License-Identifier: Apache-2.0
19 /** @brief Flags Field
21 * The values of this field are defined below.
23 * - bit 0: Identifier Present
24 * - Indicates whether the identifier field is present.
25 * - bit 1: Battery Level Present
26 * - Indicates whether the battery level field is present.
27 * - bit 2: Additional Status Present
28 * - Indicates whether the additional status field is present.
29 * - bit 3–7: RFU (Reserved for Future Use)
[all …]
/Zephyr-latest/soc/nordic/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/pinctrl/nrf-pinctrl.h>
17 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
38 DT_PROP_BY_IDX(node_id, prop, idx) == fun ? BIT(NRF_CLOCKPIN_ENABLE_POS) :
41 * @brief Utility macro compute the clockpin enable bit.
102 * @param pincfg Pin configuration bit field.
109 * @param pincfg Pin configuration bit field.
117 * @param pincfg Pin configuration bit field.
125 * @param pincfg Pin configuration bit field.
132 * @param pincfg Pin configuration bit field.
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
17 CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
18 default corresponds to the reset value of the register field.
20 cs-interval:
25 CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
26 default corresponds to the reset value of the register field.
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h4 * SPDX-License-Identifier: Apache-2.0
21 #define STM32_CLOCK_DIV(div) (((div) - 1) << STM32_CLOCK_DIV_SHIFT)
34 * @brief Pack STM32 source clock selection RCC register bit fields for the DT
36 * @param val Clock configuration field value
37 * @param mask Mask of register field in RCC register
38 * @param shift Position of field within RCC register (= field LSB's index)
53 * Pack RCC clock register offset and bit in two 32-bit values
57 * @param bit Clock bit
59 #define STM32_CLOCK(bus, bit) (STM32_CLOCK_BUS_##bus) (1 << bit) argument
/Zephyr-latest/tests/drivers/pinctrl/api/src/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 * @name Test pin configuration bit field positions and masks.
27 /** Position of the pull field. */
29 /** Mask of the pull field. */
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
39 * @name Test pinctrl pull-up/down.
43 /** Pull-up disabled. */
45 /** Pull-down enabled. */
47 /** Pull-up enabled. */
[all …]
/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_access.h4 * SPDX-License-Identifier: Apache-2.0
11 * NPCX register bit/field access operations
16 #define FIELD_POS(field) GET_POS_##field argument
17 #define FIELD_SIZE(field) GET_SIZE_##field argument
19 #define GET_FIELD(reg, field) \ argument
20 _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
21 #define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
23 #define SET_FIELD(reg, field, value) \ argument
24 _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
26 ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
[all …]
Dreg_def.h4 * SPDX-License-Identifier: Apache-2.0
20 * must meet the alignment requirement of cortex-m4.
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
90 /* 0x102: High-Frequency Reference Divisor I */
92 /* 0x104: High-Frequency Reference Divisor F */
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
133 /* 0x024: Power-Down Control 7 */
137 /* PMC internal inline functions for multi-registers */
[all …]
/Zephyr-latest/subsys/bluetooth/services/
DKconfig.dis4 # SPDX-License-Identifier: Apache-2.0
91 The Vendor ID Source field designates which organization assigned the
92 value used in the Vendor ID field value.
94 - 1 Bluetooth SIG, the Vendor ID was assigned by the Bluetooth SIG
95 - 2 USB IF, the Vendor ID was assigned by the USB IF
102 The Vendor ID field is intended to uniquely identify the vendor of the
103 device. This field is used in conjunction with Vendor ID Source field,
104 which determines which organization assigned the Vendor ID field value.
107 either of which can be used for the Vendor ID field value.
116 The Product ID field is intended to distinguish between different products
[all …]
/Zephyr-latest/include/zephyr/bluetooth/classic/
Da2dp_codec_sbc.h2 * @brief Advance Audio Distribution Profile - SBC Codec header.
5 * SPDX-License-Identifier: Apache-2.0
6 * Copyright (c) 2015-2016 Intel Corporation
13 * http://www.apache.org/licenses/LICENSE-2.0
29 #define A2DP_SBC_SAMP_FREQ_16000 BIT(7)
30 #define A2DP_SBC_SAMP_FREQ_32000 BIT(6)
31 #define A2DP_SBC_SAMP_FREQ_44100 BIT(5)
32 #define A2DP_SBC_SAMP_FREQ_48000 BIT(4)
35 #define A2DP_SBC_CH_MODE_MONO BIT(3)
36 #define A2DP_SBC_CH_MODE_DUAL BIT(2)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnordic-npm1300-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM1300-specific GPIO Flags
11 * @defgroup gpio_interface_npm1300 nPM1300-specific GPIO Flags
16 * - Bit 8: Drive strength (0=1mA, 1=6mA)
17 * - Bit 9: Debounce (0=OFF, 1=ON)
18 * - Bit 10: Watchdog reset (0=OFF, 1=ON)
19 * - Bit 11: Power loss warning (0=OFF, 1=ON)
32 /** Drive mode field mask */
50 /** Debounce field mask */
68 /** watchdog reset field mask */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
22 * @name GECKO_pin configuration bit field positions and masks.
26 /** Position of the function field. */
[all …]
Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
22 * @name GECKO_pin configuration bit field positions and masks.
26 /** Position of the function field. */
[all …]
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac_priv.h2 * Intel Hard Processor System 10 Giga bit TSN Ethernet Media Access controller (XGMAC) driver
7 * SPDX-License-Identifier: Apache-2.0
21 #define READ_BIT(var, bit) ((var >> bit) & 1u) argument
336 #define XGMAC_TDES2_IOC BIT(31)
337 #define XGMAC_TDES3_OWN BIT(31)
338 #define XGMAC_TDES3_FD BIT(29)
339 #define XGMAC_TDES3_LD BIT(28)
342 #define XGMAC_RDES3_OWN BIT(31)
343 #define XGMAC_RDES3_IOC BIT(30)
344 #define XGMAC_RDES3_FD BIT(29)
[all …]
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_mcux_lpc.h4 * SPDX-License-Identifier: Apache-2.0
12 * These attributes can be set to the "dma_slot" field
20 #define LPC_DMA_PERIPH_REQ_EN BIT(0)
25 #define LPC_DMA_HWTRIG_EN BIT(1)
27 /* HW trigger polarity. When this bit is set, the trigger will be active
30 #define LPC_DMA_TRIGPOL_HIGH_RISING BIT(2)
32 /* HW trigger type. When this bit is set, the trigger will be level triggered.
35 #define LPC_DMA_TRIGTYPE_LEVEL BIT(3)
42 #define LPC_DMA_TRIGBURST BIT(4)
45 * field, the maximum transfer burst possible is 128. The hardware supports
/Zephyr-latest/include/zephyr/drivers/rtc/
Dmaxim_ds3231.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Real-time clock control based on the DS3231 counter API.
12 * DS3231](https://www.maximintegrated.com/en/products/analog/real-time-clocks/DS3231.html)
13 * is a high-precision real-time clock with temperature-compensated
28 * functionality exposed by this header to access the real-time-clock
46 /** @brief Bit in ctrl or ctrl_stat associated with alarm 1. */
47 #define MAXIM_DS3231_ALARM1 BIT(0)
49 /** @brief Bit in ctrl or ctrl_stat associated with alarm 2. */
50 #define MAXIM_DS3231_ALARM2 BIT(1)
57 /** @brief ctrl bit for alarm 1 interrupt enable. */
[all …]
/Zephyr-latest/soc/nuvoton/npcx/npcx9/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
12 /* NPCX9 SCFG multi-registers */
18 /* NPCX9 MIWU multi-registers */
28 /* NPCX9 ADC multi-registers */
35 #define NPCX_THRCTL_CHNSEL FIELD(10, 4)
36 #define NPCX_THRCTL_THRVAL FIELD(0, 10)
43 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
44 BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
45 BIT(15) | BIT(16) | BIT(17) | BIT(18)) /* DEVALT0_LK - DEVALTJ_LK */
/Zephyr-latest/soc/nuvoton/npcx/npcx4/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
12 /* NPCX4 SCFG multi-registers */
18 /* NPCX4 MIWU multi-registers */
28 /* NPCX4 ADC multi-registers */
36 #define NPCX_THRCTL_CHNSEL FIELD(10, 5)
37 #define NPCX_THRCTL_THRVAL FIELD(0, 10)
45 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
46 BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
47 BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
48 BIT(19) | BIT(21)) /* DEVALT0_LK - DEVALTN_LK */

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