1 /* 2 * Copyright (c) 2021 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _NUVOTON_NPCX_SOC_H_ 8 #define _NUVOTON_NPCX_SOC_H_ 9 10 #include <cmsis_core_m_defaults.h> 11 12 /* NPCX9 SCFG multi-registers */ 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) 14 #define NPCX_PUPD_EN_OFFSET(n) (0x028 + n) 15 #define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n)) 16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) 17 18 /* NPCX9 MIWU multi-registers */ 19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010)) 20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010)) 21 #define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010)) 22 #define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010)) 23 #define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010)) 24 #define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010)) 25 #define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010)) 26 #define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010)) 27 28 /* NPCX9 ADC multi-registers */ 29 #define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2)) 30 #define NPCX_THRCTL_OFFSET(n) (0x060 + (n * 2)) 31 32 /* NPCX9 ADC register fields */ 33 #define NPCX_THRCTL_THEN 15 34 #define NPCX_THRCTL_L_H 14 35 #define NPCX_THRCTL_CHNSEL FIELD(10, 4) 36 #define NPCX_THRCTL_THRVAL FIELD(0, 10) 37 38 /* NPCX9 FIU register fields */ 39 #define NPCX_FIU_EXT_CFG_SPI1_2DEV 7 40 41 /* NPCX9 supported group mask of DEVALT_LK */ 42 #define NPCX_DEVALT_LK_GROUP_MASK \ 43 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | \ 44 BIT(5) | BIT(6) | BIT(11) | BIT(13) | \ 45 BIT(15) | BIT(16) | BIT(17) | BIT(18)) /* DEVALT0_LK - DEVALTJ_LK */ 46 47 /* NPCX9 Clock configuration and limitation */ 48 #define MAX_OFMCLK 100000000 49 50 #include <reg/reg_access.h> 51 #include <reg/reg_def.h> 52 #include <soc_dt.h> 53 #include <soc_clock.h> 54 #include <soc_pins.h> 55 #include <soc_power.h> 56 57 #endif /* _NUVOTON_NPCX_SOC_H_ */ 58
