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/Zephyr-latest/dts/bindings/i2s/
Dst,stm32-i2s-common.yaml27 mck-enabled:
31 An mck pin must be listed within pinctrl-0 when enabling this property.
Dnordic,nrf-i2s.yaml28 (MCK) generator. The generator is only needed when the I2S peripheral
/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
35 and OE inputs respectively. Assuming that MCK is 120MHz (cpu at full speed)
36 each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
123 where each value is configured in terms of MCK cycles. The SMC
135 each value is configured in terms of MCK cycles and a value of 0 is forbidden.
/Zephyr-latest/soc/atmel/sam/same70/
Dsoc.c39 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
66 * (MCK) frequency. in clock_init()
67 * TODO: set FWS based on the actual MCK frequency and VDDIO value in clock_init()
96 /* Setting PLLA as MCK, first prescaler, then divider and source last */ in clock_init()
/Zephyr-latest/soc/atmel/sam/samv71/
Dsoc.c37 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
64 * (MCK) frequency. in clock_init()
65 * TODO: set FWS based on the actual MCK frequency and VDDIO value in clock_init()
94 /* Setting PLLA as MCK, first prescaler, then divider and source last */ in clock_init()
/Zephyr-latest/soc/atmel/sam/sam3x/
Dsoc.c33 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
60 * (MCK) frequency. in clock_init()
61 * TODO: set FWS based on the actual MCK frequency and VDDCORE value in clock_init()
Dsoc.h47 /** Master Clock (MCK) Frequency */
/Zephyr-latest/boards/renesas/mck_ra8t1/
Dmck_ra8t1.yaml2 name: Renesas MCK-RA8T1
/Zephyr-latest/soc/microchip/mec/mec15xx/
DKconfig28 and master clock (MCK):
29 HCLK = MCK / PROC_CLK_DIV
/Zephyr-latest/soc/atmel/sam/common/
DKconfig73 and master clock (MCK) where the maximum value is 150MHz:
74 MCK = HCLK / MDIV
/Zephyr-latest/soc/atmel/sam/sam4e/
Dsoc.c36 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
62 * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet. in clock_init()
Dsoc.h46 /** Master Clock (MCK) Frequency */
/Zephyr-latest/dts/bindings/dac/
Datmel,sam-dac.yaml24 PRESCAL = (MCK / DACClock) - 2. Should be in range from 0 to 15. The
/Zephyr-latest/soc/atmel/sam/sam4s/
Dsoc.c36 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
65 * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. in clock_init()
Dsoc.h60 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/same54/
Dsoc.h43 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/same51/
Dsoc.h45 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/same53/
Dsoc.h44 /** Master Clock (MCK) Frequency */
/Zephyr-latest/boards/renesas/mck_ra8t1/doc/
Dindex.rst9 The **MCK-RA8T1** is a development kit that enables easy evaluation of motor control using permanen…
11 found here: `MCK-RA8T1 Website`_
13 MCK-RA8T1 kit includes the items below:
25 MCK-RA8T1 product contents (Credit: Renesas Electronics Corporation)
191 …ducts/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0ema5k0s00020bj-mck-ra8t1-renesas-flexi…
/Zephyr-latest/soc/atmel/sam0/samr34/
Dsoc.h38 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/samr35/
Dsoc.h38 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/samd51/
Dsoc.h51 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/samc20/
Dsoc.h66 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/samc21/
Dsoc.h66 /** Master Clock (MCK) Frequency */
/Zephyr-latest/soc/atmel/sam0/saml21/
Dsoc.h54 /** Master Clock (MCK) Frequency */

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