1 /*
2  * Copyright (c) 2021 Argentum Systems Ltd.
3  * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef _SOC_ATMEL_SAM0_SAMR34_SOC_H_
9 #define _SOC_ATMEL_SAM0_SAMR34_SOC_H_
10 
11 #ifndef _ASMLANGUAGE
12 
13 #define DONT_USE_CMSIS_INIT
14 
15 #include <zephyr/types.h>
16 
17 #if defined(CONFIG_SOC_SAMR34J16B)
18 #include <samr34j16b.h>
19 #elif defined(CONFIG_SOC_SAMR34J17B)
20 #include <samr34j17b.h>
21 #elif defined(CONFIG_SOC_SAMR34J18B)
22 #include <samr34j18b.h>
23 #else
24 #error Library does not support the specified device.
25 #endif
26 
27 #endif /* _ASMLANGUAGE */
28 
29 #define ADC_SAM0_REFERENCE_ENABLE_PROTECTED
30 
31 #include "adc_fixup_sam0.h"
32 #include "../common/soc_port.h"
33 #include "../common/atmel_sam0_dt.h"
34 
35 /** Processor Clock (HCLK) Frequency */
36 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ
37 
38 /** Master Clock (MCK) Frequency */
39 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
40 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
41 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
42 #define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000
43 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
44 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000
45 
46 #if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN)
47 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0
48 #elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN)
49 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ
50 #elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN)
51 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
52 #elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN)
53 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ
54 #else
55 #error Unsupported GCLK1 clock source.
56 #endif
57 
58 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
59 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
60 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
61 
62 #endif /* _SOC_ATMEL_SAM0_SAMR34_SOC_H_ */
63