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Searched refs:HWREG (Results 1 – 25 of 225) sorted by relevance

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/hal_ti-latest/simplelink/source/ti/devices/cc32xx/driverlib/
Dsdhost.c74 HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2; in SDHostInit()
79 while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) ) in SDHostInit()
87 HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24); in SDHostInit()
92 while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) ) in SDHostInit()
100 HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24); in SDHostInit()
105 HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9; in SDHostInit()
110 HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8; in SDHostInit()
115 while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) ) in SDHostInit()
120 HWREG(ulBase + MMCHS_O_CON) |= 1 << 21; in SDHostInit()
125 HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF; in SDHostInit()
[all …]
Di2s.c90 ulReg = HWREG(ulBase + MCASP_O_GBLCTL); in I2SGBLEnable()
100 HWREG(ulBase + MCASP_O_GBLCTL) = ulReg; in I2SGBLEnable()
105 while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg) in I2SGBLEnable()
133 if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20) in I2SEnable()
138 HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000; in I2SEnable()
217 HWREG(ulBase + MCASP_O_GBLCTL) = 0; in I2SDisable()
222 while( HWREG(ulBase + MCASP_O_GBLCTL) != 0) in I2SDisable()
254 while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)) in I2SDataPut()
262 HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; in I2SDataPut()
293 if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA) in I2SDataPutNonBlocking()
[all …]
Dflash.c136 while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) in FlashDisable()
145 HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000; in FlashDisable()
155 HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0; in FlashDisable()
162 HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; in FlashDisable()
198 HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) in FlashErase()
204 HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; in FlashErase()
205 HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) in FlashErase()
211 while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE) in FlashErase()
218 if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) in FlashErase()
262 HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = in FlashEraseNonBlocking()
[all …]
Dprcm.c102 #define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR))
275 HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2; in PRCMMCUReset()
282 HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1; in PRCMMCUReset()
322 ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF); in PRCMSysResetCauseGet()
333 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) in PRCMSysResetCauseGet()
340 !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) ) in PRCMSysResetCauseGet()
342 if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) in PRCMSysResetCauseGet()
381 HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags; in PRCMPeripheralClkEnable()
388 if( (HWREG(0x00000400) & 0xFFFF) < 2 ) in PRCMPeripheralClkEnable()
395 HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404; in PRCMPeripheralClkEnable()
[all …]
Duart.c164 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet()
194 return(HWREG(ulBase + UART_O_LCRH) & in UARTParityModeGet()
238 HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; in UARTFIFOLevelSet()
273 ulTemp = HWREG(ulBase + UART_O_IFLS); in UARTFIFOLevelGet()
338 HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; in UARTConfigSetExpClk()
351 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); in UARTConfigSetExpClk()
362 HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; in UARTConfigSetExpClk()
363 HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; in UARTConfigSetExpClk()
368 HWREG(ulBase + UART_O_LCRH) = ulConfig; in UARTConfigSetExpClk()
373 HWREG(ulBase + UART_O_FR) = 0; in UARTConfigSetExpClk()
[all …]
Dspi.c148 HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; in SPITransfer8()
156 while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) in SPITransfer8()
163 HWREG(ulWriteReg) = *ucDout; in SPITransfer8()
168 while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) in SPITransfer8()
175 *ucDin = HWREG(ulReadReg); in SPITransfer8()
194 HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; in SPITransfer8()
281 HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; in SPITransfer16()
289 while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) in SPITransfer16()
296 HWREG(ulWriteReg) = *usDout; in SPITransfer16()
301 while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) in SPITransfer16()
[all …]
Di2c.c204 HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; in I2CMasterInitExpClk()
210 if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) in I2CMasterInitExpClk()
214 HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; in I2CMasterInitExpClk()
251 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; in I2CSlaveInit()
290 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; in I2CSlaveAddressSet()
299 HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; in I2CSlaveAddressSet()
327 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; in I2CMasterEnable()
352 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; in I2CSlaveEnable()
357 HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; in I2CSlaveEnable()
382 HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); in I2CMasterDisable()
[all …]
Dgpio.c186 HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ? in GPIODirModeSet()
187 (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) : in GPIODirModeSet()
188 (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins))); in GPIODirModeSet()
226 ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR); in GPIODirModeGet()
276 HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ? in GPIOIntTypeSet()
277 (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) : in GPIOIntTypeSet()
278 (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins))); in GPIOIntTypeSet()
279 HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ? in GPIOIntTypeSet()
280 (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) : in GPIOIntTypeSet()
281 (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins))); in GPIOIntTypeSet()
[all …]
Dcamera.c72 HWREG(ulBase + CAMERA_O_CC_SYSCONFIG) = CAMERA_CC_SYSCONFIG_SOFT_RESET; in CameraReset()
77 while(!(HWREG(ulBase + CAMERA_O_CC_SYSSTATUS)& in CameraReset()
123 ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL); in CameraParamsConfig()
139 HWREG(ulBase + CAMERA_O_CC_CTRL)=ulReg; in CameraParamsConfig()
166 ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK); in CameraXClkConfig()
190 HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; in CameraXClkConfig()
219 ulReg = (HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) & in CameraXClkSet()
238 HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; in CameraXClkSet()
259 HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= CAMERA_CC_CTRL_DMA_DMA_EN; in CameraDMAEnable()
279 HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_DMA_EN; in CameraDMADisable()
[all …]
Daes.c196 if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) in AESConfigSet()
204 HWREG(ui32Base + AES_O_CTRL) = ui32Config; in AESConfigSet()
239 HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0)); in AESKey1Set()
240 HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4)); in AESKey1Set()
241 HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8)); in AESKey1Set()
242 HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12)); in AESKey1Set()
249 HWREG(ui32Base + AES_O_KEY1_4) = * ((uint32_t *)(pui8Key + 16)); in AESKey1Set()
250 HWREG(ui32Base + AES_O_KEY1_5) = * ((uint32_t *)(pui8Key + 20)); in AESKey1Set()
258 HWREG(ui32Base + AES_O_KEY1_6) = * ((uint32_t *)(pui8Key + 24)); in AESKey1Set()
259 HWREG(ui32Base + AES_O_KEY1_7) = * ((uint32_t *)(pui8Key + 28)); in AESKey1Set()
[all …]
Ddes.c105 ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); in DESConfigSet()
110 HWREG(ui32Base + DES_O_CTRL) = ui32Config; in DESConfigSet()
139 HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0)); in DESKeySet()
140 HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4)); in DESKeySet()
146 if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) in DESKeySet()
148 HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8)); in DESKeySet()
149 HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12)); in DESKeySet()
150 HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16)); in DESKeySet()
151 HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20)); in DESKeySet()
183 if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) in DESIVSet()
[all …]
Dshamd5.c82 HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= in SHAMD5DMAEnable()
108 HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= in SHAMD5DMADisable()
148 ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS); in SHAMD5IntStatus()
149 ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); in SHAMD5IntStatus()
150 return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & in SHAMD5IntStatus()
155 ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS); in SHAMD5IntStatus()
156 return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) | in SHAMD5IntStatus()
197 HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16); in SHAMD5IntEnable()
198 HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; in SHAMD5IntEnable()
203 HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_PIT_EN; in SHAMD5IntEnable()
[all …]
Dudma.c74 HWREG(UDMA_BASE + UDMA_O_CFG) = UDMA_CFG_MASTEN; in uDMAEnable()
93 HWREG(UDMA_BASE + UDMA_O_CFG) = 0; in uDMADisable()
113 return(HWREG(UDMA_BASE + UDMA_O_ERRCLR)); in uDMAErrorStatusGet()
133 HWREG(UDMA_BASE + UDMA_O_ERRCLR) = 1; in uDMAErrorStatusClear()
164 HWREG(UDMA_BASE + UDMA_O_ENASET) = 1 << (ulChannelNum & 0x1f); in uDMAChannelEnable()
191 HWREG(UDMA_BASE + UDMA_O_ENACLR) = 1 << (ulChannelNum & 0x1f); in uDMAChannelDisable()
219 return((HWREG(UDMA_BASE + UDMA_O_ENASET) & in uDMAChannelIsEnabled()
256 HWREG(UDMA_BASE + UDMA_O_CTLBASE) = (unsigned long)pControlTable; in uDMAControlBaseSet()
277 return((void *)HWREG(UDMA_BASE + UDMA_O_CTLBASE)); in uDMAControlBaseGet()
298 return((void *)HWREG(UDMA_BASE + UDMA_O_ALTBASE)); in uDMAControlAlternateBaseGet()
[all …]
Dtimer.c106 HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); in TimerEnable()
135 HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & in TimerDisable()
212 HWREG(0x440260B0) = 0xFF; in TimerConfigure()
217 HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); in TimerConfigure()
222 HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; in TimerConfigure()
228 HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; in TimerConfigure()
229 HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; in TimerConfigure()
263 HWREG(ulBase + TIMER_O_CTL) = (bInvert ? in TimerControlLevel()
264 (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : in TimerControlLevel()
265 (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); in TimerControlLevel()
[all …]
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dcrypto.c102 HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation); in CRYPTOAesLoadKey()
105 HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; in CRYPTOAesLoadKey()
106 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | in CRYPTOAesLoadKey()
113 HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | in CRYPTOAesLoadKey()
119 if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) { in CRYPTOAesLoadKey()
120 HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128; in CRYPTOAesLoadKey()
124 HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); in CRYPTOAesLoadKey()
130 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; in CRYPTOAesLoadKey()
134 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH; in CRYPTOAesLoadKey()
141 while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & in CRYPTOAesLoadKey()
[all …]
Dflash.c125 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; in FlashPowerModeSet()
126 HWREG(FLASH_BASE + FLASH_O_FWFLAG) &= ~FW_PWRMODE_DEPRECATED; in FlashPowerModeSet()
127 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; in FlashPowerModeSet()
133 HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = in FlashPowerModeSet()
134 (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & in FlashPowerModeSet()
138 HWREG(FLASH_BASE + FLASH_O_FPAC1) = in FlashPowerModeSet()
139 … (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); in FlashPowerModeSet()
144 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; in FlashPowerModeSet()
145 HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_PWRMODE_DEPRECATED; in FlashPowerModeSet()
146 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; in FlashPowerModeSet()
[all …]
Dinterrupt.c164 if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) in IntRegister()
168 ui32Value = HWREG(NVIC_VTABLE); in IntRegister()
171 g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + in IntRegister()
176 HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; in IntRegister()
210 HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; in IntPriorityGroupingSet()
224 ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; in IntPriorityGroupingGet()
255 ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); in IntPrioritySet()
258 HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; in IntPrioritySet()
273 return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & in IntPriorityGet()
292 HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; in IntEnable()
[all …]
Dprcm.c186 HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; in PRCMInfClockConfigureSet()
190 HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; in PRCMInfClockConfigureSet()
194 HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; in PRCMInfClockConfigureSet()
220 ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); in PRCMInfClockConfigureGet()
224 ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); in PRCMInfClockConfigureGet()
228 ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); in PRCMInfClockConfigureGet()
314 HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; in PRCMAudioClockConfigSet()
315 HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; in PRCMAudioClockConfigSet()
316 HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; in PRCMAudioClockConfigSet()
319 ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | in PRCMAudioClockConfigSet()
[all …]
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Dflash.c123 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; in FlashPowerModeSet()
124 HWREG(FLASH_BASE + FLASH_O_FWFLAG) &= ~FW_PWRMODE_DEPRECATED; in FlashPowerModeSet()
125 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; in FlashPowerModeSet()
131 HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = in FlashPowerModeSet()
132 (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & in FlashPowerModeSet()
134 HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = in FlashPowerModeSet()
135 (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & in FlashPowerModeSet()
139 HWREG(FLASH_BASE + FLASH_O_FPAC1) = in FlashPowerModeSet()
140 … (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); in FlashPowerModeSet()
145 HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; in FlashPowerModeSet()
[all …]
Daes.c96 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; in AESSetInitializationVector()
97 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; in AESSetInitializationVector()
98 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; in AESSetInitializationVector()
99 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; in AESSetInitializationVector()
110 iv[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0); in AESReadAuthenticationModeIV()
111 iv[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1); in AESReadAuthenticationModeIV()
112 iv[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2); in AESReadAuthenticationModeIV()
116 iv[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3); in AESReadAuthenticationModeIV()
127 while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); in AESReadNonAuthenticationModeIV()
141 …HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; … in AESStartDMAOperation()
[all …]
Dinterrupt.c162 if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) in IntRegister()
166 ui32Value = HWREG(NVIC_VTABLE); in IntRegister()
169 g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + in IntRegister()
174 HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; in IntRegister()
208 HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; in IntPriorityGroupingSet()
222 ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; in IntPriorityGroupingGet()
253 ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); in IntPrioritySet()
256 HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; in IntPrioritySet()
271 return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & in IntPriorityGet()
290 HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; in IntEnable()
[all …]
/hal_ti-latest/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/
Daes.h175 HWREG(AES_BASE + AES_O_BUF0) = buf[0]; in AESWriteBUF32()
176 HWREG(AES_BASE + AES_O_BUF1) = buf[1]; in AESWriteBUF32()
177 HWREG(AES_BASE + AES_O_BUF2) = buf[2]; in AESWriteBUF32()
178 HWREG(AES_BASE + AES_O_BUF3) = buf[3]; in AESWriteBUF32()
204 buf[0] = HWREG(AES_BASE + AES_O_BUF0); in AESReadBUF32()
205 buf[1] = HWREG(AES_BASE + AES_O_BUF1); in AESReadBUF32()
206 buf[2] = HWREG(AES_BASE + AES_O_BUF2); in AESReadBUF32()
207 buf[3] = HWREG(AES_BASE + AES_O_BUF3); in AESReadBUF32()
235 HWREG(AES_BASE + AES_O_TXTX0) = txtxor[0]; in AESWriteTXTXOR32()
236 HWREG(AES_BASE + AES_O_TXTX1) = txtxor[1]; in AESWriteTXTXOR32()
[all …]
Dckmd.h117 …uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~(CKMD_HFXTINIT_Q1CAP_M | CKMD_HFXTINIT_Q2CAP_… in CKMDSetInitialCapTrim()
120 HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; in CKMDSetInitialCapTrim()
144 uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_Q1CAP_M; in CKMDSetInitialQ1CapTrim()
146 HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; in CKMDSetInitialQ1CapTrim()
170 uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_Q2CAP_M; in CKMDSetInitialQ2CapTrim()
172 HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; in CKMDSetInitialQ2CapTrim()
196 uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_IREF_M; in CKMDSetInitialIrefTrim()
198 HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; in CKMDSetInitialIrefTrim()
222 uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_IDAC_M; in CKMDSetInitialIdacTrim()
224 HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; in CKMDSetInitialIdacTrim()
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Di2c.h203 HWREG(base + I2C_O_CCTL) = cmd; in I2CControllerCommand()
236 HWREG(base + I2C_O_CTA) = (targetAddr << 1) | receive; in I2CControllerSetTargetAddr()
256 HWREG(base + I2C_O_CCR) |= I2C_CCR_CFE_M; in I2CControllerEnable()
259 HWREG(base + I2C_O_CCTL) = I2C_CCTL_RUN_EN; in I2CControllerEnable()
279 HWREG(base + I2C_O_CCTL) = 0; in I2CControllerDisable()
282 HWREG(base + I2C_O_CCR) &= ~I2C_CCR_CFE_M; in I2CControllerDisable()
305 if (HWREG(base + I2C_O_CSTA) & I2C_CSTA_BUSY_M) in I2CControllerBusy()
336 if (HWREG(base + I2C_O_CSTA) & I2C_CSTA_BUSBSY_M) in I2CControllerBusBusy()
364 return (HWREG(base + I2C_O_CDR)); in I2CControllerGetData()
385 HWREG(base + I2C_O_CDR) = data; in I2CControllerPutData()
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Dlpcmp.h135 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_EN; in LPCMPEnable()
147 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EN; in LPCMPDisable()
163 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_EVTEN; in LPCMPEnableEvent()
175 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EVTEN; in LPCMPDisableEvent()
188 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EVTIFG; in LPCMPClearEvent()
201 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_WUENSB; in LPCMPEnableWakeup()
214 HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_WUENSB; in LPCMPDisableWakeup()
237 lpcmpcfg = HWREG(SYS0_BASE + SYS0_O_LPCMPCFG); in LPCMPSelectNegativeInput()
238 …HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) = (lpcmpcfg & ~SYS0_LPCMPCFG_NSEL_M) | (input & SYS0_LPCMPCFG_N… in LPCMPSelectNegativeInput()
255 if (HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) & SYS0_LPCMPCFG_COUT_HIGH) in LPCMPIsOutputHigh()
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