Lines Matching refs:HWREG

164     HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &  in UARTParityModeSet()
194 return(HWREG(ulBase + UART_O_LCRH) & in UARTParityModeGet()
238 HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; in UARTFIFOLevelSet()
273 ulTemp = HWREG(ulBase + UART_O_IFLS); in UARTFIFOLevelGet()
338 HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; in UARTConfigSetExpClk()
351 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); in UARTConfigSetExpClk()
362 HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; in UARTConfigSetExpClk()
363 HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; in UARTConfigSetExpClk()
368 HWREG(ulBase + UART_O_LCRH) = ulConfig; in UARTConfigSetExpClk()
373 HWREG(ulBase + UART_O_FR) = 0; in UARTConfigSetExpClk()
417 ulInt = HWREG(ulBase + UART_O_IBRD); in UARTConfigGetExpClk()
418 ulFrac = HWREG(ulBase + UART_O_FBRD); in UARTConfigGetExpClk()
424 if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) in UARTConfigGetExpClk()
436 *pulConfig = (HWREG(ulBase + UART_O_LCRH) & in UARTConfigGetExpClk()
464 HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; in UARTEnable()
469 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | in UARTEnable()
496 while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) in UARTDisable()
503 HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); in UARTDisable()
508 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | in UARTDisable()
534 HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; in UARTFIFOEnable()
559 HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); in UARTFIFODisable()
599 ulTemp = HWREG(ulBase + UART_O_CTL); in UARTModemControlSet()
601 HWREG(ulBase + UART_O_CTL) = ulTemp; in UARTModemControlSet()
640 ulTemp = HWREG(ulBase + UART_O_CTL); in UARTModemControlClear()
642 HWREG(ulBase + UART_O_CTL) = ulTemp; in UARTModemControlClear()
669 return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS)); in UARTModemControlGet()
697 return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_CTS)); in UARTModemStatusGet()
738 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet()
771 return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | in UARTFlowControlGet()
813 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet()
850 return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | in UARTTxIntModeGet()
878 return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); in UARTCharsAvail()
905 return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); in UARTSpaceAvail()
935 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) in UARTCharGetNonBlocking()
940 return(HWREG(ulBase + UART_O_DR)); in UARTCharGetNonBlocking()
976 while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) in UARTCharGet()
983 return(HWREG(ulBase + UART_O_DR)); in UARTCharGet()
1014 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) in UARTCharPutNonBlocking()
1019 HWREG(ulBase + UART_O_DR) = ucData; in UARTCharPutNonBlocking()
1060 while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) in UARTCharPut()
1067 HWREG(ulBase + UART_O_DR) = ucData; in UARTCharPut()
1096 HWREG(ulBase + UART_O_LCRH) = in UARTBreakCtl()
1098 (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : in UARTBreakCtl()
1099 (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); in UARTBreakCtl()
1128 return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); in UARTBusy()
1256 HWREG(ulBase + UART_O_IM) |= ulIntFlags; in UARTIntEnable()
1287 HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); in UARTIntDisable()
1320 return(HWREG(ulBase + UART_O_MIS)); in UARTIntStatus()
1324 return(HWREG(ulBase + UART_O_RIS)); in UARTIntStatus()
1365 HWREG(ulBase + UART_O_ICR) = ulIntFlags; in UARTIntClear()
1401 HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; in UARTDMAEnable()
1433 HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; in UARTDMADisable()
1464 return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); in UARTRxErrorGet()
1493 HWREG(ulBase + UART_O_ECR) = 0; in UARTRxErrorClear()