148     HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;  in SPITransfer8()
156     while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )  in SPITransfer8()
163     HWREG(ulWriteReg) = *ucDout;  in SPITransfer8()
168     while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )  in SPITransfer8()
175     *ucDin = HWREG(ulReadReg);  in SPITransfer8()
194     HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;  in SPITransfer8()
281     HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;  in SPITransfer16()
289     while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )  in SPITransfer16()
296     HWREG(ulWriteReg) = *usDout;  in SPITransfer16()
301     while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )  in SPITransfer16()
308     *usDin = HWREG(ulReadReg);  in SPITransfer16()
327     HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;  in SPITransfer16()
414     HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;  in SPITransfer32()
422     while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )  in SPITransfer32()
429     HWREG(ulWriteReg) = *ulDout;  in SPITransfer32()
434     while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )  in SPITransfer32()
441     *ulDin = HWREG(ulReadReg);  in SPITransfer32()
460     HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;  in SPITransfer32()
568   HWREG(ulBase + MCSPI_O_CH0CTRL) |= MCSPI_CH0CTRL_EN;  in SPIEnable()
589   HWREG(ulBase + MCSPI_O_CH0CTRL) &= ~MCSPI_CH0CTRL_EN;  in SPIDisable()
617   HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;  in SPIDmaEnable()
644   HWREG(ulBase + MCSPI_O_CH0CONF) &= ~ulFlags;  in SPIDmaDisable()
665   HWREG(ulBase + MCSPI_O_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET;  in SPIReset()
670   while(!(HWREG(ulBase + MCSPI_O_SYSSTATUS)& MCSPI_SYSSTATUS_RESETDONE))  in SPIReset()
754   ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL);  in SPIConfigSetExpClk()
771   HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData;  in SPIConfigSetExpClk()
807   HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4);  in SPIConfigSetExpClk()
819   HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData;  in SPIConfigSetExpClk()
844   ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);  in SPIDataGetNonBlocking()
851     *pulData = HWREG(ulBase + MCSPI_O_RX0);  in SPIDataGetNonBlocking()
879   while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS))  in SPIDataGet()
886   *pulData = HWREG(ulBase + MCSPI_O_RX0);  in SPIDataGet()
910     ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);  in SPIDataPutNonBlocking()
918       HWREG(ulBase + MCSPI_O_TX0) = ulData;  in SPIDataPutNonBlocking()
944   while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS))  in SPIDataPut()
951   HWREG(ulBase + MCSPI_O_TX0) = ulData;  in SPIDataPut()
977   HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;  in SPIFIFOEnable()
1003   HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags);  in SPIFIFODisable()
1028   ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);  in SPIFIFOLevelSet()
1038   HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal;  in SPIFIFOLevelSet()
1065   ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);  in SPIFIFOLevelGet()
1094   ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);  in SPIWordCountSet()
1099   HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)|  in SPIWordCountSet()
1216       HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;  in SPIIntEnable()
1225       HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;  in SPIIntEnable()
1231   HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F);  in SPIIntEnable()
1263       HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;  in SPIIntDisable()
1272       HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;  in SPIIntDisable()
1278   HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F);  in SPIIntDisable()
1307   ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F;  in SPIIntStatus()
1311      ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE);  in SPIIntStatus()
1324     ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED);  in SPIIntStatus()
1328     ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);  in SPIIntStatus()
1381       HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;  in SPIIntClear()
1390       HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;  in SPIIntClear()
1396   HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F);  in SPIIntClear()
1417   HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;  in SPICSEnable()
1438   HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;  in SPICSDisable()
1481   ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M);  in SPITransfer()