Lines Matching refs:HWREG
102 #define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR))
275 HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2; in PRCMMCUReset()
282 HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1; in PRCMMCUReset()
322 ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF); in PRCMSysResetCauseGet()
333 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) in PRCMSysResetCauseGet()
340 !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) ) in PRCMSysResetCauseGet()
342 if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) in PRCMSysResetCauseGet()
381 HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags; in PRCMPeripheralClkEnable()
388 if( (HWREG(0x00000400) & 0xFFFF) < 2 ) in PRCMPeripheralClkEnable()
395 HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404; in PRCMPeripheralClkEnable()
423 HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags; in PRCMPeripheralClkDisable()
459 if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) in PRCMPeripheralClockGet()
470 ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07); in PRCMPeripheralClockGet()
471 ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) & 0xFF); in PRCMPeripheralClockGet()
475 ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07); in PRCMPeripheralClockGet()
476 ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) & 0xFF); in PRCMPeripheralClockGet()
515 HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg) in PRCMPeripheralReset()
527 HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg) in PRCMPeripheralReset()
554 ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg); in PRCMPeripheralStatusGet()
601 HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) = in PRCMI2SClockFreqSet()
626 if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) in PRCMLPDSRestoreInfoSet()
631 HWREG(0x4402E160) = ulStackPtr; in PRCMLPDSRestoreInfoSet()
636 HWREG(0x4402E198) = ulProgCntr; in PRCMLPDSRestoreInfoSet()
644 HWREG(0x4402E18C) = ulStackPtr; in PRCMLPDSRestoreInfoSet()
649 HWREG(0x4402E190) = ulProgCntr; in PRCMLPDSRestoreInfoSet()
678 ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); in PRCMLPDSEnter()
697 HWREG(0x4402E168) |= (1<<9); in PRCMLPDSEnter()
703 HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; in PRCMLPDSEnter()
708 HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) in PRCMLPDSEnter()
753 ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); in PRCMLPDSEnterKeepDebugIf()
770 HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; in PRCMLPDSEnterKeepDebugIf()
775 HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) in PRCMLPDSEnterKeepDebugIf()
816 ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG); in PRCMLPDSWakeupSourceEnable()
826 HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal; in PRCMLPDSWakeupSourceEnable()
847 HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc; in PRCMLPDSWakeupSourceDisable()
864 return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC)); in PRCMLPDSWakeupCauseGet()
892 HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks; in PRCMLPDSIntervalSet()
893 HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20; in PRCMLPDSIntervalSet()
936 HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3); in PRCMLPDSWakeUpGPIOSelect()
992 HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF); in PRCMSRAMRetentionEnable()
1028 HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF); in PRCMSRAMRetentionDisable()
1156 if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) in PRCMHibernateWakeupCauseGet()
1349 ullRTCVal = HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_MSW_1P2); in PRCMSlowClkCtrFastGet()
1351 ullRTCVal |= HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_LSW_1P2); in PRCMSlowClkCtrFastGet()
1497 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && in PRCMOCRRegisterWrite()
1537 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && in PRCMOCRRegisterRead()
1624 HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4; in PRCMIntEnable()
1660 HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4; in PRCMIntDisable()
1683 return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS); in PRCMIntStatus()
1886 if( 0x00010001 == HWREG(0x00000400) ) in PRCMCC3200MCUInit()
1896 HWREG(0x4402F010) = 0x30031820; in PRCMCC3200MCUInit()
1897 HWREG(0x4402F00C) = 0x04000000; in PRCMCC3200MCUInit()
1904 HWREG(0x4402F11C) = 0x099; in PRCMCC3200MCUInit()
1905 HWREG(0x4402F11C) = 0x0AA; in PRCMCC3200MCUInit()
1906 HWREG(0x4402F11C) = 0x1AA; in PRCMCC3200MCUInit()
1911 HWREG(0x4402F124) = 0x099; in PRCMCC3200MCUInit()
1912 HWREG(0x4402F124) = 0x0AA; in PRCMCC3200MCUInit()
1913 HWREG(0x4402F124) = 0x1AA; in PRCMCC3200MCUInit()
1918 if((HWREG(0x4402D00C) & 0xFF) == 0x00000005) in PRCMCC3200MCUInit()
1920 HWREG(0x400F707C) |= 0x01840082; in PRCMCC3200MCUInit()
1921 HWREG(0x400F70C4)= 0x1; in PRCMCC3200MCUInit()
1922 HWREG(0x400F70C4)= 0x0; in PRCMCC3200MCUInit()
1928 ulRegVal = HWREG(0x400F7000); in PRCMCC3200MCUInit()
1930 HWREG(0x400F7000) = ulRegVal; in PRCMCC3200MCUInit()
1935 ulRegVal = HWREG(0x400F703C); in PRCMCC3200MCUInit()
1937 HWREG(0x400F703C) = ulRegVal; in PRCMCC3200MCUInit()
1952 HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008; in PRCMCC3200MCUInit()
1970 HWREG(0x4402F064) |= 0x800000; in PRCMCC3200MCUInit()
1983 HWREG(0x4402E16C) |= 0x3C; in PRCMCC3200MCUInit()
2013 if(((HWREG(0x4402F0C8) & 0xFF) == 0x2)) in PRCMCC3200MCUInit()
2015 HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2); in PRCMCC3200MCUInit()
2016 HWREG(0x4402E114) = ((HWREG(0x4402E114) & ~0xC0F) | 0x2); in PRCMCC3200MCUInit()
2022 HWREG(0x4402E184) |= 0x2; in PRCMCC3200MCUInit()
2051 if(((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE) in PRCMCC3200MCUInit()
2053 HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18)); in PRCMCC3200MCUInit()
2057 HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18)); in PRCMCC3200MCUInit()
2063 HWREG(0x4402FC74) &= ~(0x10000000); in PRCMCC3200MCUInit()
2068 if( (HWREG(0x00000400) & 0xFFFF) < 2 ) in PRCMCC3200MCUInit()
2073 HWREG(0x4402F0A8) |= 0x00000004 ; in PRCMCC3200MCUInit()
2075 else if( (HWREG(0x00000400) >> 16) >= 1 ) in PRCMCC3200MCUInit()
2081 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1); in PRCMCC3200MCUInit()
2082 if((HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) & 0x1) ) in PRCMCC3200MCUInit()
2084 HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) &= ~0x1; in PRCMCC3200MCUInit()
2085 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9); in PRCMCC3200MCUInit()
2090 HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN) &= ~0x1; in PRCMCC3200MCUInit()
2095 HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF) = 0; in PRCMCC3200MCUInit()
2096 HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF) = 0; in PRCMCC3200MCUInit()
2106 efuse_reg2= HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); in PRCMCC3200MCUInit()
2119 PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; in PRCMCC3200MCUInit()
2123 Scratch = HWREG(0x4402F028); in PRCMCC3200MCUInit()
2125 HWREG(0x4402F028) = Scratch; in PRCMCC3200MCUInit()
2127 Scratch = HWREG(0x4402F010); in PRCMCC3200MCUInit()
2130 HWREG(0x4402F010) = Scratch; in PRCMCC3200MCUInit()
2134 Scratch = HWREG(0x4402F024); in PRCMCC3200MCUInit()
2143 HWREG(0x4402F024) = Scratch; in PRCMCC3200MCUInit()
2145 Scratch = HWREG(0x4402F028); in PRCMCC3200MCUInit()
2154 HWREG(0x4402F028) = Scratch; in PRCMCC3200MCUInit()
2155 HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 in PRCMCC3200MCUInit()
2163 PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; in PRCMCC3200MCUInit()
2165 Scratch = HWREG(0x4402F028); in PRCMCC3200MCUInit()
2167 HWREG(0x4402F028) = Scratch; in PRCMCC3200MCUInit()
2169 HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 in PRCMCC3200MCUInit()
2172 HWREG(0x4402F010) |= 0x10000000; // <31:28> = 1 in PRCMCC3200MCUInit()
2183 ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); in PRCMCC3200MCUInit()
2185 HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal; in PRCMCC3200MCUInit()
2190 ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register); in PRCMCC3200MCUInit()
2192 HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal; in PRCMCC3200MCUInit()
2216 ulValue = HWREG(ulRegAddr); in PRCMHIBRegRead()
2247 HWREG(ulRegAddr) = ulValue; in PRCMHIBRegWrite()
2292 HWREG(ARCM_BASE + in PRCMCameraFreqSet()
2298 HWREG(ARCM_BASE + in PRCMCameraFreqSet()
2342 if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) in PRCMIORetentionEnable()
2347 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001D00; in PRCMIORetentionEnable()
2353 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023); in PRCMIORetentionEnable()
2427 if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) in PRCMIORetentionDisable()
2433 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001D00); in PRCMIORetentionDisable()
2439 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00000023; in PRCMIORetentionDisable()
2533 ulChipId = HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); in PRCMDeviceTypeGet()
2542 ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); in PRCMDeviceTypeGet()