74     HWREG(UDMA_BASE + UDMA_O_CFG) = UDMA_CFG_MASTEN;  in uDMAEnable()
93     HWREG(UDMA_BASE + UDMA_O_CFG) = 0;  in uDMADisable()
113     return(HWREG(UDMA_BASE + UDMA_O_ERRCLR));  in uDMAErrorStatusGet()
133     HWREG(UDMA_BASE + UDMA_O_ERRCLR) = 1;  in uDMAErrorStatusClear()
164     HWREG(UDMA_BASE + UDMA_O_ENASET) = 1 << (ulChannelNum & 0x1f);  in uDMAChannelEnable()
191     HWREG(UDMA_BASE + UDMA_O_ENACLR) = 1 << (ulChannelNum & 0x1f);  in uDMAChannelDisable()
219     return((HWREG(UDMA_BASE + UDMA_O_ENASET) &  in uDMAChannelIsEnabled()
256     HWREG(UDMA_BASE + UDMA_O_CTLBASE) = (unsigned long)pControlTable;  in uDMAControlBaseSet()
277     return((void *)HWREG(UDMA_BASE + UDMA_O_CTLBASE));  in uDMAControlBaseGet()
298     return((void *)HWREG(UDMA_BASE + UDMA_O_ALTBASE));  in uDMAControlAlternateBaseGet()
332     HWREG(UDMA_BASE + UDMA_O_SWREQ) = 1 << (ulChannelNum & 0x1f);  in uDMAChannelRequest()
379         HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) = 1 << ulChannelNum;  in uDMAChannelAttributeEnable()
388         HWREG(UDMA_BASE + UDMA_O_ALTSET) = 1 << ulChannelNum;  in uDMAChannelAttributeEnable()
396         HWREG(UDMA_BASE + UDMA_O_PRIOSET) = 1 << ulChannelNum;  in uDMAChannelAttributeEnable()
404         HWREG(UDMA_BASE + UDMA_O_REQMASKSET) = 1 << ulChannelNum;  in uDMAChannelAttributeEnable()
452         HWREG(UDMA_BASE + UDMA_O_USEBURSTCLR) = 1 << ulChannelNum;  in uDMAChannelAttributeDisable()
461         HWREG(UDMA_BASE + UDMA_O_ALTCLR) = 1 << ulChannelNum;  in uDMAChannelAttributeDisable()
469         HWREG(UDMA_BASE + UDMA_O_PRIOCLR) = 1 << ulChannelNum;  in uDMAChannelAttributeDisable()
477         HWREG(UDMA_BASE + UDMA_O_REQMASKCLR) = 1 << ulChannelNum;  in uDMAChannelAttributeDisable()
521     if(HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) & (1 << ulChannelNum))  in uDMAChannelAttributeGet()
529     if(HWREG(UDMA_BASE + UDMA_O_ALTSET) & (1 << ulChannelNum))  in uDMAChannelAttributeGet()
537     if(HWREG(UDMA_BASE + UDMA_O_PRIOSET) & (1 << ulChannelNum))  in uDMAChannelAttributeGet()
545     if(HWREG(UDMA_BASE + UDMA_O_REQMASKSET) & (1 << ulChannelNum))  in uDMAChannelAttributeGet()
614     ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0);  in uDMAChannelControlSet()
626     pCtl = (tDMAControlTable *)HWREG(UDMA_BASE+UDMA_O_CTLBASE);  in uDMAChannelControlSet()
728     ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0);  in uDMAChannelTransferSet()
744     pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE);  in uDMAChannelTransferSet()
876     ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0);  in uDMAChannelScatterGatherSet()
891     pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE);  in uDMAChannelScatterGatherSet()
953     ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0);  in uDMAChannelSizeGet()
965     pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE);  in uDMAChannelSizeGet()
1023     ASSERT(HWREG(UDMA_O_CTLBASE) != 0);  in uDMAChannelModeGet()
1035     pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE);  in uDMAChannelModeGet()
1164     return(HWREG(UDMA_BASE + UDMA_O_CHIS));  in uDMAIntStatus()
1192     HWREG(UDMA_BASE + UDMA_O_CHIS) = ulChanMask;  in uDMAIntClear()
1248     HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) |  in uDMAChannelAssign()