90   ulReg = HWREG(ulBase + MCASP_O_GBLCTL);  in I2SGBLEnable()
100   HWREG(ulBase + MCASP_O_GBLCTL) = ulReg;  in I2SGBLEnable()
105   while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg)  in I2SGBLEnable()
133   if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20)  in I2SEnable()
138     HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000;  in I2SEnable()
217   HWREG(ulBase + MCASP_O_GBLCTL) = 0;  in I2SDisable()
222   while( HWREG(ulBase + MCASP_O_GBLCTL) != 0)  in I2SDisable()
254   while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA))  in I2SDataPut()
262   HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData;  in I2SDataPut()
293   if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)  in I2SDataPutNonBlocking()
298     HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData;  in I2SDataPutNonBlocking()
335   while(!(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA))  in I2SDataGet()
343   *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine);  in I2SDataGet()
374   if(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA)  in I2SDataGetNonBlocking()
379     *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine);  in I2SDataGetNonBlocking()
453   HWREG(ulBase + MCASP_O_ACLKXCTL) = ulClkDiv;  in I2SConfigSetExpClk()
455   HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv);  in I2SConfigSetExpClk()
460   HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0x7FFF));  in I2SConfigSetExpClk()
465   HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0x7FFF));  in I2SConfigSetExpClk()
475     HWREG(ulBase + MCASP_O_TXFMCTL) = 0x111;  in I2SConfigSetExpClk()
480     HWREG(ulBase + MCASP_O_RXFMCTL) = 0x111;  in I2SConfigSetExpClk()
487     HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113;  in I2SConfigSetExpClk()
492     HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113;  in I2SConfigSetExpClk()
508   HWREG(ulBase + MCASP_O_TXMASK) = ulBitMask;  in I2SConfigSetExpClk()
513   HWREG(ulBase + MCASP_O_RXMASK) = ulBitMask;  in I2SConfigSetExpClk()
518   HWREG(ulBase + MCASP_O_TXTDM) = 0x3;  in I2SConfigSetExpClk()
523   HWREG(ulBase + MCASP_O_RXTDM) = 0x3;  in I2SConfigSetExpClk()
554   HWREG(ulBase + MCASP_0_WFIFOCTL) = ((1 <<16) | ((ulTxLevel & 0xFF) << 8)  in I2STxFIFOEnable()
575   HWREG(ulBase + MCASP_0_WFIFOCTL) = 0;  in I2STxFIFODisable()
605   HWREG(ulBase + MCASP_0_RFIFOCTL) = ( (1 <<16) | ((ulRxLevel & 0xFF) << 8)  in I2SRxFIFOEnable()
626   HWREG(ulBase + MCASP_0_RFIFOCTL) = 0;  in I2SRxFIFODisable()
646   return HWREG(ulBase + MCASP_0_WFIFOSTS);  in I2STxFIFOStatusGet()
666   return HWREG(ulBase + MCASP_0_RFIFOSTS);  in I2SRxFIFOStatusGet()
707     HWREG(ulBase + MCASP_O_PDIR) |= ulDataLine;  in I2SSerializerConfig()
714     HWREG(ulBase + MCASP_O_PDIR) &= ~ulDataLine;  in I2SSerializerConfig()
720   HWREG(ulBase + MCASP_O_XRSRCTL0 + ((ulDataLine-1) << 2))  in I2SSerializerConfig()
759   HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR )  in I2SIntEnable()
765   HWREG(ulBase + MCASP_O_EVTCTLX) |= (ulIntFlags & 0xFF);  in I2SIntEnable()
770   HWREG(ulBase + MCASP_O_EVTCTLR) |= ((ulIntFlags >> 16) & 0xFF);  in I2SIntEnable()
795   HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET)  in I2SIntDisable()
801   HWREG(ulBase + MCASP_O_EVTCTLX) &= ~(ulIntFlags & 0xFF);  in I2SIntDisable()
806   HWREG(ulBase + MCASP_O_EVTCTLR) &= ~((ulIntFlags >> 16) & 0xFF);  in I2SIntDisable()
847     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW) << 20;  in I2SIntStatus()
854   ulStatus |= HWREG(ulBase + MCASP_O_TXSTAT);  in I2SIntStatus()
859   ulStatus |= HWREG(ulBase + MCASP_O_RXSTAT) << 16;  in I2SIntStatus()
889   HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK)  in I2SIntClear()
895   HWREG(ulBase + MCASP_O_TXSTAT) = ulStatFlags & 0x1FF ;  in I2SIntClear()
900   HWREG(ulBase + MCASP_O_RXSTAT) = (ulStatFlags >> 16) & 0x1FF;  in I2SIntClear()
984    HWREG(ulBase + MCASP_O_TXTDM) = ulActSlot;  in I2STxActiveSlotSet()
1005    HWREG(ulBase + MCASP_O_RXTDM) = ulActSlot;  in I2SRxActiveSlotSet()