204     HWREG(ui32Base + I2C_O_MTPR) = ui32TPR;  in I2CMasterInitExpClk()
210     if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS)  in I2CMasterInitExpClk()
214         HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR;  in I2CMasterInitExpClk()
251     HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;  in I2CSlaveInit()
290             HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;  in I2CSlaveAddressSet()
299             HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr;  in I2CSlaveAddressSet()
327     HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE;  in I2CMasterEnable()
352     HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE;  in I2CSlaveEnable()
357     HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;  in I2CSlaveEnable()
382     HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE);  in I2CMasterDisable()
407     HWREG(ui32Base + I2C_O_SCSR) = 0;  in I2CSlaveDisable()
412     HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE);  in I2CSlaveDisable()
530     HWREG(ui32Base + I2C_O_MIMR) = 1;  in I2CMasterIntEnable()
574     HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags;  in I2CMasterIntEnableEx()
599     HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;  in I2CSlaveIntEnable()
640     HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags;  in I2CSlaveIntEnableEx()
665     HWREG(ui32Base + I2C_O_MIMR) = 0;  in I2CMasterIntDisable()
697     HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags;  in I2CMasterIntDisableEx()
722     HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;  in I2CSlaveIntDisable()
754     HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags;  in I2CSlaveIntDisableEx()
787         return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);  in I2CMasterIntStatus()
791         return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);  in I2CMasterIntStatus()
825         return(HWREG(ui32Base + I2C_O_MMIS));  in I2CMasterIntStatusEx()
829         return(HWREG(ui32Base + I2C_O_MRIS));  in I2CMasterIntStatusEx()
863         return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false);  in I2CSlaveIntStatus()
867         return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false);  in I2CSlaveIntStatus()
901         return(HWREG(ui32Base + I2C_O_SMIS));  in I2CSlaveIntStatusEx()
905         return(HWREG(ui32Base + I2C_O_SRIS));  in I2CSlaveIntStatusEx()
942     HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;  in I2CMasterIntClear()
949     HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC;  in I2CMasterIntClear()
989     HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags;  in I2CMasterIntClearEx()
1025     HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC;  in I2CSlaveIntClear()
1065     HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;  in I2CSlaveIntClearEx()
1098     HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;  in I2CMasterSlaveAddrSet()
1126     return(HWREG(ui32Base + I2C_O_MBMON));  in I2CMasterLineStateGet()
1153     if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY)  in I2CMasterBusy()
1188     if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY)  in I2CMasterBusBusy()
1269     HWREG(ui32Base + I2C_O_MCS) = ui32Cmd;  in I2CMasterControl()
1299     ui32Err = HWREG(ui32Base + I2C_O_MCS);  in I2CMasterErr()
1346     HWREG(ui32Base + I2C_O_MDR) = ui8Data;  in I2CMasterDataPut()
1372     return(HWREG(ui32Base + I2C_O_MDR));  in I2CMasterDataGet()
1403     HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value;  in I2CMasterTimeoutSet()
1433         HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN;  in I2CSlaveACKOverride()
1437         HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN;  in I2CSlaveACKOverride()
1468         HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL;  in I2CSlaveACKValueSet()
1472         HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL;  in I2CSlaveACKValueSet()
1520     return(HWREG(ui32Base + I2C_O_SCSR));  in I2CSlaveStatus()
1546     HWREG(ui32Base + I2C_O_SDR) = ui8Data;  in I2CSlaveDataPut()
1572     return(HWREG(ui32Base + I2C_O_SDR));  in I2CSlaveDataGet()
1612     HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000;  in I2CTxFIFOConfigSet()
1617     HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;  in I2CTxFIFOConfigSet()
1643     HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH;  in I2CTxFIFOFlush()
1682     HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff;  in I2CRxFIFOConfigSet()
1687     HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;  in I2CRxFIFOConfigSet()
1712     HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH;  in I2CRxFIFOFlush()
1742     return(HWREG(ui32Base + I2C_O_FIFOSTATUS));  in I2CFIFOStatus()
1770     while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)  in I2CFIFODataPut()
1777     HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;  in I2CFIFODataPut()
1804     if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)  in I2CFIFODataPutNonBlocking()
1810         HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;  in I2CFIFODataPutNonBlocking()
1839     while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)  in I2CFIFODataGet()
1846     return(HWREG(ui32Base + I2C_O_FIFODATA));  in I2CFIFODataGet()
1874     if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)  in I2CFIFODataGetNonBlocking()
1880         *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA);  in I2CFIFODataGetNonBlocking()
1913     HWREG(ui32Base + I2C_O_MBLEN) = ui8Length;  in I2CMasterBurstLengthSet()
1941     return(HWREG(ui32Base + I2C_O_MBCNT));  in I2CMasterBurstCountGet()
1982     HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;  in I2CMasterGlitchFilterConfigSet()
2019     HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA;  in I2CSlaveFIFOEnable()
2045     HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;  in I2CSlaveFIFODisable()