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Searched refs:TSC_IOSCR_G5_IO4_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5728 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
5729 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f051x8.h5759 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
5760 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f071xb.h6312 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6313 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f042x6.h9534 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
9535 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f048xx.h9498 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
9499 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f072xb.h10109 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
10110 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f091xc.h10766 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
10767 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f098xx.h10733 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
10734 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f078xx.h10079 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
10080 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6285 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6286 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l062xx.h6422 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6423 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l053xx.h6444 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6445 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l072xx.h6581 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6582 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l073xx.h6740 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6741 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l083xx.h6877 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6878 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l063xx.h6579 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6580 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l082xx.h6718 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
6719 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7546 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
7547 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f318xx.h7533 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
7534 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9399 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
9400 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8756 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
8757 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32u083xx.h9693 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
9694 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8187 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
8188 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8015 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
8016 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32wb15xx.h8187 #define TSC_IOSCR_G5_IO4_Pos (19U) macro
8188 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */

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