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Searched refs:TSC_IOSCR_G5_IO3_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5725 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
5726 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f051x8.h5756 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
5757 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f071xb.h6309 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6310 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f042x6.h9531 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
9532 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f048xx.h9495 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
9496 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f072xb.h10106 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
10107 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f091xc.h10763 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
10764 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f098xx.h10730 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
10731 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f078xx.h10076 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
10077 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6282 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6283 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l062xx.h6419 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6420 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l053xx.h6441 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6442 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l072xx.h6578 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6579 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l073xx.h6737 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6738 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l083xx.h6874 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6875 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l063xx.h6576 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6577 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l082xx.h6715 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
6716 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7543 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
7544 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f318xx.h7530 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
7531 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9396 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
9397 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8753 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
8754 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32u083xx.h9690 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
9691 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8184 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
8185 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8012 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
8013 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32wb15xx.h8184 #define TSC_IOSCR_G5_IO3_Pos (18U) macro
8185 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */

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