Home
last modified time | relevance | path

Searched refs:TSC_IOSCR_G5_IO2_Pos (Results 1 – 25 of 81) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5722 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
5723 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f051x8.h5753 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
5754 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f071xb.h6306 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6307 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f042x6.h9528 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
9529 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f048xx.h9492 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
9493 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f072xb.h10103 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
10104 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f091xc.h10760 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
10761 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f098xx.h10727 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
10728 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f078xx.h10073 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
10074 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6279 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6280 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l062xx.h6416 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6417 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l053xx.h6438 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6439 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l072xx.h6575 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6576 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l073xx.h6734 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6735 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l083xx.h6871 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6872 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l063xx.h6573 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6574 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l082xx.h6712 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
6713 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7540 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
7541 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f318xx.h7527 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
7528 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9393 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
9394 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8750 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
8751 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32u083xx.h9687 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
9688 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8181 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
8182 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8009 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
8010 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32wb15xx.h8181 #define TSC_IOSCR_G5_IO2_Pos (17U) macro
8182 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */

1234