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Searched refs:TSC_IOSCR_G5_IO1_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5719 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
5720 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f051x8.h5750 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
5751 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f071xb.h6303 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6304 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f042x6.h9525 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
9526 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f048xx.h9489 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
9490 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f072xb.h10100 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
10101 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f091xc.h10757 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
10758 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f098xx.h10724 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
10725 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f078xx.h10070 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
10071 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6276 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6277 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l062xx.h6413 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6414 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l053xx.h6435 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6436 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l072xx.h6572 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6573 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l073xx.h6731 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6732 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l083xx.h6868 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6869 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l063xx.h6570 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6571 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l082xx.h6709 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
6710 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7537 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
7538 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f318xx.h7524 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
7525 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9390 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
9391 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8747 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
8748 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32u083xx.h9684 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
9685 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8178 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
8179 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8006 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
8007 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32wb15xx.h8178 #define TSC_IOSCR_G5_IO1_Pos (16U) macro
8179 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */

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