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Searched refs:TSC_IOSCR_G2_IO1_Pos (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5683 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
5684 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f051x8.h5714 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
5715 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f071xb.h6267 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6268 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f042x6.h9489 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
9490 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f048xx.h9453 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
9454 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f072xb.h10064 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
10065 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f091xc.h10721 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
10722 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f098xx.h10688 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
10689 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f078xx.h10034 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
10035 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6240 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6241 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l062xx.h6377 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6378 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l053xx.h6399 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6400 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l072xx.h6536 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6537 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l073xx.h6695 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6696 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l083xx.h6832 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6833 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l063xx.h6534 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6535 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l082xx.h6673 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
6674 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7501 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
7502 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f318xx.h7488 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
7489 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9354 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
9355 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8711 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
8712 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32u083xx.h9648 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
9649 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8142 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
8143 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7970 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
7971 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32wb15xx.h8142 #define TSC_IOSCR_G2_IO1_Pos (4U) macro
8143 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */

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