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Searched refs:TSC_IOGCSR_G5S_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5903 #define TSC_IOGCSR_G5S_Pos (20U) macro
5904 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f051x8.h5934 #define TSC_IOGCSR_G5S_Pos (20U) macro
5935 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f071xb.h6487 #define TSC_IOGCSR_G5S_Pos (20U) macro
6488 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f042x6.h9709 #define TSC_IOGCSR_G5S_Pos (20U) macro
9710 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f048xx.h9673 #define TSC_IOGCSR_G5S_Pos (20U) macro
9674 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f072xb.h10284 #define TSC_IOGCSR_G5S_Pos (20U) macro
10285 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f091xc.h10941 #define TSC_IOGCSR_G5S_Pos (20U) macro
10942 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f098xx.h10908 #define TSC_IOGCSR_G5S_Pos (20U) macro
10909 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f078xx.h10254 #define TSC_IOGCSR_G5S_Pos (20U) macro
10255 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6460 #define TSC_IOGCSR_G5S_Pos (20U) macro
6461 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l062xx.h6597 #define TSC_IOGCSR_G5S_Pos (20U) macro
6598 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l053xx.h6619 #define TSC_IOGCSR_G5S_Pos (20U) macro
6620 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l072xx.h6756 #define TSC_IOGCSR_G5S_Pos (20U) macro
6757 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l073xx.h6915 #define TSC_IOGCSR_G5S_Pos (20U) macro
6916 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l083xx.h7052 #define TSC_IOGCSR_G5S_Pos (20U) macro
7053 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l063xx.h6754 #define TSC_IOGCSR_G5S_Pos (20U) macro
6755 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32l082xx.h6893 #define TSC_IOGCSR_G5S_Pos (20U) macro
6894 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7721 #define TSC_IOGCSR_G5S_Pos (20U) macro
7722 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32f318xx.h7708 #define TSC_IOGCSR_G5S_Pos (20U) macro
7709 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9508 #define TSC_IOGCSR_G5S_Pos (20U) macro
9509 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8904 #define TSC_IOGCSR_G5S_Pos (20U) macro
8905 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32u083xx.h9841 #define TSC_IOGCSR_G5S_Pos (20U) macro
9842 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8335 #define TSC_IOGCSR_G5S_Pos (20U) macro
8336 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8163 #define TSC_IOGCSR_G5S_Pos (20U) macro
8164 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
Dstm32wb15xx.h8335 #define TSC_IOGCSR_G5S_Pos (20U) macro
8336 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */

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