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Searched refs:TSC_IOCCR_G5_IO4_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5826 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
5827 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f051x8.h5857 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
5858 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f071xb.h6410 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6411 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f042x6.h9632 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
9633 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f048xx.h9596 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
9597 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f072xb.h10207 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
10208 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f091xc.h10864 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
10865 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f098xx.h10831 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
10832 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f078xx.h10177 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
10178 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6383 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6384 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l062xx.h6520 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6521 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l053xx.h6542 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6543 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l072xx.h6679 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6680 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l073xx.h6838 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6839 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l083xx.h6975 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6976 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l063xx.h6677 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6678 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l082xx.h6816 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
6817 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7644 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
7645 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f318xx.h7631 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
7632 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9467 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
9468 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8842 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
8843 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32u083xx.h9779 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
9780 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8273 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
8274 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8101 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
8102 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32wb15xx.h8273 #define TSC_IOCCR_G5_IO4_Pos (19U) macro
8274 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */

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