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Searched refs:TSC_IOCCR_G5_IO3_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5823 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
5824 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f051x8.h5854 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
5855 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f071xb.h6407 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6408 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f042x6.h9629 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
9630 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f048xx.h9593 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
9594 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f072xb.h10204 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
10205 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f091xc.h10861 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
10862 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f098xx.h10828 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
10829 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f078xx.h10174 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
10175 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6380 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6381 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l062xx.h6517 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6518 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l053xx.h6539 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6540 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l072xx.h6676 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6677 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l073xx.h6835 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6836 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l083xx.h6972 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6973 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l063xx.h6674 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6675 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l082xx.h6813 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
6814 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7641 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
7642 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f318xx.h7628 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
7629 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9464 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
9465 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8839 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
8840 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32u083xx.h9776 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
9777 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8270 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
8271 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8098 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
8099 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32wb15xx.h8270 #define TSC_IOCCR_G5_IO3_Pos (18U) macro
8271 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */

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