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Searched refs:TSC_IOCCR_G5_IO1_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5817 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
5818 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f051x8.h5848 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
5849 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f071xb.h6401 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6402 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f042x6.h9623 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
9624 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f048xx.h9587 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
9588 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f072xb.h10198 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
10199 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f091xc.h10855 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
10856 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f098xx.h10822 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
10823 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f078xx.h10168 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
10169 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6374 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6375 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l062xx.h6511 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6512 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l053xx.h6533 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6534 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l072xx.h6670 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6671 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l073xx.h6829 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6830 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l083xx.h6966 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6967 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l063xx.h6668 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6669 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l082xx.h6807 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
6808 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7635 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
7636 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f318xx.h7622 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
7623 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9458 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
9459 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8833 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
8834 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32u083xx.h9770 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
9771 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8264 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
8265 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8092 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
8093 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32wb15xx.h8264 #define TSC_IOCCR_G5_IO1_Pos (16U) macro
8265 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */

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