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Searched refs:TSC_IOCCR_G2_IO1_Pos (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5781 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
5782 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f051x8.h5812 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
5813 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f071xb.h6365 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6366 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f042x6.h9587 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
9588 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f048xx.h9551 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
9552 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f072xb.h10162 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
10163 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f091xc.h10819 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
10820 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f098xx.h10786 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
10787 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f078xx.h10132 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
10133 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6338 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6339 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l062xx.h6475 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6476 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l053xx.h6497 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6498 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l072xx.h6634 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6635 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l073xx.h6793 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6794 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l083xx.h6930 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6931 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l063xx.h6632 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6633 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32l082xx.h6771 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
6772 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7599 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
7600 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32f318xx.h7586 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
7587 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9422 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
9423 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8797 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
8798 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32u083xx.h9734 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
9735 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8228 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
8229 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h8056 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
8057 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
Dstm32wb15xx.h8228 #define TSC_IOCCR_G2_IO1_Pos (4U) macro
8229 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */

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