/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5633 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 5634 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f051x8.h | 5664 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 5665 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f071xb.h | 6217 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6218 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f042x6.h | 9439 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 9440 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f048xx.h | 9403 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 9404 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f072xb.h | 10014 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 10015 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f091xc.h | 10671 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 10672 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f098xx.h | 10638 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 10639 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f078xx.h | 9984 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 9985 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6190 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6191 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l062xx.h | 6327 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6328 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l053xx.h | 6349 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6350 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l072xx.h | 6486 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6487 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l073xx.h | 6645 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6646 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l083xx.h | 6782 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6783 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l063xx.h | 6484 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6485 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32l082xx.h | 6623 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 6624 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7451 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 7452 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32f318xx.h | 7438 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 7439 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9334 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 9335 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8673 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 8674 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32u083xx.h | 9610 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 9611 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8104 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 8105 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7932 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 7933 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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D | stm32wb15xx.h | 8104 #define TSC_IOASCR_G6_IO1_Pos (20U) macro 8105 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
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