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Searched refs:TSC_IOASCR_G5_IO4_Pos (Results 1 – 25 of 81) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5630 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
5631 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f051x8.h5661 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
5662 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f071xb.h6214 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6215 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f042x6.h9436 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
9437 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f048xx.h9400 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
9401 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f072xb.h10011 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
10012 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f091xc.h10668 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
10669 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f098xx.h10635 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
10636 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f078xx.h9981 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
9982 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6187 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6188 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l062xx.h6324 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6325 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l053xx.h6346 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6347 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l072xx.h6483 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6484 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l073xx.h6642 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6643 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l083xx.h6779 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6780 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l063xx.h6481 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6482 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32l082xx.h6620 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
6621 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7448 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
7449 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32f318xx.h7435 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
7436 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9331 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
9332 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8670 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
8671 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32u083xx.h9607 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
9608 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8101 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
8102 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7929 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
7930 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
Dstm32wb15xx.h8101 #define TSC_IOASCR_G5_IO4_Pos (19U) macro
8102 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */

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