Home
last modified time | relevance | path

Searched refs:TSC_IOASCR_G5_IO3_Pos (Results 1 – 25 of 81) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5627 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
5628 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f051x8.h5658 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
5659 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f071xb.h6211 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6212 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f042x6.h9433 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
9434 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f048xx.h9397 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
9398 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f072xb.h10008 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
10009 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f091xc.h10665 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
10666 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f098xx.h10632 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
10633 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f078xx.h9978 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
9979 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6184 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6185 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l062xx.h6321 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6322 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l053xx.h6343 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6344 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l072xx.h6480 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6481 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l073xx.h6639 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6640 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l083xx.h6776 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6777 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l063xx.h6478 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6479 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32l082xx.h6617 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
6618 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7445 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
7446 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32f318xx.h7432 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
7433 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9328 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
9329 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8667 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
8668 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32u083xx.h9604 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
9605 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8098 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
8099 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7926 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
7927 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
Dstm32wb15xx.h8098 #define TSC_IOASCR_G5_IO3_Pos (18U) macro
8099 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */

1234