Home
last modified time | relevance | path

Searched refs:TSC_IOASCR_G5_IO2_Pos (Results 1 – 25 of 81) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5624 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
5625 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f051x8.h5655 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
5656 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f071xb.h6208 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6209 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f042x6.h9430 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
9431 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f048xx.h9394 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
9395 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f072xb.h10005 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
10006 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f091xc.h10662 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
10663 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f098xx.h10629 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
10630 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f078xx.h9975 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
9976 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6181 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6182 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l062xx.h6318 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6319 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l053xx.h6340 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6341 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l072xx.h6477 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6478 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l073xx.h6636 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6637 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l083xx.h6773 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6774 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l063xx.h6475 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6476 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32l082xx.h6614 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
6615 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7442 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
7443 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32f318xx.h7429 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
7430 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9325 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
9326 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8664 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
8665 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32u083xx.h9601 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
9602 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8095 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
8096 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7923 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
7924 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
Dstm32wb15xx.h8095 #define TSC_IOASCR_G5_IO2_Pos (17U) macro
8096 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */

1234