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Searched refs:TSC_IOASCR_G4_IO4_Pos (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5618 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
5619 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f051x8.h5649 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
5650 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f071xb.h6202 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6203 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f042x6.h9424 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
9425 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f048xx.h9388 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
9389 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f072xb.h9999 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
10000 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f091xc.h10656 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
10657 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f098xx.h10623 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
10624 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f078xx.h9969 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
9970 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6175 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6176 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l062xx.h6312 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6313 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l053xx.h6334 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6335 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l072xx.h6471 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6472 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l073xx.h6630 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6631 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l083xx.h6767 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6768 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l063xx.h6469 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6470 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32l082xx.h6608 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
6609 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7436 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
7437 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32f318xx.h7423 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
7424 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9319 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
9320 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8658 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
8659 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32u083xx.h9595 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
9596 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8089 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
8090 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7917 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
7918 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
Dstm32wb15xx.h8089 #define TSC_IOASCR_G4_IO4_Pos (15U) macro
8090 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */

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