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Searched refs:TSC_IOASCR_G4_IO1_Pos (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5609 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
5610 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f051x8.h5640 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
5641 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f071xb.h6193 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6194 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f042x6.h9415 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
9416 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f048xx.h9379 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
9380 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f072xb.h9990 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
9991 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f091xc.h10647 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
10648 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f098xx.h10614 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
10615 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f078xx.h9960 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
9961 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6166 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6167 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l062xx.h6303 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6304 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l053xx.h6325 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6326 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l072xx.h6462 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6463 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l073xx.h6621 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6622 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l083xx.h6758 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6759 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l063xx.h6460 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6461 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32l082xx.h6599 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
6600 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7427 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
7428 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32f318xx.h7414 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
7415 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9310 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
9311 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8649 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
8650 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32u083xx.h9586 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
9587 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8080 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
8081 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7908 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
7909 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
Dstm32wb15xx.h8080 #define TSC_IOASCR_G4_IO1_Pos (12U) macro
8081 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */

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