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Searched refs:TSC_IOASCR_G3_IO4_Pos (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5606 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
5607 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f051x8.h5637 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
5638 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f071xb.h6190 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6191 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f042x6.h9412 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
9413 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f048xx.h9376 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
9377 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f072xb.h9987 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
9988 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f091xc.h10644 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
10645 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f098xx.h10611 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
10612 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f078xx.h9957 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
9958 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h6163 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6164 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l062xx.h6300 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6301 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l053xx.h6322 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6323 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l072xx.h6459 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6460 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l073xx.h6618 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6619 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l083xx.h6755 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6756 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l063xx.h6457 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6458 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32l082xx.h6596 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
6597 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7424 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
7425 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32f318xx.h7411 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
7412 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9307 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
9308 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8646 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
8647 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32u083xx.h9583 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
9584 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8077 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
8078 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7905 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
7906 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
Dstm32wb15xx.h8077 #define TSC_IOASCR_G3_IO4_Pos (11U) macro
8078 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */

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