/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5603 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 5604 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f051x8.h | 5634 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 5635 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f071xb.h | 6187 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6188 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f042x6.h | 9409 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 9410 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f048xx.h | 9373 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 9374 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f072xb.h | 9984 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 9985 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f091xc.h | 10641 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 10642 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f098xx.h | 10608 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 10609 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f078xx.h | 9954 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 9955 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6160 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6161 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l062xx.h | 6297 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6298 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l053xx.h | 6319 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6320 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l072xx.h | 6456 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6457 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l073xx.h | 6615 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6616 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l083xx.h | 6752 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6753 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l063xx.h | 6454 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6455 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32l082xx.h | 6593 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 6594 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7421 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 7422 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32f318xx.h | 7408 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 7409 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9304 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 9305 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8643 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 8644 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32u083xx.h | 9580 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 9581 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8074 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 8075 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7902 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 7903 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|
D | stm32wb15xx.h | 8074 #define TSC_IOASCR_G3_IO3_Pos (10U) macro 8075 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
|