/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5600 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 5601 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f051x8.h | 5631 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 5632 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f071xb.h | 6184 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6185 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f042x6.h | 9406 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 9407 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f048xx.h | 9370 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 9371 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f072xb.h | 9981 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 9982 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f091xc.h | 10638 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 10639 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f098xx.h | 10605 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 10606 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f078xx.h | 9951 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 9952 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6157 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6158 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l062xx.h | 6294 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6295 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l053xx.h | 6316 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6317 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l072xx.h | 6453 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6454 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l073xx.h | 6612 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6613 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l083xx.h | 6749 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6750 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l063xx.h | 6451 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6452 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32l082xx.h | 6590 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 6591 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7418 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 7419 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32f318xx.h | 7405 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 7406 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9301 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 9302 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8640 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 8641 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32u083xx.h | 9577 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 9578 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8071 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 8072 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7899 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 7900 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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D | stm32wb15xx.h | 8071 #define TSC_IOASCR_G3_IO2_Pos (9U) macro 8072 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
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