/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5594 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 5595 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f051x8.h | 5625 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 5626 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f071xb.h | 6178 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6179 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f042x6.h | 9400 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 9401 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f048xx.h | 9364 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 9365 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f072xb.h | 9975 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 9976 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f091xc.h | 10632 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 10633 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f098xx.h | 10599 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 10600 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f078xx.h | 9945 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 9946 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6151 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6152 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l062xx.h | 6288 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6289 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l053xx.h | 6310 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6311 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l072xx.h | 6447 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6448 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l073xx.h | 6606 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6607 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l083xx.h | 6743 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6744 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l063xx.h | 6445 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6446 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32l082xx.h | 6584 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 6585 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7412 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 7413 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32f318xx.h | 7399 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 7400 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9295 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 9296 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8634 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 8635 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32u083xx.h | 9571 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 9572 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8065 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 8066 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7893 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 7894 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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D | stm32wb15xx.h | 8065 #define TSC_IOASCR_G2_IO4_Pos (7U) macro 8066 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
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