/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5591 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 5592 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f051x8.h | 5622 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 5623 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f071xb.h | 6175 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6176 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f042x6.h | 9397 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 9398 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f048xx.h | 9361 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 9362 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f072xb.h | 9972 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 9973 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f091xc.h | 10629 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 10630 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f098xx.h | 10596 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 10597 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f078xx.h | 9942 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 9943 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6148 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6149 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l062xx.h | 6285 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6286 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l053xx.h | 6307 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6308 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l072xx.h | 6444 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6445 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l073xx.h | 6603 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6604 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l083xx.h | 6740 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6741 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l063xx.h | 6442 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6443 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32l082xx.h | 6581 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 6582 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7409 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 7410 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32f318xx.h | 7396 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 7397 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9292 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 9293 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8631 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 8632 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32u083xx.h | 9568 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 9569 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8062 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 8063 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7890 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 7891 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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D | stm32wb15xx.h | 8062 #define TSC_IOASCR_G2_IO3_Pos (6U) macro 8063 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
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